CN103280459A - Graphic strain NMOS (N-channel Metal Oxide Semiconductor) device with deep groove structure, and manufacturing method thereof - Google Patents

Abstract

The invention relates to a semiconductor technique, and provides a graphic strain NMOS (N-channel Metal Oxide Semiconductor) device with a deep groove structure, and a manufacturing method thereof, which are used for solving the problems of non-uniform distribution of groove strain caused by the adoption of a local strain technique and lower design flexibility caused by the adoption of a global strain technique device in the conventional strain NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor). According to the technical scheme, the graphic strain NMOS device with the deep groove structure comprises a source electrode, a drain electrode, a semiconductor substrate, a grid oxide layer, a source electrode expansion region, a source electrode heavily-doped region, a drain electrode expansion region, a drain electrode heavily-doped region, a grid electrode, a side wall, a deep isolation groove, top layer strain silicon and a medium layer, wherein the deep isolation groove is formed on the outer side of an active region; the top layer strain silicon is only positioned below a groove region; the medium layer is only positioned below the top layer strain silicon; and intrinsic tensile stress silicon nitride films are covered on the upper surfaces of the deep isolation groove, the source electrode heavily-doped region, the drain electrode heavily-doped region, the grid electrode and the side wall. The graphic strain NMOS device has the beneficial effects of larger and more uniform groove strain and suitability for strain NMOS devices.

Description

Patterned strained NMOS device with deep trench structure and method for manufacturing the same

technical field

The present invention relates to semiconductor technology, in particular to strained N-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs).

Background technique

In the era of the development of semiconductor integrated circuits to ultra-deep submicron, the carrier mobility and current driving capability of semiconductor devices can be improved by adopting strained silicon technology. Strain technology has attracted much attention due to its compatibility with traditional processes and its substantial improvement in performance. Introducing biaxial tensile stress parallel to the channel plane in the channel of N-type metal oxide semiconductor field effect transistor (NMOSFET) can improve device performance; introducing uniaxial tensile stress in the channel length direction can also improve device performance , and the drive capability of the device increases with the increase of stress.

The current strained silicon technology is mainly divided into global strain technology and local strain technology. Local strain techniques typically introduce stress only in localized regions of the semiconductor device. Local strain technology mainly includes germanium silicon source drain (SiGe S/D) or carbon silicon source drain (SiC S/D), double stress layer (strained silicon nitride capping technology CESL), stress memory technology (Stress Memorization Technique, SMT) And shallow trench isolation (Shallow Trench Isolation, STI), etc., the cross-sectional schematic diagram of the existing local strain MOS device is shown in Figure 1, which includes semiconductor substrate 1, shallow trench isolation region 2, gate oxide layer 3, gate 4, source Extension region 5, drain extension region 6, sidewall 7, silicon germanium or silicon carbon source and drain 8, source heavily doped region 9, drain heavily doped region 10, strained silicon nitride capping layer 11, source and drain. The strain desalination silicon capping layer 11 and the silicon germanium or silicon carbon source and drain 8 can be used simultaneously or independently in one device. The source extension region 5 and the source heavily doped region 9 are arranged side by side on the upper surface of the substrate 1 close to the source, and the drain extension region 6 and the drain heavily doped region 10 are arranged side by side on the substrate 1 The upper surface is close to the position of the drain. If the device is provided with silicon germanium or silicon carbon source and drain 8, then a silicon germanium or silicon carbon source and drain 8 is arranged on the upper surface of the source heavily doped region 9, and is connected with the source extension region. 5 phase contact, another silicon germanium or carbon silicon source and drain 8 is arranged on the upper surface of the drain heavily doped region 10, and is in contact with the drain extension region 6, between the source extension region 5 and the drain extension region 6 The upper surface of the substrate 1 is provided with a gate oxide layer 3, the gate 4 is disposed above the gate oxide layer 3, above the source extension region 5 and the drain extension region 6, and the gate 4 is close to both sides of the source and drain Each is provided with a sidewall 7, and the shallow trench isolation region 2 is arranged outside the active region, that is, surrounding the channel, source and drain regions, the shallow trench isolation region 2, silicon germanium or silicon carbon source and drain 8, and sidewall 7 And the upper surface of the gate 4 is covered with a strained silicon nitride capping layer 11 . Wherein, the channel region refers to the region between the source extension region 5 and the drain extension region 6 . Local strain technology usually introduces uniaxial stress into the channel, in which uniaxial compressive stress can improve the driving capability of PMOS devices without causing other performance degradation, such as reduced device stability and threshold voltage fluctuations; in addition, local strain technology is due to It has good process manufacturing compatibility with CMOS technology and simple manufacturing method, and only needs a small increase in cost when improving the performance of semiconductor devices, so it is widely favored by the industry. However, the local strain technology indirectly transfers the stress to the channel region. There must be a certain degree of stress attenuation or release during this transfer process, which limits its main application to small-scale devices with a channel length less than 130nm, and the channel The average stress is small, usually less than 1GPa; for devices with a channel length greater than 130nm, the device performance improvement brought by local strain technology is not obvious.

Global strain technology includes silicon germanium virtual substrate, strained silicon on insulator (SSOI), silicon germanium on insulator (SGOI), etc. The cross-sectional structure diagram of the existing virtual substrate global strain MOS device is shown in Figure 2, which includes source and drain Pole, substrate 1, silicon germanium dummy substrate 12, strained silicon layer 26, shallow trench isolation region 2, gate oxide layer 3, gate 4, source extension region 5, drain extension region 6, spacer 7, source Extremely heavily doped region 9, drain heavily doped region 10, the silicon germanium dummy substrate 12 is arranged on the upper surface of the substrate 1, the strained silicon layer 26 is arranged on the upper surface of the silicon germanium dummy substrate 12, and the source is extended The region 5 and the heavily doped source region 9 are arranged side by side on the upper surface of the strained silicon layer 3 close to the source, and the drain extension region 6 and the heavily doped drain region 10 are arranged side by side on the upper surface of the strained silicon layer 26 close to the source. The position of the drain, the upper surface of the strained silicon layer between the source extension region 5 and the drain extension region 6 is provided with a gate oxide layer 3, the gate 4 is arranged above the gate oxide layer 3, and the gate 4 is close to the source and drain. A sidewall 7 is provided on both sides of the electrode, and the two sidewalls 7 are respectively arranged above the source extension region 5 and the drain extension region 6. The shallow trench isolation region 2 is arranged outside the active region, that is, the channel, the source and surrounded by the drain region. Global strain technology can introduce large biaxial stress to the channel region, usually greater than 1GPa, and its stress is not limited by the size of the device. However, the preparation process of the substrate material is complex and the manufacturing cost is relatively high. Usually only one type of strain can be generated on a silicon chip, which cannot meet the needs of different devices for different strains, and the flexibility of device design is low. For the silicon-germanium virtual substrate, the stress of the top layer silicon 26 (or the strained silicon layer) increases with the increase of the germanium content of the relaxed germanium-silicon layer 12, and the relaxed germanium-silicon layer 12 with high germanium content, the germanium-silicon layer The thickness of 12 cannot be too small; in addition, the critical thickness of the top strained silicon layer 26 decreases with the increase of the germanium content of the relaxed germanium silicon layer 12 .

If the global strain technology can be combined with the local strain technology, the global strain technology can be applied to the local area, and a larger stress can be introduced to the local area, which can effectively improve the device performance without reducing the flexibility of the device design. improve device performance.

Contents of the invention

The purpose of the present invention is to overcome the current strained NMOSFET using local strain technology channel stress distribution is not uniform, and the shortcomings of low flexibility in device design using global strain technology, to provide a patterned strain NMOS device with a deep groove structure and its Production Method.

The present invention solves the technical problem, and adopts the technical scheme that a patterned strained NMOS device with a deep groove structure includes a source, a drain, a semiconductor substrate, a gate oxide layer, a source extension region, and a source heavily doped region , the drain extension region, the drain heavily doped region, the gate and the sidewall, and is characterized in that it also includes a deep isolation trench arranged outside the active region, a top-layer strained silicon only under the channel region, and only a top-layer The dielectric layer under the strained silicon, the upper surface of the deep isolation groove, the heavily doped source region, the heavily doped drain region, the gate and the side wall are covered with a layer of intrinsic tensile stress silicon nitride film.

Specifically, the vertical distance from the upper surface to the lower surface of the deep isolation trench is at least 0.4 μm.

Further, the deep isolation groove is rectangular.

Specifically, the deep isolation groove is trapezoidal or stepped, and the long side of the trapezoidal or stepped shape is located on the upper surface of the deep isolation groove.

Still further, the dielectric layer is silicon dioxide.

A method for fabricating a patterned strained NMOS device with a deep groove structure, characterized in that it comprises the following steps:

Step 01. Make a deep isolation trench outside the active area of the semiconductor substrate where the device will be fabricated. The depth of the deep isolation trench is not less than 0.4um. Dry etching is used. After the deep isolation trench is etched, it is first grown by thermal oxidation. Layer silicon dioxide layer, and then deposit silicon dioxide or other insulating medium;

Step 02, performing wet etching on the semiconductor substrate region between the deep isolation trenches to form an active region, the etching depth is greater than 0.2um and less than the depth of the deep isolation trenches;

Step 03: Deposit a relaxed germanium silicon layer on the active region, the thickness of the deposited relaxed germanium silicon layer is not less than 0.2um, but less than and close to the thickness of the active region;

Step 04, epitaxial silicon layer on the relaxed silicon germanium layer to form top strained silicon, the thickness of which is greater than 15nm and less than 50nm;

Step 05. Thermally grow a gate oxide layer on the top layer of strained silicon, deposit polysilicon on the gate oxide layer, deposit a gate silicon nitride etch barrier layer on the polysilicon, and perform gate etching to form a polysilicon gate electrode, that is, a gate , and then make silicon nitride sidewalls on both sides of the gate oxide layer, gate and gate silicon nitride etch stop layer close to the source and drain, and then deposit a silicon nitride etch stop layer in the non-active area ;

Step 06. Using silicon nitride as an etching barrier layer, perform dry etching on the top strained silicon layer and the relaxed silicon germanium layer. The total etching depth is greater than the thickness of the strained silicon layer on the top layer, but less than the strained silicon layer on the top layer and the relaxed silicon germanium layer. sum of thicknesses;

Step 07, using wet selective etching to remove the relaxed silicon germanium layer to form a void region;

Step 08, grow a silicon dioxide layer with a certain thickness on the silicon interface in the cavity area by dry oxidation, and then fill the cavity area with the silicon dioxide layer as a dielectric layer;

Step 09: Under the deposited silicon nitride etching stopper layer as a mask, perform dry etching to remove the silicon dioxide in the source and drain regions, and then use a wet method to clean the channel region that has not been dry-etched clean The silicon dioxide remaining on the side of the silicon forms the etched area of the source and drain;

Step 10, performing single crystal silicon epitaxy in the source and drain etched regions;

Step 11, removing the silicon nitride etch barrier layer and the gate silicon nitride etch barrier layer mask, doping the source extension region and the drain extension region, making side walls, and heavily doping the source and drain regions, A heavily doped source region and a heavily doped drain region are formed, and then an intrinsic tensile stress silicon nitride film is deposited on the upper surfaces of the heavily doped source region, the heavily doped drain region, the gate and side walls.

Specifically, in step 01, after the deep isolation trench is etched, a silicon dioxide layer is grown by thermal oxidation, and the thickness of the silicon dioxide layer is not less than 5 nm.

Further, in step 08, the certain thickness is 2nm to 5nm.

Specifically, in step 5, the thickness of the silicon nitride sidewall is greater than 10 nm and less than 40 nm.

Further, in step 11, the sidewalls are composed of silicon nitride sidewalls and sidewalls deposited after doping the source extension region or the drain extension region.

The beneficial effect of the present invention is that, through the above-mentioned patterned strained NMOS device with deep groove structure and its manufacturing method, it can be seen that the device is different from ordinary global strained devices and local strained devices, and its virtual substrate germanium silicon layer, namely The relaxed silicon germanium layer is only grown in the active region, and its stress only acts on the channel region of the device. Since the stress in the edge region of the channel is partially relaxed after source and drain etching, the subsequent tensile stress silicon nitride capping layer can Reintroduce greater stress to this region. In the local strain technology, the stress of the channel region decreases rapidly with the increase of the channel length, and the stress of the channel region decreases rapidly with the increase of the distance from the source and drain, and the stress distribution of the channel is uneven; in the present invention The channel stress is larger and more uniform, and its stress is basically not affected by the device size.

Description of drawings

FIG. 1 is a cross-sectional view of an existing local strain MOS device;

FIG. 2 is a cross-sectional view of an existing global strain MOS device;

Fig. 3 is the sectional view of making deep isolation groove on semiconductor substrate in the present embodiment;

4 is a cross-sectional view of the device after wet etching of silicon in the NMOS active region in this embodiment;

5 is a cross-sectional view of the epitaxial relaxed silicon germanium layer in the etching region in this embodiment;

6 is a cross-sectional view of the device after epitaxial monocrystalline silicon is grown on the relaxed silicon germanium layer in the active region in this embodiment;

7 is a cross-sectional view of the device after gate fabrication and silicon nitride etching stop mask deposition in this embodiment;

FIG. 8 is a cross-sectional view of the device after etching the strained silicon on the top layer of the source and drain regions in this embodiment;

FIG. 9 is a cross-sectional view of the device when a cavity region is formed after selectively etching the relaxed germanium-silicon layer in this embodiment;

FIG. 10 is a cross-sectional view of the device after filling the void region with silicon dioxide in this embodiment;

11 is a cross-sectional view of the device after dry etching of silicon dioxide in the source and drain regions in this embodiment;

12 is a cross-sectional view of the device after epitaxial single crystal silicon in the source and drain regions in this embodiment;

13 is a cross-sectional view of a patterned strained NMOS device with a deep groove structure according to the present invention;

Among them, 1 is the semiconductor substrate, 2 is the shallow trench isolation region, 3 is the gate oxide, 4 is the polycrystalline gate, 5 is the source extension region, 6 is the drain extension region, 7 is the sidewall, 8 is germanium silicon or Silicon carbon source and drain, 9 is the source heavily doped region, 10 is the drain heavily doped region, 11 is the strained silicon nitride capping layer, 12 is the silicon germanium dummy substrate, 13 is the deep isolation trench, 14 is the active 15 is the relaxed silicon germanium layer, 16 is the top layer strained silicon layer (or top layer silicon layer), 17 is the silicon nitride etching barrier layer for gate etching, and 18 is the silicon nitride side wall for protecting the gate electrode , 19 is the silicon nitride etch barrier layer protecting the non-active area, 20 is the etching area, 21 is the cavity area, 22 is the dielectric layer, 23 is the source and drain etching area, and 24 is the silicon nitride formed twice The side wall, 25 is the intrinsic tensile stress silicon nitride cap layer, and 110 is the strained silicon stress relaxation dividing line in the top layer after the relaxation of the silicon germanium layer is etched.

Detailed ways

The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

The cross-sectional view of the patterned strained NMOS device with a deep groove structure of the present invention is shown in Figure 13, which includes a source, a drain, a semiconductor substrate 1, a gate oxide layer 3, a source extension region 5, and a source heavily doped region 9. The drain extension region 6, the drain heavily doped region 10, the gate 4 and the sidewall 24, also including the deep isolation trench 13 arranged outside the active region 14, and the top-layer strained silicon 16 located only below the channel region and the dielectric layer 22 located only under the top-layer strained silicon 16, the upper surfaces of the deep isolation trench 13, the source heavily doped region 9, the drain heavily doped region 10, the gate 4 and the spacer 24 are covered with a layer of intrinsic Zhang Stressed silicon nitride film 25 . The fabrication method of the patterned strained NMOS device with a deep groove structure in the present invention is as follows: firstly, a deep isolation trench 13 is formed outside the active region 14 of the device on the semiconductor substrate 1, wherein the depth of the deep isolation trench 13 is not low At 0.4um, dry etching is used. After the deep isolation trenches 13 are etched, a layer of silicon dioxide is grown by thermal oxidation, and then silicon dioxide or other insulating media are deposited, and then the gap between the two deep isolation trenches 13 is The semiconductor substrate region is wet-etched to form the active region 14, the etching depth is greater than 0.2um, less than the depth of the deep isolation trench 13, and then the active region 14 is deposited with a relaxed germanium-silicon layer 15, and the deposited relaxation The thickness of the silicon germanium layer 15 is not less than 0.2um, but less than and close to the thickness of the active region 14, and then epitaxial silicon layer on the relaxed silicon germanium layer 15 to form the top strained silicon silicon 16 (or top silicon) and doping it, Its thickness is greater than 15nm and less than 50nm, and a gate oxide layer 3 is thermally grown on the top layer of strained silicon 16, polysilicon is deposited on the gate oxide layer 3, and a gate silicon nitride etching barrier layer 17 is deposited on the polysilicon and gate is etched Form the polysilicon gate electrode by etching, i.e. the gate 4, and then make silicon nitride sidewalls 18 on both sides of the gate oxide layer 3, the gate 4 and the gate silicon nitride etching stopper layer 17 close to the source and drain, and then Deposit a silicon nitride etch barrier layer 19 in the non-active area, and then use silicon nitride as the etch barrier layer to perform dry etching on the top strained silicon layer 16 and the relaxed silicon germanium layer 15, and the total etching depth greater than the thickness of the top layer strained silicon 16, and less than the sum of the thickness of the top layer strained silicon 16 and the relaxed silicon germanium layer 15, and then the relaxed silicon germanium layer 15 is removed by wet selective etching to form a cavity region 21, and then oxidized by dry method A silicon dioxide layer of a certain thickness is grown on the silicon interface in the cavity region 21, and then the silicon dioxide layer is filled in the cavity region 21 as a dielectric layer 22, and the silicon nitride etching barrier layer (including gate silicon nitride) is etched through the deposited silicon nitride. The etch stop layer 17 and the silicon nitride etch stop layer 19) are used as a mask, and the silicon dioxide in the source and drain regions is removed by dry etching, and then the channel that has not been dry etched is cleaned by a wet method The silicon dioxide remaining on the side of the silicon region forms the source and drain etched regions 23, and performs single crystal silicon epitaxy in the source and drain etched regions 23, and finally removes the silicon nitride etch barrier layer 19 and gate silicon nitride etch Mask the barrier layer 17 to dope the source extension region 5 and the drain extension region 6, make sidewalls 24, and heavily dope the source and drain regions to form the source heavily doped region 9 and the drain heavily doped region 10 , and then deposit an intrinsic tensile stress silicon nitride film 25 on the upper surfaces of the heavily doped source region 9 , the heavily doped drain region 10 , the gate 4 and the sidewall 24 .

Example

The sectional view of the patterned strained NMOS device with deep trench structure in this example is shown in FIG. 13 , and the deep isolation trench 13 can be rectangular, trapezoidal or stepped.

The patterned strained NMOS device with a deep trench structure in this example includes a source, a drain, a semiconductor substrate 1, a gate oxide layer 3, a source extension region 5, a source heavily doped region 9, and a drain extension region 6 , the heavily doped drain region 10, the gate 4 and the sidewall 24, the positions of which are the same as those of the source, the drain, the semiconductor substrate 1, the gate oxide layer 3, the source extension region 5, the heavily doped source The impurity region 9, the drain extension region 6, the drain heavily doped region 10, the gate 4 and the sidewall 7 correspond to each other (see Figure 1 or Figure 2), and compared with the prior art, it also includes 14 outside the deep isolation trench 13, the deep isolation trench 13 is about to surround the channel, source and drain regions, the top-layer strained silicon 16 only under the channel region and the dielectric layer 22 only under the top-layer strained silicon 16, deep The upper surfaces of the isolation trench 13 , the source heavily doped region 9 , the drain heavily doped region 10 , the gate 4 and the sidewall 24 are covered with a layer of intrinsic tensile stress silicon nitride film 25 .

Here, the vertical distance from the upper surface to the lower surface of the deep isolation trench 13 is at least 0.4 μm, and can be rectangular, trapezoidal or stepped. When the deep isolation trench 13 is trapezoidal or stepped, the long side of the trapezoidal or stepped shape is located The upper surface of the deep isolation trench 13. The dielectric layer 22 is silicon dioxide.

In the manufacturing method of the patterned strained NMOS device with deep groove structure in this example, the following steps are included:

Step 01. Fabricate deep isolation trenches 13 outside the active region 14 of the semiconductor substrate 1 where the device will be fabricated. See FIG. After etching, first grow a silicon dioxide layer with a thickness of not less than 5nm by thermal oxidation, and then deposit silicon dioxide or other insulating media by CVD or LPCVD. The deep isolation trench 13 is mainly used for device isolation and subsequent processes Supporting the grid 4.

Step 02: Perform wet etching on the semiconductor substrate region between the deep isolation trenches 13 to form the active region 14, see FIG. The etching depth is greater than 0.2um and less than the depth of the deep isolation groove 13.

Step 03: Deposit the relaxed germanium silicon layer 15 on the active region 14, the thickness of the deposited relaxed germanium silicon layer 15 is not less than 0.2um, but less than and close to the thickness of the active region 14, see FIG. 5 .

Step 04, epitaxial silicon layer on the relaxed silicon germanium layer 15 to form top layer strained silicon 16, as shown in FIG. 6, the thickness of which is greater than 15nm and less than 50nm.

Step 05. Thermally grow a gate oxide layer 3 on the top layer of strained silicon 16, deposit polysilicon on the gate oxide layer 3, deposit a gate silicon nitride etch barrier layer 17 on the polysilicon, and perform gate etching to form a polysilicon gate electrode , that is, the gate 4, and then make silicon nitride sidewalls 18 on both sides of the gate oxide layer 3, the gate 4 and the gate silicon nitride etching stopper layer 17 close to the source and the drain, and the silicon nitride sidewalls The thickness of 18 is greater than 10nm and less than 40nm, and then a silicon nitride etching stopper layer 19 is deposited in the non-active area, see FIG. 7 .

Step 06: Using silicon nitride as an etching barrier layer, perform dry etching on the top strained silicon layer 16 and the relaxed silicon germanium layer 15, the total etching depth is greater than the thickness of the top strained silicon layer 16, and less than the thickness of the top strained silicon layer 16 and the relaxed silicon layer. The sum of the thicknesses of the silicon-germanium layer 15 after etching is shown in FIG. 8 .

Step 07: Remove the relaxed silicon germanium layer 15 by wet selective etching to form a cavity region 21, see FIG. The plane is perpendicular to the tangential direction in the figure) and is connected to the isolation groove 13. In the width direction, the strained silicon layer 16 of biaxial tensile stress cannot relax the stress in the width direction due to the limitation of the gate; while in the channel length direction (from source to drain direction), the strained silicon layer 16 is due to the Both ends of the channel are free, and the stress in the silicon in the area below the stress relaxation line 110 is relaxed, while the strain in the area above the stress relaxation line 110 is restrained by the gate, so the strain cannot be relaxed and remains in a state of tensile strain. .

Step 08, grow a silicon dioxide layer with a thickness of 2nm to 5nm on the silicon interface in the void region 21 by dry oxidation, and then fill the void region 21 with a silicon dioxide layer as the dielectric layer 22, see FIG. 10; The purpose of the silicon dioxide layer is to prevent interface leakage due to interface defects between the filled silicon dioxide and the silicon in the channel region; the filled silicon dioxide and the thermally grown silicon dioxide have the same function as the buried oxide layer in the SOI device, so Filled silicon dioxide and thermally grown silicon dioxide are used as the dielectric layer 22 .

Step 09, using the deposited silicon nitride etch stop layer (including the gate silicon nitride etch stop layer 17 and the silicon nitride etch stop layer 19) as a mask, dry the silicon dioxide in the source and drain regions and then use wet method to clean the remaining silicon dioxide on the silicon side of the channel region that has not been etched by dry method to form source and drain etched regions 23, so that the epitaxial single crystal silicon and The strained silicon 16 on top of the channel region has a good contact, see FIG. 11 .

Step 10, performing single crystal silicon epitaxy in the source and drain etched regions 23, see FIG. 12 ;

Step 11, remove the silicon nitride etch stop layer 19 and the mask of the gate silicon nitride etch stop layer 17, do the source extension region 5 and the drain extension region 6, and make side walls 24, the side walls 24 is composed of silicon nitride sidewalls 18 and sidewalls deposited after doping the source extension region 5 and drain extension region 6, and the source and drain regions are heavily doped to form the source heavily doped region 9 and the drain heavily doped region 10, and then deposit intrinsic tensile stress silicon nitride film 25 on the upper surfaces of source heavily doped region 9, drain heavily doped region 10, gate 4 and sidewall 24, and the device formed See Figure 13 for a cross-sectional view. By depositing an intrinsic tensile stress silicon nitride film 25, a larger tensile stress along the channel length direction can be introduced into the channel region, so that the final channel region material stress is equal to the biaxial tensile stress introduced by the relaxed silicon germanium layer 15. Stress and the composite stress of the uniaxial tensile stress introduced by the intrinsic tensile stress silicon nitride film 25. It should be noted that the thickness of the intrinsic tensile stress silicon nitride film 25 is between tens to hundreds of nanometers, and its intrinsic The maximum stress value can reach 3GPa.

The difference from ordinary strained SOI devices is that the dielectric layer 22 is only under the channel region, and the top strained silicon 16 is the channel region of the NMOS device, and its stress is the biaxial tensile stress and intrinsic tensile stress introduced by the relaxed germanium silicon layer 15 The uniaxial tensile stress introduced by the silicon nitride film 25 constitutes composite stress. The stress in the source and drain regions is different from the stress in the channel region. The channel region is compound stress, while the source and drain regions are compressive stress introduced by the intrinsic tensile stress silicon nitride film 25 directly deposited thereon.

The depth of the deep isolation groove 13 of the device is greater than 0.4um, which is much larger than that of ordinary isolation grooves. Its function is to be the same as the common isolation trench on the one hand, to be used for device isolation, and on the other hand to be used to relax the silicon etching self-stop boundary before the epitaxy of the germanium-silicon layer 15. The thickness of the silicon nitride sidewall 18 produced at one time is relatively thin, and its thickness is between 10nm and 40nm, which is mainly used to protect the gate when etching the strained silicon 16 and the relaxed germanium silicon layer 15 on the top layer of the source and drain regions. It is used for isolation between the gate and the source and drain regions when epitaxial single crystal silicon is used. The purpose of its thinner thickness is to limit the dielectric layer 22 below the channel region, so that the thickness of the source extension region 5 and the drain extension region 6 is relatively small. Large, so that the resistance of the source extension region 5 and the drain extension region 6 can be reduced; at the same time, since the source and drain regions are directly connected to the substrate 1, the heat dissipation of the device can be enhanced and the floating body effect can be reduced. The top-layer strained silicon 16 in the channel region of the device is made by an epitaxial process, and its growth quality is good, and the thickness can be controlled at the nanometer level, which can make the top-layer strained silicon 16 thinner, allowing the device to work in a fully depleted state, thereby overcoming Problems such as the floating body effect existing in SOI devices. In this device, the silicon dioxide dielectric layer 22 is limited only under the channel region, similar to the BOX region in an ultra-thin strained SOI device, which is only limited to a local area, so the device can also be called a patterned strained SOI device.

This device is different from ordinary globally strained devices and local strained devices. Its relaxed silicon germanium layer 15 is only grown in the active region, and its stress only acts on the channel region of the device. Being partially relaxed, the silicon nitride film 25 can re-introduce greater stress to this region through the intrinsic tensile stress. In the local strain technology, the stress of the channel region decreases rapidly with the increase of the channel length, and the stress of the channel region decreases rapidly with the increase of the distance from the source and drain, and the stress distribution of the channel is uneven; in the present invention The channel stress is larger and more uniform, and its stress is basically not affected by the device size.

This device is different from ordinary SON (or SOA) devices. The thickness of the relaxed silicon germanium layer 15 in the invention is much greater than the thickness of the silicon germanium layer in the SON device; The thickness of the layer 15 is generally greater than 0.2um; the silicon germanium layer in the SON device is used to etch the void region under the channel, while the relaxation of the silicon germanium layer 15 in the present invention is to form a void region 21 under the channel to fill the oxide Silicon forms a local SOI device, and the second is to introduce stress to the channel region by using the relaxed germanium silicon layer 15; the improvement of device performance in the present invention is mainly caused by stress.

Claims (10)

1. the patterned strained nmos device that has deep groove structure, comprise source electrode, drain electrode, Semiconductor substrate (1), gate oxide (3), source extension regions (5), source electrode heavily doped region (9), drain extensions (6), drain electrode heavily doped region (10), grid (4) and side wall (24), it is characterized in that, also comprise the deep isolation trench (13) that is arranged on active area (14) outside, the top layer strained silicon (16) that only is positioned at the channel region below reaches the dielectric layer (22) that only is positioned at top layer strained silicon below, described deep isolation trench (13), source electrode heavily doped region (9), drain electrode heavily doped region (10), the upper surface of grid (4) and side wall (24) is coated with one deck intrinsic tensile stress silicon nitride film (25).

2. according to the described patterned strained nmos device with deep groove structure of claim 1, it is characterized in that the upper surface of described deep isolation trench (13) is at least 0.4 μ m to the vertical range of lower surface.

3. according to the described patterned strained nmos device with deep groove structure of claim 1, it is characterized in that described deep isolation trench (13) is rectangle.

4. according to the described patterned strained nmos device with deep groove structure of claim 1, it is characterized in that described deep isolation trench (13) is trapezoidal or stairstepping, described trapezoidal or step-like long limit is positioned at the upper surface of trench structure.

5. according to claim 1 or 2 or 3 or 4 described patterned strained nmos devices with deep groove structure, it is characterized in that described dielectric layer (22) is silicon dioxide.

6. have the manufacture method of the patterned strained nmos device of deep groove structure, it is characterized in that, may further comprise the steps:

Step 01, at the active area that will make device (14) the arranged outside deep isolation trench (13) of Semiconductor substrate (1), wherein deep isolation trench (13) degree of depth is not less than 0.4um, adopt dry etching, pass through thermal oxide growth layer of silicon dioxide layer, deposit silicon dioxide or other dielectrics again after deep isolation trench (13) etching earlier;

Step 02, wet etching is carried out in Semiconductor substrate (1) zone between the deep isolation trench (13) be formed with source region (14), etching depth is greater than 0.2um, less than deep isolation trench (13) degree of depth;

Step 03, active area (14) is carried out relaxation germanium silicon layer (15) deposit, the thickness of deposit relaxation germanium silicon layer (15) is not less than 0.2um, and less than and near active area (14) thickness;

Step 04, go up silicon epitaxial layers at relaxation germanium silicon layer (15) and form top layer strained silicon (16) and mix, its thickness greater than 15nm less than 50nm;

Step 05, go up heat growth gate oxide (3) in top layer strained silicon (16), go up the deposit polysilicon at gate oxide (3), deposit grid silicon nitride etch barrier layer (17) and carry out the grid etching and form polygate electrodes on polysilicon, be grid (4), both sides near source electrode and drain electrode make silicon nitride side wall (18) on gate oxide (3), grid (4) and grid silicon nitride etch barrier layer (17) again, again at non-active area deposit silicon nitride etching barrier layer (19);

Step 06, be etching barrier layer with the silicon nitride, top layer strained silicon (16) and relaxation germanium silicon layer (15) are carried out dry etching, the etching total depth is greater than top layer strained silicon (16) thickness, less than top layer strained silicon (16) and relaxation germanium silicon layer (15) thickness sum;

Step 07, employing wet method selective etch are removed relaxation germanium silicon layer (15), form cavity district (21);

Step 08, by dry oxidation certain thickness silicon dioxide layer of silicon interface growth in cavity district (21), in cavity district (21), fill silicon dioxide layer as dielectric layer (22) again;

Step 09, the silicon nitride etch barrier layer by deposit are under the mask, source-drain area silicon dioxide is carried out dry etching to be removed, and then with wet-cleaned not by the clean residual silicon dioxide in channel region silicon side of dry etching, the zone (23) that is etched is leaked in the formation source;

Step 10, leak the zone (23) that is etched in the source and carry out the monocrystalline silicon extension;

Step 11, removal silicon nitride etch barrier layer (19) and grid silicon nitride etch barrier layer (17) mask, carry out the doping of source extension regions (5) and drain extensions (6), make side wall (24), to source-drain area heavy doping, form source electrode heavily doped region (9) and drain electrode heavily doped region (10), again at the upper surface deposition of intrinsic tensile stress silicon nitride film (25) of source electrode heavily doped region (9), drain electrode heavily doped region (10), grid (4) and side wall (24).

7. according to the described manufacture method with patterned strained nmos device of deep groove structure of claim 6, it is characterized in that, in the step 01, earlier by thermal oxide growth layer of silicon dioxide layer, the thickness of this silicon dioxide layer is for being not less than 5nm after described deep isolation trench (13) etching.

8. according to the described manufacture method with patterned strained nmos device of deep groove structure of claim 6, it is characterized in that in the step 08, described certain thickness is that 2nm is to 5nm.

9. according to the described manufacture method with patterned strained nmos device of deep groove structure of claim 6, it is characterized in that, in the step 5, the thickness of described silicon nitride side wall (18) greater than 10nm less than 40nm.

10. according to claim 6 or 7 or 8 or 9 described manufacture methods with patterned strained nmos device of deep groove structure, it is characterized in that, in the step 11, the side wall of deposit was formed jointly after described side wall (24) was mixed by silicon nitride side wall (18) and source extension regions (8) or drain extensions (10).

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