CN103269220A - Clock recovery circuit through NFC active load modulation based on digital phase-locked loop - Google Patents
Clock recovery circuit through NFC active load modulation based on digital phase-locked loop Download PDFInfo
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Abstract
A clock recovery circuit through NFC active load modulation based on a digital phase-locked loop is formed by a digital phase-locked loop and a digital delay locking loop. The digital phase-locked loop works under a tracking carrier frequency mode and a fixed oscillation frequency mode. Under the fixed oscillation frequency mode, oscillation frequency is formed and locked in the period of tracking a carrier wave, the digital phase-locked loop is an all-digital structure phase-locked loop, and the digital delay locking loop receives a split phase clock of the phase-locked loop, and fast locks a clock which is closest to a carrier phase through comparison with a phase of the carrier wave. The digital delay locking loop works under a phase tracking mode and a fixed phase mode, under the fixed phase mode, the digital delay locking loop constantly outputs the same split phase clock, and the clock is obtained under a tracking mode. The clock recovery circuit reduces frequency difference caused by injecting noise in the time of conversion from a closed loop to an open loop, enables bandwidth of the phase-locked loop to be reduced to further lower phase noise, and can avoid the situation that the phase difference cannot be corrected due to the fact that the bandwidth is reduced.
Description
Technical field
The present invention relates to Near-field-communication(hereinafter to be referred as NFC) active lift-off technology field, specifically be a kind of based on the trivial clock recovery circuitry of the NFC active load modulation of ring mutually of numeral.
Background technology
Generally in NFC adopt passive or active load is modulated to realize to return from the contactless data that snap into reader.Passive load modulation utilization changes the antenna impedance of contactless card and launches data, and the load-modulate of having chance with is then by intermittently initiatively emission and reader carrier wave are realized purpose with the emission data of passive mode equivalence with alternating electric field frequently.Than passive mode, active load modulation has the ability of longer communication distance and stronger anti-metallic shield.
In order to reach the purpose of maximum communication distance, the alternating electric field of active load modulate emission need and outside reader electromagnetic field maintenance phase place consistent, reason is that the phase difference of these two electromagnetic fields rotates maximum communication distance is fluctuateed.
Although the active load modulation has the inaccessiable advantage of passive mode, very big difficulty is arranged also in realization.Because when non-contact card is initiatively launched alternating electromagnetic field, the signal from reader that antenna end receives is far smaller than the signal that self launches, so the exalted carrier clock phase can depart from the carrier phase of reader in the signal that receives, thereby the alternating electromagnetic field that makes emission can't be simulated the passive load modulation effectively, and communication distance is shortened.Therefore when clamping is subjected to data-signal, can utilize the oscillator clock that maintains frequency to transmit when transmitting on clock recovery and oscillator of injection locking of carrier wave, this can utilize a phase-locked loop to realize.Still locking frequency and phase place for a long time when but traditional phase-locked loop circuit is difficult to remain on no input clock.According to the requirement of typeA among the IEC14443 and type B, frame data are the longest can to comprise 256 bytes, calculates the communication time (each byte comprises a bit parity check code) that can reach 21.7ms with the communication data rate of minimum 106K.Allow phase-locked loop freedom of entry when vibration, what produce during this period differs less than 90 °, and then the deviation of frequency is less than 0.82ppm (11Hz), and this just needs the very complicated accurate circuit of design, sometimes even be difficult to actually realize in chip-scale.In order to address this problem, can to allow phase-locked loop also the incoming carrier clock be recovered and follows the tracks of in the gap of emission alternating electromagnetic field, and proofread and correct the phase error of accumulating in the open loop duration of oscillation.But also there are some problems in such method.Because in emission alternating electromagnetic field gap, antenna energies such as needs exhaust Shi Caineng and carry out recovery to the reader carrier wave, so this section can be used to follow the tracks of the time of carrier wave and relatively lack (several to dozens of carrier cycles), this just requires to design a very large phase-locked loop of loop bandwidth.But the phase-locked loop of big bandwidth can be introduced very big frequency error (the electric charge injection of switch etc. causes) when changing from closed loop to open loop, thereby has produced before recovering closed loop next time follows the tracks of greater than 90 ° differ also not waiting until.Therefore when the design bandwidth of phase lock loop, face awkward selection.
List of references:
1.ISO/IEC14443protocol,international?standard.
2.“Method?and?device?for?active?load?modulation?by?inductor?coupling”,US?patent,Pub?No:US2012/0071089.
Summary of the invention
The objective of the invention is to overcome above-mentioned the deficiencies in the prior art, provide a kind of, by suppressing the CE-BEM model error, improve the accuracy of channel estimating.
Technical solution of the present invention is as follows:
A kind of clock recovery circuitry of modulating based on the NFC active load of the trivial ring mutually of numeral, its characteristics are, this clock recovery circuitry is a twin nuclei that is made of digital phase-locked loop and digital delay locked loop, wherein digital phase-locked loop is major loop, the locking of frequency is provided, digital delay locked loop is the secondary ring road, and the locking of phase place is provided:
Described digital phase-locked loop is operated in follows the tracks of carrier frequency and two kinds of patterns of built-in oscillation frequency, and under the built-in oscillation frequency mode, frequency of oscillation locks the frequency that forms during following the tracks of carrier wave, and this digital phase-locked loop is digital framework phase-locked loop; The input of digital phase-locked loop is the carrier clock that receives, and output is the clock signal behind the VCO two divided-frequency.
Described digital delay locked loop receives the branch phase clock of described phase-locked loop, and by with one of the comparison quick lock in of the phase place of carrier wave near the clock of carrier phase; This digital delay locked Phase Tracking pattern and stationary phase pattern of being operated in, under stationary phase pattern pattern, this loop is exported same minute phase clock always, and this clock is obtained by locking under the tracing mode.
Described digital phase-locked loop comprises successively digital frequency phase detector, enable signal switch, digital filter and the numerically-controlled oscillator that connects, the carrier clock that being input as of this digital frequency phase detector receives and an output mutually of numerically-controlled oscillator;
Described digital delay locked loop comprises successively lead-lag phase discriminator, enable signal switch, counter, MUX and the phase interpolator that connects, and the input of this lead-lag phase discriminator is the carrier clock that receives and the output of MUX;
The digital control amount that is input as loop filter output of numerically-controlled oscillator, it is output as 6 phase clocks (only draw among Fig. 1 wherein positive three-phase).6 phase clocks that are input as numerically-controlled oscillator output of phase interpolator 23, it is output as the clock of 18 phase 27.12MHz, and they become the input signal of MUX.
Digital phase-locked loop has a lower loop bandwidth, thus the random noise that samples when suppressing from closed loop to open loop, and digital delay locked loop has very high bandwidth, can eliminate the phase error that phase-locked loop accumulates when operate in open loop state in several carrier cycles.
Compared with prior art, technique effect of the present invention is to receive data and recovery is followed the tracks of to the reader carrier wave in emission alternating electromagnetic field gap, differs as far as possible little clock signal thereby provide when the emission alternating electromagnetic field with the reader carrier wave.Simultaneously, reduced the frequency difference that the injection noise when changing from closed loop to open loop causes as much as possible.Adopted a secondary ring to correct fast simultaneously and differed, the bandwidth of phase-locked loop is reduced with further attenuating phase noise, can can't not correct differing again because bandwidth reduces.
Description of drawings
Fig. 1 is the schematic diagram that the present invention is based on the clock recovery circuitry of the trivial NFC active load modulation that encircles mutually of numeral.
Fig. 2 is the working timing figure of clock recovery circuitry.
Fig. 3 is the concrete structure figure of digital phase-locked loop among the present invention.
Fig. 4 is the concrete structure figure of digital delay locked loop among the present invention.
Embodiment
The invention will be further described below in conjunction with embodiment and accompanying drawing, but should not limit protection scope of the present invention with this.
The present invention proposes the purpose that keeps emission and the synchronous alternating electromagnetic field of reader carrier wave when the twin nuclei that adopts a digital phase-locked loop and digital delay locked loop is implemented in the active load modulation.Fig. 1 is the schematic diagram that the present invention is based on the clock recovery circuitry of the trivial NFC active load modulation that encircles mutually of numeral, wherein digital phase-locked loop 10 is by the digital frequency phase detector 11 that connects successively, and enable signal switch, digital filter 12 and numerically-controlled oscillator 13 are formed.One output mutually of the carrier clock that being input as of digital frequency phase detector 11 receives and numerically-controlled oscillator, digital frequency phase detector 11 is output as and represents the digital quantity that input clock differs, the digital control amount that is input as loop filter output of numerically-controlled oscillator 13, it is output as 6 phase clocks (only draw among Fig. 1 wherein positive three-phase).The great advantage of digital phase-locked loop is to be subjected to the influence of parasitic parameter less, is particularly suitable for the application of open loop.When loop is changed to open loop by closed loop, the random noise that digital filter is only sampled and produced by digital frequency phase detector, and the traditional analog loop also will be subjected to the influence of nonrandom disturbance such as electric charge injection.Thereby the bandwidth of phase lock loop of this moment can reduce and further suppresses random noise.
The function of following the tracks of carrier wave is fast realized by a digital delay locked loop 20.This loop is by the lead-lag phase discriminator 21 of an output, and enable signal switch, counter 22, MUX 24 and phase interpolator 23 constitute, and purpose is to select fast with carrier wave to differ minimum clock in the clock set that postpones output through difference.The input of lead-lag phase discriminator 21 is the carrier clock that receives and the output of MUX, the output of lead-lag phase discriminator 21 is lead-lag marking signals of one, the input of counter 22 is the lead-lag marking signals by enable switch control, output is the number of phases of control MUX, the input of MUX 24 is the output of counter and 18 27.12MHz clocks mutually from phase interpolator 23 output, its output be one with the immediate clock of carrier phase (this clock while is as the counting clock of counter).
The work schedule of this dicyclo framework clock recovery circuitry is seen shown in Figure 2.When contactless card received reader signal, phase-locked loop can the all-the-way tracking carrier wave, such as type B pattern.Also can when receiving big signal groove, close the tracking of phase-locked loop, as type A pattern.When the emission alternating electromagnetic field, phase-locked loop keeps the frequency of oscillation before the operate in open loop state to continue as radiating circuit provides clock.Become big gradually because small frequency departure can make to differ, therefore can allow phase-locked loop open again in the gap of emission electromagnetic field, come the deviation of emending frequency and phase place.Be 64/fc and 8/fc emission maximum off time that can provide under Type A and the type B pattern, and fc is the frequency of carrier wave.Owing to have no progeny in the emission, the residual amount of energy on the antenna still can influence carrier clock to be accepted, so actual available tracking time is less than above-mentioned value.Because the limited bandwidth of phase-locked loop, so Duan intermittent time often can not make to differ fully and eliminate, and therefore needs to select fast with carrier wave with digital delay locked loop during this period to differ minimum clock.Two loops all enter hold mode when entering emission mode, up to next one emission intermittently.
Fig. 3 and Fig. 4 have provided the more detailed structure chart of digital phase-locked loop and digital delay locked loop respectively.Because output frequency is Discrete Change in digital phase-locked loop, improves frequency accuracy and do not bring the increase of power consumption area can utilize digital sigma Delta modulator 33 to realize.Digital control amount after the modulation becomes analog quantity (voltage or electric current) by analog to digital converter 36, again by low pass filter simulations of 37 filtering quantizing noise rear drives voltage-controlled (Current Control) oscillator 38.One of this oscillator is exported mutually behind two-divider 35 and carrier wave ratio forms first via feedback.Other phase clocks produce the clock of 36 phase 13.56MHz through phase interpolator 43.A phase and the carrier wave selected wherein by the MUX 44 of counter 42 controls relatively form the second tunnel feedback through phase discriminator 41.Application example:
For verifying validity of the present invention, utilize matlab to design the twin nuclei that a digital phase-locked loop and digital delay locked loop road are formed.The bandwidth of this phase-locked loop is 100KHz, and analog to digital converter has 7 precision, utilizes the single order sigma Delta modulator when over-sampling rate is 68 times, can improve 8 frequency accuracy, and the resolution of the phase frequency detector of phase-locked loop is 90ps.With the carrier wave of 13.56MHz the phase-locked loop output clock of the frequency difference of 83Hz being arranged is 30 ° differing of 1ms accumulation.And because the lock speed of delay lock loop is each carrier cycle 2ns, therefore only need 3 carrier cycles (0.22us) just can recover to differ with zero of carrier wave.For the traditional analog framework phase-locked loop of same bandwidth, since the bandwidth restriction, differing and can't in several carrier cycles, eliminate in the 1ms accumulation.
Claims (2)
1. one kind based on the trivial clock recovery circuitry of the NFC active load modulation of ring mutually of numeral, it is characterized in that, this clock recovery circuitry is a twin nuclei that is made of digital phase-locked loop and digital delay locked loop, wherein digital phase-locked loop is major loop, the locking of frequency is provided, digital delay locked loop is the secondary ring road, and the locking of phase place is provided:
Described digital phase-locked loop is operated in follows the tracks of carrier frequency and two kinds of patterns of built-in oscillation frequency, and under the built-in oscillation frequency mode, frequency of oscillation locks the frequency that forms during following the tracks of carrier wave, and this digital phase-locked loop is digital framework phase-locked loop; The input of digital phase-locked loop is the carrier clock that receives, and output is the clock signal behind the VCO two divided-frequency.
Described digital delay locked loop receives the branch phase clock of described phase-locked loop, and by with one of the comparison quick lock in of the phase place of carrier wave near the clock of carrier phase; This digital delay locked Phase Tracking pattern and stationary phase pattern of being operated in, under stationary phase pattern pattern, this loop is exported same minute phase clock always, and this clock is obtained by locking under the tracing mode.
2. according to claim 1 based on the trivial clock recovery circuitry of the NFC active load modulation of ring mutually of numeral, it is characterized in that, described digital phase-locked loop comprises successively digital frequency phase detector (11), enable signal switch, digital filter (12) and the numerically-controlled oscillator (13) that connects, and one of the carrier clock that being input as of this digital frequency phase detector receives and numerically-controlled oscillator exported mutually;
Described digital delay locked loop comprises successively lead-lag phase discriminator (21), enable signal switch, counter (22), MUX (24) and the phase interpolator (23) that connects, and the input of this lead-lag phase discriminator is the carrier clock that receives and the output of MUX;
Described phase interpolator (23) receives 6 phase clocks of numerically-controlled oscillator (13) output, and exports the clock of 18 phase 27.12MHz.
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| CN103475363A (en) * | 2013-09-04 | 2013-12-25 | 苏州苏尔达信息科技有限公司 | Digital phase-locked loop circuit of binary-phase comparator |
| CN103490773A (en) * | 2013-09-04 | 2014-01-01 | 苏州苏尔达信息科技有限公司 | Digital phase-locked loop circuit of linear phase comparator |
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