CN103268302A - Interface expanding circuit, interface expanding connecting method and embedded system - Google Patents
Interface expanding circuit, interface expanding connecting method and embedded system Download PDFInfo
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- CN103268302A CN103268302A CN2013101379595A CN201310137959A CN103268302A CN 103268302 A CN103268302 A CN 103268302A CN 2013101379595 A CN2013101379595 A CN 2013101379595A CN 201310137959 A CN201310137959 A CN 201310137959A CN 103268302 A CN103268302 A CN 103268302A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
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- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
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Abstract
The embodiment of the invention provides an interface expanding circuit, an interface expanding connecting method and an embedded system for realizing the effect that when a south bridge chip accesses one BIOS (basic input output system) chip in the two BIOS chips, a CPU (central processing unit) can be used for updating the other BIOS chip. The interface expanding circuit comprises a switching connecting circuit, wherein the switching connecting circuit is connected with at least two BIOS chips, is used for connecting the first BIOS chip in the at least two BIOS chips with an SPI (serial peripheral interface) arranged on the south bridge chip, and is also used for connecting at least one second BIOS chip except the first BIOS chip in the at least two BIOS chips with a circuit capable of providing the SPI, so the second BIOS chip can be updated through the switching connecting circuit and the circuit capable of providing the SPI.
Description
Technical field
The present invention relates to the circuit design technique field, relate in particular to a kind of interface expanded circuit, interface method of extending and connecting and embedded system.
Background technology
In order to improve the reliability of system, when design embedded system circuit, be everlasting and hang two Basic Input or Output System (BIOS) (BIOS under the South Bridge chip, Basic Input Output System) chip, decide for one and use the BIOS chip, another does standby BIOS chip, be damaged and start from standby BIOS with the BIOS chip data when main, and the content recovery in the standby BIOS chip is used in the BIOS chip to main.Because two BIOS chips all will connect Serial Peripheral Interface (SPI) (SPI, Serial Peripheral Interface), and South Bridge chip has only a SPI, therefore need to increase peripheral auxiliary circuits and be articulated in same SPI to two BIOS chips, and select to visit a BIOS chip in two BIOS chips by switching chip selection signal.Under present system architecture, CPU (central processing unit) (CPU, Center Processing Unit) need be upgraded to a BIOS chip in two BIOS chips by the SPI on the South Bridge chip.This has caused when CPU upgrades to a BIOS chip in two BIOS chips by the SPI on the South Bridge chip, and South Bridge chip can't conduct interviews to another BIOS chip.
In sum, under present system architecture, two BIOS chips connect the same SPI on the South Bridge chips, and when this can cause existing systems can't be implemented in South Bridge chip a BIOS chip in two BIOS chips is conducted interviews, CPU upgraded to another BIOS chip.
Summary of the invention
The embodiment of the invention provides a kind of interface expanded circuit, interface method of extending and connecting and embedded system, and CPU can upgrade to another BIOS chip when to be implemented in South Bridge chip a BIOS chip in two BIOS chips being conducted interviews.
First aspect provides a kind of interface expanded circuit, and described interface expanded circuit comprises the switching connecting circuit, and described switching connecting circuit connects at least two basic input-output system BIOS chips;
Described switching connecting circuit is used for a BIOS chip of described at least two BIOS chips is linked to each other with serial peripheral interface SPI on the South Bridge chip;
Described switching connecting circuit also is used for described at least two BIOS chips at least one the 2nd BIOS chip except a BIOS chip is linked to each other with the circuit that SPI can be provided, and makes described the 2nd BIOS chip to upgrade by the described circuit of SPI and the described switching connecting circuit of can providing.
In conjunction with first aspect, in first kind of possible implementation, the described circuit of SPI that can provide is connected to central processing unit CPU, and described switching connecting circuit links to each other with SPI on the described CPU;
Described switching connecting circuit specifically is used for described at least two BIOS chips at least one the 2nd BIOS chip except a BIOS chip is linked to each other with SPI on the CPU, makes described the 2nd BIOS chip to upgrade by the SPI on the described CPU and described switching connecting circuit.
In conjunction with first aspect, in second kind of possible implementation, the described circuit of SPI that can provide comprises the change-over circuit that is arranged in described interface expanded circuit, described change-over circuit respectively with CPU on non-SPI link to each other with described switching connecting circuit;
Described change-over circuit is used for described CPU when the non-SPI by self upgrades to described the 2nd BIOS chip that switches connecting circuit and connect, and the upgrading signal that the non-SPI on the described CPU is sent is converted to the upgrading signal based on the SPI form.
In conjunction with first aspect, in the third possible implementation, the described circuit of SPI that can provide comprises the change-over circuit that is arranged in described interface expanded circuit, described change-over circuit respectively with South Bridge chip on non-SPI link to each other with described switching connecting circuit;
Described change-over circuit is used for when CPU upgrades to the 2nd BIOS chip that switches connecting circuit and connect by the non-SPI on the South Bridge chip, and the upgrading signal that the non-SPI on the South Bridge chip is sent is converted to the upgrading signal based on the SPI form.
In conjunction with to the third possible implementation of first aspect any one of first aspect and first kind of possible implementation of first aspect, in the 4th kind of possible implementation, described switching connecting circuit, when also being used for resetting in system, with a described BIOS chip from state that SPI on the described South Bridge chip links to each other under switch to the state that links to each other with the circuit that SPI can be provided, and with described the 2nd BIOS chip from state that the circuit that SPI can be provided links to each other under switch to the state that links to each other with SPI on the described South Bridge chip.
In conjunction with second kind of possible implementation of first aspect, in the 5th kind of possible implementation, described change-over circuit connects South Bridge chip by the quick peripheral component interconnect Bus PC I-E interface on the peripheral component interconnect bus pci interface on the CPU and/or the CPU.
In conjunction with the third possible implementation of first aspect, in the 6th kind of possible implementation, described change-over circuit connects South Bridge chip by the quick peripheral component interconnect Bus PC I-E interface on the few stitch type LPC interface on the South Bridge chip and/or the peripheral component interconnect bus pci interface on the South Bridge chip and/or the South Bridge chip.
In conjunction with first kind of possible implementation of first aspect any one implementation to the 4th kind of possible implementation of first aspect, in the 7th kind of possible implementation, described interface expanded circuit is complex programmable logic device (CPLD) or is on-site programmable gate array FPGA.
Second aspect provides a kind of interface method of extending and connecting, comprising:
By switching connecting circuit, the BIOS chip at least two BIOS chips is linked to each other with serial peripheral interface SPI on the South Bridge chip;
By described switching connecting circuit, with at least one the 2nd BIOS chip except a BIOS chip in described at least two BIOS chips, link to each other with the circuit that SPI can be provided, make described the 2nd BIOS chip to upgrade by the described circuit of SPI and the described switching connecting circuit of can providing.
In conjunction with second aspect, in first kind of possible implementation, described by switching connecting circuit with described at least one the 2nd BIOS chip, link to each other with the circuit that SPI can be provided, make described the 2nd BIOS chip to upgrade by the described circuit of SPI and the described switching connecting circuit of can providing, comprising:
By described switching connecting circuit with at least one the 2nd BIOS chip except a BIOS chip in described at least two BIOS chips, link to each other with the SPI on the CPU, make described the 2nd BIOS chip to upgrade by the SPI on the described CPU and described switching connecting circuit.
In conjunction with second aspect, in second kind of possible implementation, described by switching connecting circuit with described at least one the 2nd BIOS chip, link to each other with the circuit that SPI can be provided, make described the 2nd BIOS chip to upgrade by the described circuit of SPI and the described switching connecting circuit of can providing, comprising:
By described switching connecting circuit with at least one the 2nd BIOS chip except a BIOS chip in described at least two BIOS chips, link to each other with non-SPI on the CPU by change-over circuit, make described the 2nd BIOS chip when upgrading by the non-SPI on the described CPU and described switching connecting circuit, by with switch upgrading signal that change-over circuit that connecting circuit links to each other sends the non-SPI on the CPU and be converted to upgrading signal based on the SPI form.
In conjunction with second aspect, in the third possible implementation, described by switching connecting circuit with described at least one the 2nd BIOS chip, link to each other with the circuit that SPI can be provided, make described the 2nd BIOS chip to upgrade by the described circuit of SPI and the described switching connecting circuit of can providing, comprising:
By described switching connecting circuit with at least one the 2nd BIOS chip except a BIOS chip in described at least two BIOS chips, link to each other with non-SPI on the South Bridge chip by change-over circuit, make described the 2nd BIOS chip when upgrading by the non-SPI on the described South Bridge chip and described switching connecting circuit, by with switch upgrading signal that change-over circuit that connecting circuit links to each other sends the non-SPI on the South Bridge chip and be converted to upgrading signal based on the SPI form.
In conjunction with to the third possible implementation of second aspect any one of second aspect and first kind of possible implementation of second aspect, in the 4th kind of possible implementation, described method also comprises:
When system resets, by described switching connecting circuit with a BIOS chip from state that SPI on the South Bridge chip links to each other under switch to the state that links to each other with the circuit that SPI can be provided, and with the 2nd BIOS chip from state that the circuit that SPI can be provided links to each other under switch to the state that links to each other with SPI on the South Bridge chip.
The third aspect, a kind of embedded system is provided, comprise at least two basic input-output system BIOS chips and South Bridge chip, described embedded system also comprises the interface expanded circuit, described interface expanded circuit comprises the switching connecting circuit, and described switching connecting circuit connects described at least two basic input-output system BIOS chips;
Described switching connecting circuit is used for a BIOS chip of described at least two BIOS chips is linked to each other with serial peripheral interface SPI on the South Bridge chip;
Described switching connecting circuit also is used for described at least two BIOS chips at least one the 2nd BIOS chip except a described BIOS chip is linked to each other with the circuit that SPI can be provided, and makes described the 2nd BIOS chip to upgrade by the described circuit of SPI and the described switching connecting circuit of can providing.
In conjunction with the third aspect, in first kind of possible implementation, the described circuit of SPI that can provide is connected to central processing unit CPU, and described switching connecting circuit links to each other with SPI on the described CPU;
Described switching connecting circuit specifically is used for described at least two BIOS chips at least one the 2nd BIOS chip except a described BIOS chip is linked to each other with SPI on the CPU, makes described the 2nd BIOS chip to upgrade by the SPI on the described CPU and described switching connecting circuit.
In conjunction with the third aspect, in second kind of possible implementation, the described circuit of SPI that can provide comprises the change-over circuit that is arranged in described interface expanded circuit, described change-over circuit respectively with CPU on non-SPI link to each other with described switching connecting circuit;
Described change-over circuit is used for CPU when the non-SPI by self upgrades to the 2nd BIOS chip that switches connecting circuit and connect, and the upgrading signal that the non-SPI on the described CPU is sent is converted to the upgrading signal based on the SPI form.
In conjunction with the third aspect, in the third possible implementation, the described circuit of SPI that can provide comprises the change-over circuit that is arranged in described interface expanded circuit, described change-over circuit respectively with South Bridge chip on non-SPI link to each other with described switching connecting circuit;
Described change-over circuit is used for when CPU upgrades to the 2nd BIOS chip that switches connecting circuit and connect by the non-SPI on the South Bridge chip, and the upgrading signal that the non-SPI on the South Bridge chip is sent is converted to the upgrading signal based on the SPI form.
In conjunction with first kind of the third aspect and the third aspect possible implementation any one to the third possible implementation of the third aspect, in the 4th kind of possible implementation, described switching connecting circuit, when also being used for resetting in system, with a described BIOS chip from state that SPI on the described South Bridge chip links to each other under switch to the state that links to each other with the circuit that SPI can be provided, and with described the 2nd BIOS chip from state that the circuit that SPI can be provided links to each other under switch to the state that links to each other with SPI on the described South Bridge chip.
In conjunction with second kind of possible implementation of the third aspect, in the 5th kind of possible implementation, described change-over circuit connects South Bridge chip by the quick peripheral component interconnect Bus PC I-E interface on the peripheral component interconnect bus pci interface on the CPU and/or the CPU.
In conjunction with the third possible implementation of the third aspect, in the 6th kind of possible implementation, described change-over circuit connects South Bridge chip by the quick peripheral component interconnect Bus PC I-E interface on the few stitch type LPC interface on the South Bridge chip and/or the peripheral component interconnect bus pci interface on the South Bridge chip and/or the South Bridge chip.
In conjunction with first kind of the third aspect and the third aspect possible implementation any one to the third possible implementation of the third aspect, in the 7th kind of possible implementation, described interface expanded circuit is complex programmable logic device (CPLD) or is on-site programmable gate array FPGA.
The beneficial effect of the embodiment of the invention comprises:
A kind of interface expanded circuit that the embodiment of the invention provides, interface method of extending and connecting and embedded system, by switch connecting circuit will at least two a BIOS chip in the BIOS chips link to each other with SPI on the South Bridge chip, and at least one the 2nd BIOS chip except a BIOS chip links to each other with the circuit that SPI can be provided at least two BIOS chips of general, thereby expand SPI indirectly, make the 2nd BIOS chip to upgrade by circuit and switching connecting circuit that SPI can be provided, and then when at least two BIOS chips are arranged in the system that comprises this interface expanded circuit, when South Bridge chip conducted interviews to a BIOS chip, the 2nd BIOS chip can be upgraded by circuit and switching connecting circuit that SPI can be provided.
Description of drawings
Fig. 1 is the synoptic diagram that two BIOS chips are connected with South Bridge chip in the prior art;
The synoptic diagram of one of annexation of the interface expanded circuit that Fig. 2 provides for the embodiment of the invention;
Two synoptic diagram of the annexation of the interface expanded circuit that Fig. 3 provides for the embodiment of the invention;
Three synoptic diagram of the annexation of the interface expanded circuit that Fig. 4 provides for the embodiment of the invention;
Four synoptic diagram of the annexation of the interface expanded circuit that Fig. 5 provides for the embodiment of the invention.
Embodiment
At present, two BIOS chips are connected implementation as shown in Figure 1 with South Bridge chip, and BIOS1 chip 11 and BIOS2 chip 12 are connected on the South Bridge chip 10 by same SPI.The chip selection signal CS of South Bridge chip 10 outputs is directly inputted in the BIOS1 chip, and chip selection signal CS is input in the BIOS2 chip through phase inverter 13.At system's run duration, select South Bridge chip 10 can visit which BIOS chip by the SPI of self by the high-low level of chip selection signal CS.
But in the process of the normal operation of processor, the firmware in the South Bridge chip also can irregularly be visited the BIOS chip at present.South Bridge chip for this type, if use connectivity scenario shown in Figure 1, then can share a SPI with BIOS chip and standby BIOS chip because of main, at CPU (central processing unit) (CPU, Center Processing Unit) in the time of will upgrading standby BIOS chip by South Bridge chip, South Bridge chip switches under the control of chip selection signal with standby BIOS chip and is connected, if the firmware in the South Bridge chip need be visited the main BIOS chip of using at this moment, because the BIOS chip that link to each other with the SPI of South Bridge chip this moment is standby BIOS chip, this and the main of visit before use the data in the BIOS chip different, therefore, it is unusual to cause system to occur, wherein, main is BIOS1 chip 11(or BIOS2 chip 12 with the BIOS chip), standby BIOS chip is BIOS2 chip 12(or BIOS1 chip 11).
A kind of interface expanded circuit, interface method of extending and connecting and embedded system that the embodiment of the invention provides, expand SPI indirectly by the circuit that SPI can be provided, thereby when being implemented in firmware in the South Bridge chip and pair conducting interviews with a BIOS chip, the circuit that the 2nd BIOS chip can be by can providing SPI and switch connecting circuit and upgrade.
Below in conjunction with Figure of description, the embodiment of a kind of interface expanded circuit, interface method of extending and connecting and the embedded system that the embodiment of the invention is provided describes.
The embodiment of the invention provides a kind of interface expanded circuit, and as shown in Figure 2, interface expanded circuit 21 comprises switching connecting circuit 211, switches connecting circuit 211 and connects at least two BIOS chips; Switch connecting circuit 211, be used for a BIOS chip 22 of at least two BIOS chips is linked to each other with serial peripheral interface SPI on the South Bridge chip 23; Switching connecting circuit 211 also is used at least two BIOS chips at least one the 2nd BIOS chip 24 except a BIOS chip 22 is linked to each other with the circuit 25 that SPI can be provided, make the 2nd BIOS chip 24 to upgrade by circuit 25 and switching connecting circuit 211 that SPI can be provided, namely make the 2nd BIOS chip 24 that links to each other with the circuit 25 that SPI can be provided to upgrade by circuit 25 and switching connecting circuit 211 that SPI can be provided.
Wherein, a BIOS chip is the BIOS chip that links to each other with SPI on the South Bridge chip, and the 2nd BIOS chip is other BIOS chip except a BIOS chip in a plurality of BIOS chips, and the 2nd BIOS chip all connects commutation circuit.
Because it is at present the framework of processor becomes increasingly complex, more and more abundanter with the content of depositing in two BIOS chips that SPI on the South Bridge chip is connected.Some South Bridge chip can arrange read-write protection to some zone in two BIOS chips by the SPI of self, and restriction is to the read-write operation of the BIOS chip of its connection.Therefore, when adopting the connected mode of South Bridge chip shown in Figure 1 and two BIOS chips, can't carry out erasable to whole standby BIOS chip, and when adopting connecting circuit shown in Figure 2, can upgrade with switching connecting circuit pair the 2nd DIOS chip that links to each other with the circuit that SPI can be provided by the circuit that SPI can be provided, that is to say can be by SPI can be provided circuit and the zone in switching connecting circuit pair the 2nd BIOS chip that links to each other with the circuit that SPI can be provided carry out erasable, namely can to BIOS chip that the circuit that SPI can be provided links to each other in part or all of zone carry out erasable.
Further, as shown in Figure 3, can provide the circuit of SPI to be connected to central processing unit CPU 26, switch connecting circuit 211 and link to each other with SPI on the CPU26, therefore, the circuit that SPI can be provided is the SPI on the CPU26; Switching connecting circuit 211 concrete being used for links to each other two BIOS chips at least one the 2nd BIOS chip 24 except a BIOS chip 22 at least with SPI on the CPU26, make the 2nd BIOS chip 24 and to switch connecting circuit 211 by the SPI on the CPU26 and upgrade, namely make and the 2nd BIOS chip 24 that the SPI on the CPU26 links to each other can be upgraded by the SPI on the CPU26 and switching connecting circuit 211.
When switching connecting circuit 211 and SPI on the CPU26 links to each other, can adopt the 2nd different BIOS chip 24 of known chip selection signal control technology control to link to each other with SPI on the CPU26 in the difference moment as two or more the 2nd BIOS chips 24.
Further, as shown in Figure 4, can provide the circuit 25 of SPI to comprise the change-over circuit 212 that is arranged in interface expanded circuit 21, change-over circuit 212 respectively with CPU26 on non-SPI with switch connecting circuit 211 and link to each other, namely change-over circuit 212 respectively with CPU26 on the IO interface of non-SPI link to each other with switching connecting circuit 211; Change-over circuit 212, be used for CPU26 when by the IO interface of non-SPI of self the 2nd BIOS chip 24 that switches connecting circuit 211 and connect being upgraded, the upgrading signal that the IO interface of the non-SPI on the CPU26 is sent is converted to the upgrading signal based on the SPI form.
In Fig. 4, change-over circuit 212 connects CPU26 by the IO interface of the non-SPI on the CPU26.Wherein, change-over circuit 212 can connect CPU26 by the IO interface of a non-SPI on the CPU26, also can connect CPU26 by the IO interface of a plurality of non-SPI on the CPU26.Equate with the quantity of SPI on the IO interface quantity of non-SPI on the CPU26 that change-over circuit 22 is connected and the change-over circuit 22.
Change-over circuit in the interface expanded circuit shown in Figure 4 connects CPU by the quick peripheral component interconnect Bus PC I-E interface on (PCI, the Peripheral Component Interconnect) interface of the peripheral component interconnect bus on the CPU and/or the CPU.Certainly, change-over circuit can also connect CPU by other IO interface on the CPU.
Further, as shown in Figure 5, can provide the circuit 25 of SPI to comprise the change-over circuit 212 that is arranged in interface expanded circuit 21, change-over circuit 212 respectively with South Bridge chip 23 on non-SPI with switch connecting circuit 211 and link to each other, namely change-over circuit 212 respectively with South Bridge chip 23 on the IO interface of non-SPI link to each other with switching connecting circuit 211; Change-over circuit 212, be used for when the IO interface of CPU by the non-SPI on the South Bridge chip upgraded to the 2nd BIOS chip that switches connecting circuit 211 and connect, the upgrading signal that the IO interface of the non-SPI on the South Bridge chip is sent is converted to the upgrading signal based on the SPI form.
In Fig. 5, change-over circuit 212 connects South Bridge chip 23 by the IO interface of the non-SPI on the South Bridge chip 23.Wherein, change-over circuit 212 can connect South Bridge chip 23 by the IO interface of a non-SPI on the South Bridge chip 23, also can connect South Bridge chip 23 by the IO interface of a plurality of non-SPI on the South Bridge chip 23.Equal the quantity of the SPI on the change-over circuit 212 with the quantity of the IO interface of non-SPI on the South Bridge chip 23 that change-over circuit 212 is connected.
Change-over circuit in the interface expanded circuit shown in Figure 5 connects South Bridge chip by at least a interface in the following interface on the South Bridge chip: few stitch type (LPC, Low Pin Count) interface, pci interface, PCI-E interface.Certainly, change-over circuit can also connect South Bridge chip by the IO interface of other the non-SPI on the South Bridge chip.
Further, when the switching connecting circuit 211 among Fig. 2-Fig. 5 also is used for resetting in the system that comprises BIOS chip, South Bridge chip and CPU, with a BIOS chip 22 from state that SPI on the South Bridge chip 23 links to each other under switch to the state that links to each other with the circuit 25 that SPI can be provided, and with the 2nd BIOS chip 24 from state that the circuit 25 that SPI can be provided links to each other under switch to the state that links to each other with SPI on the South Bridge chip 23.
Particularly, when switching connecting circuit 211 only links to each other the 2nd a BIOS chip 24 with the circuit 25 that SPI can be provided, the 2nd BIOS chip is standby BIOS chip, when switching connecting circuit 211 and being used for resetting in the system that comprises BIOS chip, South Bridge chip and CPU, with a BIOS chip 22 from state that SPI on the South Bridge chip 23 links to each other under switch to the state that links to each other with the circuit 25 that SPI can be provided, and with standby BIOS chip from state that the circuit 25 that SPI can be provided links to each other under switch to the state that links to each other with SPI on the South Bridge chip 23.When switching connecting circuit 211 links to each other a plurality of the 2nd BIOS chips 24 with the circuit 25 that SPI can be provided, the 2nd BIOS chip that links to each other with the circuit 25 that SPI can be provided is standby BIOS chip, switching connecting circuit 211 is used for comprising the BIOS chip, when the system of South Bridge chip and CPU resets, with a BIOS chip 22 from state that SPI on the South Bridge chip 23 links to each other under switch to the state that links to each other with the circuit 25 that SPI can be provided, and from a plurality of standby BIOS chips, select a BIOS chip, and with the BIOS chip selected from state that the circuit 25 that SPI can be provided links to each other under switch to the state that links to each other with SPI on the South Bridge chip 23.
Like this, when the BIOS chip that is connected with the SPI of South Bridge chip went wrong, the user can reset by the system that will comprise BIOS chip, South Bridge chip and CPU, changed the BIOS chip that the SPI on the South Bridge chip connects.
Further, when switching connecting circuit and also being used for powering on for the first time in the system that comprises South Bridge chip, BIOS chip and CPU, the signal of the BIOS chip that links to each other according to be used for determining of receiving and the SPI on the South Bridge chip, BIOS chip of selection links to each other with SPI on the South Bridge chip from the BIOS chip that links to each other with self.
The interface expanded circuit that the embodiment of the invention provides can be CPLD (CPLD, Complex Programmable Logic Device) or be field programmable gate array (FPGA, Field Programmable Gate Array), can also be the circuit of other device composition.
The embodiment of the invention also provides a kind of interface method of extending and connecting, comprising: by switching connecting circuit, the BIOS chip at least two BIOS chips is linked to each other with serial peripheral interface SPI on the South Bridge chip; By switching connecting circuit, with the 2nd BIOS chip of at least one except a BIOS chip at least two BIOS chips, link to each other with the circuit that SPI can be provided, make the 2nd BIOS chip the circuit of SPI can be provided and switch connecting circuit by this and upgrade, namely make the 2nd BIOS chip that links to each other with the circuit that SPI can be provided the circuit of SPI can be provided and switch connecting circuit by this and upgrade.
Further, by switching connecting circuit with at least one the 2nd BIOS chip, link to each other with the circuit that SPI can be provided, making the 2nd BIOS chip the circuit of SPI can be provided and switch connecting circuit by this upgrades, comprise: by switching connecting circuit with at least one the 2nd BIOS chip except a BIOS chip at least two BIOS chips, link to each other with the SPI on the CPU, make the 2nd BIOS chip and to switch connecting circuit by the SPI on this CPU and upgrade, namely make and the 2nd BIOS chip that the SPI on the CPU links to each other can be upgraded by the SPI on this CPU and switching connecting circuit.
Further, by switching connecting circuit with at least one the 2nd BIOS chip, link to each other with the circuit that SPI can be provided, making the 2nd BIOS chip the circuit of SPI can be provided and switch connecting circuit by this upgrades, comprise: by switching connecting circuit with at least one the 2nd BIOS chip except a BIOS chip at least two BIOS chips, IO interface by the non-SPI on change-over circuit and the CPU links to each other, make the 2nd BIOS chip upgrade in IO interface and switching connecting circuit by the non-SPI on the described CPU, namely make the 2nd BIOS chip that links to each other with the IO interface of non-SPI on the CPU in the IO interface by the non-SPI on the described CPU and switch connecting circuit when upgrading that the upgrading signal that the IO interface of the non-SPI on the CPU is sent by the change-over circuit that links to each other with the switching connecting circuit is converted to the upgrading signal based on the SPI form.
Further, by switching connecting circuit with at least one the 2nd BIOS chip, link to each other with the circuit that SPI can be provided, making the 2nd BIOS chip the circuit of SPI can be provided and switch connecting circuit by this upgrades, comprise: by switching connecting circuit with at least one the 2nd BIOS chip except a BIOS chip at least two BIOS chips, IO interface by the non-SPI on change-over circuit and the South Bridge chip links to each other, make the 2nd BIOS chip upgrade in IO interface and switching connecting circuit by the non-SPI on the South Bridge chip, namely make the 2nd BIOS chip that links to each other with the IO interface of non-SPI on the South Bridge chip in the IO interface by the non-SPI on the South Bridge chip and switch connecting circuit when upgrading that the upgrading signal that the non-SPI on the South Bridge chip is sent by the change-over circuit that links to each other with the switching connecting circuit is converted to the upgrading signal based on the SPI form.
Further, the interface method of extending and connecting that the embodiment of the invention provides, also comprise: when resetting in the system that comprises South Bridge chip, BIOS chip and CPU, by switch connecting circuit with a BIOS chip from state that SPI on the South Bridge chip links to each other under switch to the state that links to each other with the circuit that SPI can be provided, and with the 2nd BIOS chip from state that the circuit that SPI can be provided links to each other under switch to the state that links to each other with SPI on the South Bridge chip.
Particularly, when only having the 2nd a BIOS chip to link to each other with the circuit that SPI can be provided by switching connecting circuit, the 2nd BIOS chip is standby BIOS chip, when the system that comprises BIOS chip, South Bridge chip and CPU resets, by switching connecting circuit the one BIOS chip is switched to the state that links to each other with the circuit that SPI can be provided from the state that links to each other with SPI on the South Bridge chip, and standby BIOS chip is switched to the state that links to each other with SPI on the South Bridge chip from the state that links to each other with the circuit that SPI can be provided.When a plurality of the 2nd BIOS chips link to each other with the circuit that SPI can be provided, the 2nd BIOS chip that links to each other with the circuit that SPI can be provided is standby BIOS chip, comprising the BIOS chip, when the system of South Bridge chip and CPU resets, by switching connecting circuit the one BIOS chip is switched to the state that links to each other with the circuit that SPI can be provided from the state that links to each other with SPI on the South Bridge chip, and from a plurality of standby BIOS chips, select a BIOS chip, and the BIOS chip selected is switched to the state that links to each other with SPI on the South Bridge chip from the state that links to each other with the circuit that SPI can be provided.
Like this, when the BIOS chip that is connected with the SPI of South Bridge chip went wrong, the user can change the BIOS chip that the SPI on the South Bridge chip connects by system is resetted.
The embodiment of the invention also provides a kind of embedded system, as shown in Figure 2, comprise at least two basic input-output system BIOS chips and South Bridge chip 23, this embedded system also comprises interface expanded circuit 21, interface expanded circuit 21 comprises switching connecting circuit 211, switches connecting circuit 211 and connects at least two basic input-output system BIOS chips; Switch connecting circuit 211, be used for a BIOS chip 22 of at least two BIOS chips is linked to each other with serial peripheral interface SPI on the South Bridge chip 23; Switching connecting circuit 211 also is used at least two BIOS chips at least one the 2nd BIOS chip 24 except a described BIOS chip 22 is linked to each other with the circuit 25 that SPI can be provided, make the 2nd BIOS chip 24 to upgrade by circuit 25 and switching connecting circuit 211 that SPI can be provided, namely make the 2nd BIOS chip 24 that links to each other with the circuit 25 that SPI can be provided to upgrade by circuit 25 and switching connecting circuit 211 that SPI can be provided.
Further, as shown in Figure 3, can provide the circuit of SPI to be connected to central processing unit CPU 26, switch connecting circuit 211 and link to each other with SPI on the CPU26, therefore, the circuit that SPI can be provided is the SPI on the CPU26; Switching connecting circuit 211 concrete being used for links to each other two BIOS chips at least one the 2nd BIOS chip 24 except a described BIOS chip 22 at least with SPI on the CPU26, make the 2nd BIOS chip 24 and to switch connecting circuit 211 by the SPI on the CPU26 and upgrade, namely make and the 2nd BIOS chip 24 that the SPI on the CPU26 links to each other can be upgraded by the SPI on the CPU26 and switching connecting circuit 211.
When switching connecting circuit 211 and SPI on the CPU26 links to each other, can adopt different the 2nd BIOS chip 24 of the different moment of chip selection signal control to link to each other with SPI on the CPU26 as two or more the 2nd BIOS chips 24.
Further, as shown in Figure 4, can provide the circuit 25 of SPI to comprise the change-over circuit 212 that is arranged in interface expanded circuit 21, change-over circuit 212 respectively with CPU26 on non-SPI IO interface with switch connecting circuit 211 and link to each other; Change-over circuit 212, be used for CPU26 when by the IO interface of non-SPI of self the 2nd BIOS chip 24 that switches connecting circuit 211 and connect being upgraded, the upgrading signal that the IO interface of the non-SPI on the CPU26 is sent is converted to the upgrading signal based on the SPI form.
Change-over circuit in the interface expanded circuit shown in Figure 4 connects CPU by the pci interface on the CPU and/or the PCI-E interface on the CPU.Certainly, change-over circuit can also connect CPU by other IO interface on the CPU.
Further, as shown in Figure 5, can provide the circuit 25 of SPI to comprise the change-over circuit 212 that is arranged in interface expanded circuit 21, change-over circuit 212 respectively with South Bridge chip 23 on non-SPI IO interface with switch connecting circuit 211 and link to each other; Change-over circuit 212, be used for when the IO interface of CPU by the non-SPI on the South Bridge chip 23 upgraded to the 2nd BIOS chip 24 that switches connecting circuit 211 and connect, the upgrading signal that the IO interface of the non-SPI on the South Bridge chip 23 is sent is converted to the upgrading signal based on the SPI form.
Change-over circuit in the interface expanded circuit shown in Figure 5 connects South Bridge chip by at least a interface in the following interface on the South Bridge chip: LPC interface pci interface, PCI-E interface.Certainly, change-over circuit can also connect South Bridge chip by the IO interface of other the non-SPI on the South Bridge chip.
Further, switching connecting circuit 211 among Fig. 2-Fig. 5, also be used for when embedded system resets, with a BIOS chip 22 from state that SPI on the South Bridge chip 23 links to each other under switch to the state that links to each other with the circuit 25 that SPI can be provided, and with the 2nd BIOS chip 24 from state that the circuit 25 that SPI can be provided links to each other under switch to the state that links to each other with SPI on the South Bridge chip 23.
Particularly, when switching connecting circuit 211 only links to each other the 2nd a BIOS chip 24 with the circuit 25 that SPI can be provided, the 2nd BIOS chip is standby BIOS chip, switching connecting circuit 211 is used for when this embedded system resets, with a BIOS chip 22 from state that SPI on the South Bridge chip 23 links to each other under switch to the state that links to each other with the circuit 25 that SPI can be provided, and with standby BIOS chip from state that the circuit 25 that SPI can be provided links to each other under switch to the state that links to each other with SPI on the South Bridge chip 23.When switching connecting circuit 211 links to each other a plurality of the 2nd BIOS chips 24 with the circuit 25 that SPI can be provided, the 2nd BIOS chip that links to each other with the circuit 25 that SPI can be provided is standby BIOS chip, switching connecting circuit 211 is used for when this embedded system resets, with a BIOS chip 22 from state that SPI on the South Bridge chip 23 links to each other under switch to the state that links to each other with the circuit 25 that SPI can be provided, and from a plurality of standby BIOS chips, select a BIOS chip, and with the BIOS chip selected from state that the circuit 25 that SPI can be provided links to each other under switch to the state that links to each other with SPI on the South Bridge chip 23.
Through the above description of the embodiments, those skilled in the art can be well understood to the embodiment of the invention and can realize by hardware, also can realize by the mode that software adds necessary general hardware platform.Based on such understanding, the technical scheme of the embodiment of the invention can embody with the form of software product, it (can be CD-ROM that this software product can be stored in a non-volatile memory medium, USB flash disk, portable hard drive etc.) in, comprise some instructions with so that computer equipment (can be personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the present invention.
It will be appreciated by those skilled in the art that accompanying drawing is the synoptic diagram of a preferred embodiment, the module in the accompanying drawing or flow process might not be that enforcement the present invention is necessary.
It will be appreciated by those skilled in the art that the module in the device among the embodiment can be distributed in the device of embodiment according to the embodiment description, also can carry out respective change and be arranged in the one or more devices that are different from present embodiment.The module of above-described embodiment can be merged into a module, also can further split into a plurality of submodules.
The invention described above embodiment sequence number does not represent the quality of embodiment just to description.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (15)
1. an interface expanded circuit is characterized in that, described interface expanded circuit comprises the switching connecting circuit, and described switching connecting circuit connects at least two basic input-output system BIOS chips;
Described switching connecting circuit is used for a BIOS chip of described at least two BIOS chips is linked to each other with serial peripheral interface SPI on the South Bridge chip;
Described switching connecting circuit also is used for described at least two BIOS chips at least one the 2nd BIOS chip except a BIOS chip is linked to each other with the circuit that SPI can be provided, and makes described the 2nd BIOS chip to upgrade by the described circuit of SPI and the described switching connecting circuit of can providing.
2. interface expanded circuit as claimed in claim 1 is characterized in that, the described circuit of SPI that can provide is connected to central processing unit CPU, and described switching connecting circuit links to each other with SPI on the described CPU;
Described switching connecting circuit specifically is used for described at least two BIOS chips at least one the 2nd BIOS chip except a BIOS chip is linked to each other with SPI on the CPU, makes described the 2nd BIOS chip to upgrade by the SPI on the described CPU and described switching connecting circuit.
3. interface expanded circuit as claimed in claim 1 is characterized in that, the described circuit of SPI that can provide comprises the change-over circuit that is arranged in described interface expanded circuit, described change-over circuit respectively with CPU on non-SPI link to each other with described switching connecting circuit;
Described change-over circuit is used for described CPU when the non-SPI by self upgrades to described the 2nd BIOS chip that switches connecting circuit and connect, and the upgrading signal that the non-SPI on the described CPU is sent is converted to the upgrading signal based on the SPI form.
4. interface expanded circuit as claimed in claim 1, it is characterized in that, the described circuit of SPI that can provide comprises the change-over circuit that is arranged in described interface expanded circuit, described change-over circuit respectively with South Bridge chip on non-SPI link to each other with described switching connecting circuit;
Described change-over circuit is used for when CPU upgrades to the 2nd BIOS chip that switches connecting circuit and connect by the non-SPI on the South Bridge chip, and the upgrading signal that the non-SPI on the South Bridge chip is sent is converted to the upgrading signal based on the SPI form.
5. as the arbitrary described interface expanded circuit of claim 1～4, it is characterized in that, described switching connecting circuit, when also being used for resetting in system, with a described BIOS chip from state that SPI on the described South Bridge chip links to each other under switch to the state that links to each other with the circuit that SPI can be provided, and with described the 2nd BIOS chip from state that the circuit that SPI can be provided links to each other under switch to the state that links to each other with SPI on the described South Bridge chip.
6. an interface method of extending and connecting is characterized in that, comprising:
By switching connecting circuit, the BIOS chip at least two BIOS chips is linked to each other with serial peripheral interface SPI on the South Bridge chip;
By described switching connecting circuit, with at least one the 2nd BIOS chip except a BIOS chip in described at least two BIOS chips, link to each other with the circuit that SPI can be provided, make described the 2nd BIOS chip to upgrade by the described circuit of SPI and the described switching connecting circuit of can providing.
7. method as claimed in claim 6, it is characterized in that, described by switching connecting circuit with described at least one the 2nd BIOS chip, link to each other with the circuit that SPI can be provided, make described the 2nd BIOS chip to upgrade by the described circuit of SPI and the described switching connecting circuit of can providing, comprising:
By described switching connecting circuit with at least one the 2nd BIOS chip except a BIOS chip in described at least two BIOS chips, link to each other with the SPI on the CPU, make described the 2nd BIOS chip to upgrade by the SPI on the described CPU and described switching connecting circuit.
8. method as claimed in claim 6, it is characterized in that, described by switching connecting circuit with described at least one the 2nd BIOS chip, link to each other with the circuit that SPI can be provided, make described the 2nd BIOS chip to upgrade by the described circuit of SPI and the described switching connecting circuit of can providing, comprising:
By described switching connecting circuit with at least one the 2nd BIOS chip except a BIOS chip in described at least two BIOS chips, link to each other with non-SPI on the CPU by change-over circuit, make described the 2nd BIOS chip when upgrading by the non-SPI on the described CPU and described switching connecting circuit, by with switch upgrading signal that change-over circuit that connecting circuit links to each other sends the non-SPI on the CPU and be converted to upgrading signal based on the SPI form.
9. method as claimed in claim 6, it is characterized in that, described by switching connecting circuit with described at least one the 2nd BIOS chip, link to each other with the circuit that SPI can be provided, make described the 2nd BIOS chip to upgrade by the described circuit of SPI and the described switching connecting circuit of can providing, comprising:
By described switching connecting circuit with at least one the 2nd BIOS chip except a BIOS chip in described at least two BIOS chips, link to each other with non-SPI on the South Bridge chip by change-over circuit, make described the 2nd BIOS chip when upgrading by the non-SPI on the described South Bridge chip and described switching connecting circuit, by with switch upgrading signal that change-over circuit that connecting circuit links to each other sends the non-SPI on the South Bridge chip and be converted to upgrading signal based on the SPI form.
10. as the arbitrary described method of claim 6～9, it is characterized in that described method also comprises:
When system resets, by described switching connecting circuit with a BIOS chip from state that SPI on the South Bridge chip links to each other under switch to the state that links to each other with the circuit that SPI can be provided, and with the 2nd BIOS chip from state that the circuit that SPI can be provided links to each other under switch to the state that links to each other with SPI on the South Bridge chip.
11. embedded system, comprise at least two basic input-output system BIOS chips and South Bridge chip, it is characterized in that, also comprise the interface expanded circuit, described interface expanded circuit comprises the switching connecting circuit, and described switching connecting circuit connects described at least two basic input-output system BIOS chips;
Described switching connecting circuit is used for a BIOS chip of described at least two BIOS chips is linked to each other with serial peripheral interface SPI on the described South Bridge chip;
Described switching connecting circuit also is used for described at least two BIOS chips at least one the 2nd BIOS chip except a described BIOS chip is linked to each other with the circuit that SPI can be provided, and makes described the 2nd BIOS chip to upgrade by the described circuit of SPI and the described switching connecting circuit of can providing.
12. embedded system as claimed in claim 11 is characterized in that, the described circuit of SPI that can provide is connected to central processing unit CPU, and described switching connecting circuit links to each other with SPI on the described CPU;
Described switching connecting circuit specifically is used for described at least two BIOS chips at least one the 2nd BIOS chip except a described BIOS chip is linked to each other with SPI on the CPU, makes described the 2nd BIOS chip to upgrade by the SPI on the described CPU and described switching connecting circuit.
13. embedded system as claimed in claim 11 is characterized in that, the described circuit of SPI that can provide comprises the change-over circuit that is arranged in described interface expanded circuit, described change-over circuit respectively with CPU on non-SPI link to each other with described switching connecting circuit;
Described change-over circuit is used for CPU when the non-SPI by self upgrades to the 2nd BIOS chip that switches connecting circuit and connect, and the upgrading signal that the non-SPI on the described CPU is sent is converted to the upgrading signal based on the SPI form.
14. embedded system as claimed in claim 11, it is characterized in that, the described circuit of SPI that can provide comprises the change-over circuit that is arranged in described interface expanded circuit, described change-over circuit respectively with South Bridge chip on non-SPI link to each other with described switching connecting circuit;
Described change-over circuit is used for when CPU upgrades to the 2nd BIOS chip that switches connecting circuit and connect by the non-SPI on the South Bridge chip, and the upgrading signal that the non-SPI on the South Bridge chip is sent is converted to the upgrading signal based on the SPI form.
15. as the arbitrary described embedded system of claim 11～14, it is characterized in that, described switching connecting circuit, when also being used for resetting in system, with a described BIOS chip from state that SPI on the described South Bridge chip links to each other under switch to the state that links to each other with the circuit that SPI can be provided, and with described the 2nd BIOS chip from state that the circuit that SPI can be provided links to each other under switch to the state that links to each other with SPI on the described South Bridge chip.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310137959.5A CN103268302B (en) | 2013-04-19 | 2013-04-19 | A kind of Interface Expanding circuit, Interface Expanding method of attachment and embedded system |
| PCT/CN2014/071985 WO2014169727A1 (en) | 2013-04-19 | 2014-02-12 | Interface expanding circuit, interface expanding connecting method, and embedded system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310137959.5A CN103268302B (en) | 2013-04-19 | 2013-04-19 | A kind of Interface Expanding circuit, Interface Expanding method of attachment and embedded system |
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| Publication Number | Publication Date |
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| CN103268302A true CN103268302A (en) | 2013-08-28 |
| CN103268302B CN103268302B (en) | 2016-08-03 |
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| CN201310137959.5A Active CN103268302B (en) | 2013-04-19 | 2013-04-19 | A kind of Interface Expanding circuit, Interface Expanding method of attachment and embedded system |
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| CN (1) | CN103268302B (en) |
| WO (1) | WO2014169727A1 (en) |
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| WO2014169727A1 (en) * | 2013-04-19 | 2014-10-23 | 华为技术有限公司 | Interface expanding circuit, interface expanding connecting method, and embedded system |
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| CN104618121A (en) * | 2015-01-29 | 2015-05-13 | 曙光云计算技术有限公司 | Switch and server system |
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| CN110401586A (en) * | 2019-07-26 | 2019-11-01 | 广东浪潮大数据研究有限公司 | A kind of bus communication, device, equipment and readable storage medium storing program for executing |
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| WO2014169727A1 (en) | 2014-10-23 |
| CN103268302B (en) | 2016-08-03 |
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Effective date of registration: 20211222 Address after: 450046 Floor 9, building 1, Zhengshang Boya Plaza, Longzihu wisdom Island, Zhengdong New Area, Zhengzhou City, Henan Province Patentee after: xFusion Digital Technologies Co., Ltd. Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: HUAWEI TECHNOLOGIES Co.,Ltd. |