CN103248797A - Video resolution enhancing method and module based on FPGA (field programmable gate array) - Google Patents
Video resolution enhancing method and module based on FPGA (field programmable gate array) Download PDFInfo
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Abstract
The invention relates to a processing method and a hardware module for enhancing the resolution of a digital video file with an ordinary resolution and then outputting the digital video file onto a high-definition display device for real time display. The method comprises the following steps of sequentially storing each frame image of a digital video material with low resolution rate into a cache of a FPGA embedded system; utilizing a standard interpolation algorithm (bilinear interpolation and bicubic interpolation and the like) to reasonably estimate and insert an undefined pixel value between two adjacent pixel point on each frame image, amplifying each frame image, maintaining the smoothness and contrast ratio of the image, improving the resolution rate of each frame image, i.e. the resolution rate of the video; and finally, sequentially and continuously outputting each processed frame image to the display device. The method and the module can be widely applied to the fields such as family life, medical imaging, security monitoring, intelligent car control and outdoor video advertisement and has the characteristics of high output resolution rate, strong real-time property, small size, simplicity and convenience in operation, low cost, high reliability and the like.
Description
Technical field
The present invention relates to a kind of field of video processing, output to processing method and the hardware module that the high definition display device shows in real time after especially the resolution of the digital video file of common resolution can being strengthened.
Background technology
The resolution of HD video commonly used mainly contains 720P(1280 * 720) and 1080p(1920 * 1080) etc. form.Watch real HD video, except the high definition display device, also need the high-definition video signal source that is complementary.The data volume of high-definition signal is huge, is a very big challenge to current storage system.Comparatively speaking, the advantage that non-HD video has aboundresources, data volume is little and be easy to store.Produced the lower DVD film of a large amount of resolution in the past, and the video camera that remains low resolution of fields employings such as present medical image, security monitoring and intelligent vehicle control, therefore realize that the broadcast of low-resolution video on high-resolution display device is exigence.If yet with low resolution video signal, be that 720 * 576 standard definition television signal is directly inputted in the HDTV and plays such as resolution, because vision signal resolution is less than monitor resolution, then several pixels of display show the same pixel of input signal, tangible mosaic effect appears.
Be the resolution that the super-resolution rebuilding technology of cost can improve image effectively to sacrifice video frame rate.By extracting spatial domain and time-domain information additional in the image sequence, utilize the image of multiframe low resolution can generate the image of a vertical frame dimension resolution.Yet, because the super-resolution rebuilding technology is with the synthetic frame of multiple image, in order to meet the video playback requirement of 60 frame per seconds, must adopts 240 frame per seconds even higher high frame per second signal, otherwise can't realize continuous broadcast.On the one hand the high-frequency frame transducer is expensive, and current on the other hand super-resolution rebuilding algorithm also can't be handled continuous vision signal rapidly, so the super-resolution rebuilding technology can not be used for improving in real time the resolution of vision signal.
One piece of prospectus CN101639932B of Chinese patent has described the method and system that a kind of digital image resolution strengthens.The method mainly comprises: image interpolation, carry out the arest neighbors interpolation to the luminance graph of low-resolution image; Improve the Bayes image interpolation model; Interpolation correction is with the luminance graph of improved Bayes image interpolation type correction high-definition picture.At coloured image, the method provides image preliminary treatment and reprocessing, and the former carries out color space conversion to the low resolution coloured image of input, and the high-resolution luminance graph after the latter will proofread and correct becomes coloured image with chromatic component figure reverse conversion.The problem that the method is huge at original Bayes's interpolation method amount of calculation, execution speed is slow by determining descent direction and step-length fast, has been accelerated the execution of interpolation, has the edge hold facility simultaneously, and effectively restoring image detail improves image definition.Yet the method adopts is that the method for software is carried out interpolation to picture signal, thereby can not carry out real-time processing to the bigger vision signal of data volume.
The present invention combines field programmable gate array (FPGA) hardware programming and video signal interpolation, can improve the resolution of existing non-high-definition video signal in real time, eliminate mosaic effect, thereby the non-HD video that will enrich video format with high definition in the high definition display device plays back.Therefore, the low cost that can in the high definition display device, play as a kind of non-HD video of the present invention and effective solution.
Summary of the invention
The technical problem that the present invention mainly solves be design and provide a kind of original video material that will have common resolution to strengthen resolution after output to processing method and the hardware module that the high definition display device shows in real time.The present invention adopts the standard interpolation algorithm that each two field picture the original video stream is amplified from principle, utilize high speed data transfer and the handling property of FPGA, especially powerful concurrent operation ability, the reading of digital video file, processing and output procedure are combined closely, thereby the video resolution that obtains a kind of hard real-time strengthens module, low resolution digital video material and high-resolution display device are mated well, solved under the different situation of resolution and shown fuzzy drawback, and video super-resolution reconstruction technique time overhead excessive defective.
The present invention is mainly used in fields such as family life, medical image, security monitoring, intelligent vehicle control, outdoor video advertisement, have characteristics such as output resolution ratio height, real-time, miniaturization, easy and simple to handle, with low cost, reliability height, satisfy the general requirement that people show high-resolution.The technical solution adopted in the present invention is: at first will be generally the low resolution video camera from the digital video input equipment 4(of low resolution, DVD player etc.) each two field picture of video file, under the control of fpga chip 2, store into successively in the buffer memory RAM memory 3 of FPGA embedded system 1; Utilize standard interpolation algorithm (bilinear interpolation then, bicubic interpolation etc.) undefined pixel value between two neighbor pixels on every two field picture is reasonably estimated and insertion, amplify each two field picture, and flatness and the contrast of maintenance image, thereby improve the resolution of every two field picture, i.e. the resolution of video; The every two field picture that to handle at last outputs to high-resolution display device 5 successively continuously and shows.
The designed video resolution based on FPGA of the present invention strengthens module and has following characteristics:
1. integrated level height, good portability, the chip of all uses and electronic devices and components all are integrated on the circuit board, and volume is little, and is in light weight;
2. with low cost, employed all is FPGA and the related chip of entry level, is beneficial to large-scale production;
3. employing modularized design, simple in structure, be convenient to assembling and debugging;
4. the design of digitizer has guaranteed high stability.
Description of drawings
The video resolution that Fig. 1 is based on FPGA strengthens the Hardware Design block diagram
Fig. 2 is the pile line operation block diagram of FPGA processing video frames image
Embodiment
Provide specific implementation method below in conjunction with accompanying drawing, further specify the video resolution Enhancement Method based on FPGA of the present invention and Module Design and adjustment method.
The refresh rate of general video source is generally 60Hz, and namely per second is exported 60 two field pictures, and the transfer of data of video source and receiver is with the sign of field sync signal (VSYNC) as every two field picture.In resolution enhancing process of the present invention, be the cycle with the field sync signal, the input to each two field picture of video of design, interpolation are amplified and output need take three cycles altogether.At first send control signal by FPGA, first field signal in the cycle output interface by video camera or DVD 4 the N two field picture of digital video file is cached in the RAM memory 3 of embedded development plate; At second field signal in the cycle, N+1 two field picture to buffer memory carries out interpolation and amplification by standard interpolation algorithm (bilinear interpolation and bicubic interpolation etc.), while is based on the high-speed parallel operational performance of fpga chip 2, with second two field picture of other memory space buffer memory video on the RAM memory 3 of embedded development plate; The 3rd field signal be in the cycle, and the N two field picture after will amplifying by video output interface outputs to display device, handles the N+1 two field picture of buffer memory simultaneously, and reads in the N+2 two field picture of video.Angle from the hardware effort flow process, this is a kind of pile line operation, FPGA transmits control signal to video input apparatus and display device simultaneously, receives and the transmission data by different interfaces, and the disposal ability of its high-speed parallel has obtained maximum development and use.Angle from sequential, because it is very fast based on the made of hardware circuits which process speed image of FPGA, only need in this example can satisfy the hard real time requirement continuously at the high-resolution video of high-resolution display device 5 outputs on display device through the time-delay (2/60 second) in two field signal cycles.From the angle of occupying system resources, each step only needs buffer memory three two field pictures simultaneously, and the memory space that needs is very little.
Simultaneously the invention process the interpolation algorithm of arest neighbors interpolation, Bayes's interpolation and fractal interpolation etc. carry out the amplification of image, this algorithm all drops within the protection range of the present invention.
Claims (4)
1. method and module that strengthens based on the video resolution of FPGA, its body is FPGA embedded system (1), by fpga chip (2), memory RAM (3) is integrated on the block system development board to be formed, fpga chip (2) transmits control signal simultaneously to two ancillary equipment, the invention is characterized in: utilize based on the high-speed hardware circuit of FPGA and realize the high-speed real-time of video is handled and output, with field sync signal cycle of input video reference period as operation, the workflow of fpga chip (2) is divided into the pile line operation of three steps: first cycle is read in first two field picture and buffer memory from input equipment (4), the image of second period interpolation processing buffer memory, and continue to read in second two field picture and buffer memory from input equipment (4), the 3rd cycle exported the image of having handled to display device (5), interpolation processing second two field picture, and read in the 3rd two field picture, flow process is proceeded according to this, finishes or interrupts up to video input; With the field sync signal of input video directly as the field sync signal of output video, thereby realize that output video is identical with the input video frame rate.
2. according to method and the module of the described video resolution enhancing of claim 1, it is characterized in that: ancillary equipment is low-resolution video input equipment (4), high-resolution display device (5).
3. method and the module that strengthens according to the described video resolution of claim 1, it is characterized in that: fpga chip (2) is connected with the FPGA data/address bus with memory RAM (3), is connected by the normal video interface between FPGA embedded system (1) and ancillary equipment (4), (5).
4. method and the module that strengthens according to the described video resolution of claim 1 is characterized in that: realized multiple different image interpolation algorithm based on the hardware circuit of FPGA.
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Cited By (13)
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| CN103646378A (en) * | 2013-11-15 | 2014-03-19 | 天津天地伟业数码科技有限公司 | High reduction degree spatial domain image zooming method based on FPGA platform |
| CN104219529A (en) * | 2014-09-02 | 2014-12-17 | 广东威创视讯科技股份有限公司 | Image scaling method, system and device |
| CN105160622A (en) * | 2015-09-25 | 2015-12-16 | 南京铁道职业技术学院 | Field programmable gate array (FPGA) based implementation method for image super resolution |
| CN103929599B (en) * | 2014-04-30 | 2017-01-25 | 哈尔滨工程大学 | Digital video image real-time zooming method based on FPGA |
| CN107155131A (en) * | 2016-03-02 | 2017-09-12 | 王进洪 | A kind of video image resolution processes system and method |
| CN107507147A (en) * | 2017-08-29 | 2017-12-22 | 丹阳华神电器有限公司 | A kind of image intelligent restoring method and device for medical display device |
| CN108769583A (en) * | 2018-05-24 | 2018-11-06 | 上海大学 | A kind of superfine electric scope high definition interpolating module and method based on FPGA |
| CN110555800A (en) * | 2018-05-30 | 2019-12-10 | 北京三星通信技术研究有限公司 | image processing apparatus and method |
| CN111028752A (en) * | 2019-11-20 | 2020-04-17 | 深圳市鑫乐意科技有限公司 | Method for converting LVDS signal into RSDS signal |
| CN111314741A (en) * | 2020-05-15 | 2020-06-19 | 腾讯科技（深圳）有限公司 | Video super-resolution processing method and device, electronic equipment and storage medium |
| CN112764377A (en) * | 2020-12-30 | 2021-05-07 | 中国科学院长春光学精密机械与物理研究所 | Real-time line time adjusting device and method for push-broom optical remote sensing camera |
| CN115829842A (en) * | 2023-01-05 | 2023-03-21 | 武汉图科智能科技有限公司 | Device for realizing picture super-resolution reconstruction based on FPGA |
| CN116886996A (en) * | 2023-09-06 | 2023-10-13 | 浙江富控创联技术有限公司 | Digital village multimedia display screen broadcasting system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103646378A (en) * | 2013-11-15 | 2014-03-19 | 天津天地伟业数码科技有限公司 | High reduction degree spatial domain image zooming method based on FPGA platform |
| CN103929599B (en) * | 2014-04-30 | 2017-01-25 | 哈尔滨工程大学 | Digital video image real-time zooming method based on FPGA |
| CN104219529A (en) * | 2014-09-02 | 2014-12-17 | 广东威创视讯科技股份有限公司 | Image scaling method, system and device |
| CN104219529B (en) * | 2014-09-02 | 2018-09-25 | 广东威创视讯科技股份有限公司 | Image-scaling method, system and device |
| CN105160622A (en) * | 2015-09-25 | 2015-12-16 | 南京铁道职业技术学院 | Field programmable gate array (FPGA) based implementation method for image super resolution |
| CN105160622B (en) * | 2015-09-25 | 2018-08-31 | 南京铁道职业技术学院 | The implementation method of image super-resolution based on FPGA |
| CN107155131A (en) * | 2016-03-02 | 2017-09-12 | 王进洪 | A kind of video image resolution processes system and method |
| CN107507147A (en) * | 2017-08-29 | 2017-12-22 | 丹阳华神电器有限公司 | A kind of image intelligent restoring method and device for medical display device |
| CN108769583A (en) * | 2018-05-24 | 2018-11-06 | 上海大学 | A kind of superfine electric scope high definition interpolating module and method based on FPGA |
| US11967045B2 (en) | 2018-05-30 | 2024-04-23 | Samsung Electronics Co., Ltd | Image processing device and method |
| CN110555800A (en) * | 2018-05-30 | 2019-12-10 | 北京三星通信技术研究有限公司 | image processing apparatus and method |
| CN111028752A (en) * | 2019-11-20 | 2020-04-17 | 深圳市鑫乐意科技有限公司 | Method for converting LVDS signal into RSDS signal |
| CN111028752B (en) * | 2019-11-20 | 2023-09-01 | 深圳市鑫乐意科技有限公司 | Method for converting LVDS signals into RSDS signals |
| CN111314741A (en) * | 2020-05-15 | 2020-06-19 | 腾讯科技（深圳）有限公司 | Video super-resolution processing method and device, electronic equipment and storage medium |
| CN112764377A (en) * | 2020-12-30 | 2021-05-07 | 中国科学院长春光学精密机械与物理研究所 | Real-time line time adjusting device and method for push-broom optical remote sensing camera |
| CN112764377B (en) * | 2020-12-30 | 2022-03-01 | 中国科学院长春光学精密机械与物理研究所 | Real-time line time adjusting device and method for push-broom optical remote sensing camera |
| CN115829842A (en) * | 2023-01-05 | 2023-03-21 | 武汉图科智能科技有限公司 | Device for realizing picture super-resolution reconstruction based on FPGA |
| CN115829842B (en) * | 2023-01-05 | 2023-04-25 | 武汉图科智能科技有限公司 | Device for realizing super-resolution reconstruction of picture based on FPGA |
| CN116886996A (en) * | 2023-09-06 | 2023-10-13 | 浙江富控创联技术有限公司 | Digital village multimedia display screen broadcasting system |
| CN116886996B (en) * | 2023-09-06 | 2023-12-01 | 浙江富控创联技术有限公司 | Digital village multimedia display screen broadcasting system |
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Application publication date: 20130814 |