CN103199864B - A kind of gradual approaching A/D converter - Google Patents
A kind of gradual approaching A/D converter Download PDFInfo
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- CN103199864B CN103199864B CN201310048708.XA CN201310048708A CN103199864B CN 103199864 B CN103199864 B CN 103199864B CN 201310048708 A CN201310048708 A CN 201310048708A CN 103199864 B CN103199864 B CN 103199864B
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Abstract
The invention discloses a kind of gradual approaching A/D converter, comprise a digital to analog converter, a comparator, an Approach by inchmeal logical circuit, a clock source; Approach by inchmeal logical circuit comprises a shift register, a data register.Unit in data register comprises first, second, third, fourth transistor, first and second current potential, a short circuit capacitance, a self-lock switch, first, second, third inverter.The present invention significantly reduces and exports comparative result to the time delay of digital to analog converter action from comparator, therefore can the switching rate of remarkable Lifting Modules number converter.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of analog to digital converter, particularly gradual approaching A/D converter.
Background technology
Fig. 1 shows a traditional gradual approaching A/D converter, and it comprises digital to analog converter 100, comparator 105, and Approach by inchmeal logical circuit 110.Wherein, Approach by inchmeal logical circuit 110 is made up of shift register 120 and data register 115.Shift register 120 is the arrays be made up of some shifting deposit unit 140-1 ~ 140-n, and each shifting deposit unit has a data input pin D, an output Q, an input end of clock Ck; Wherein, the data input pin of arbitrary shifting deposit unit 140-i is all coupled to the output of upper level 140-(i-1), the data input pin of first mobile deposit unit is coupled to the input 121 of described shift register, and the input end of clock of each shifting deposit unit is coupled to the input end of clock 136 of described shift register.The output of i-th shifting deposit unit 140-i is coupled to i-th output 122-i of shift register 120.Data register 115 comprises an array be made up of data registration unit 145-1 ~ 145-n, and data registration unit 145-i has data input pin D, output Q.The data input pin D of data registration unit 145-i is coupled to the output 107 of comparator 105, and its output Q is coupled to i-th input 231-i of digital to analog converter 100.Comparator 105 is used for the output 102 of comparator input signal 101 and digital to analog converter.The work clock 131 of comparator 105 is provided by clock source 130, work when the logic level generation saltus step of comparator operationally clock.Gate 135 is used for more whether completing of detection comparator, and in this realizing circuit of Fig. 1, gate 135 is actually or door.Time comparator resets, two exports 106,107 and is logical zero, the output 136 of 135 is logical zero, comparator 105 works when clock source exports the logic level generation saltus step of 131,106, one in 107 is 1 by logical zero saltus step, the output 136 of gate 135 is made to jump to logical one by logical zero, flip-flop shift 120.If before 136 saltus steps, the i-th-1 output 122-(i-1) of shift register is high, and i-th exports 122-i is low, and so after 136 saltus steps, i-th of shift register exports 122-i and also become height from low.Then, i-th data registration unit 145-i is triggered, and makes it export the value of the output 107 of 231-i seizure comparator.Because 231 is also simultaneously the input of digital to analog converter 100, when signal 231-i changes, the output 102 of digital to analog converter 100 changes accordingly, is input to comparator 105, waits for the saltus step next time of clock 131.This process goes on always, and the n position of shift register 120 exports saltus step successively for high, and the data registration unit 145 inside data register 115 is triggered successively, stores the comparative result of comparator, until all data registration unit are finished.Now the n position of data register 115 exports the output that 231-1 ~ 231-n is exactly this gradual approaching A/D converter.
In a kind of implementation shown in Fig. 1, shifting deposit unit 140 and data registration unit 145 are common d type flip flop.It has multiple way of realization, such as static d type flip flop or dynamic D trigger, other way of realization can also be had.
The conversion speed of this gradual approaching A/D converter is limited to several factors, and the logical time delay between the input outputting to digital to analog converter from comparator is exactly one of them.As shown in Figure 2, this logical time delay through gate 135, shifting deposit unit 140-i, data registration unit 145-I.Wherein, the time delay of gate 135 (or door) is greatly between 3 ~ 4 inverter time delays, and the time delay of shifting deposit unit and data registration unit is also large between 2 ~ 4 inverter time delays.Total logical time delay is greatly between 7 ~ 12 inverter time delays, and therefore conventional successive approach type analog to digital converter conversion speed is slow.
Summary of the invention
Technical problem to be solved by this invention is: overcome the problem that conventional successive approach type analog to digital converter conversion speed is slow, a kind of high speed self-locking register for analog to digital converter is provided, significantly can reduce and export the time delay of comparative result to digital to analog converter action from comparator, the switching rate of remarkable Lifting Modules number converter.
The technology of the present invention solution: a kind of high speed self-locking register for analog to digital converter, a kind of gradual approaching A/D converter, comprises a digital to analog converter, a comparator, an Approach by inchmeal logical circuit, a clock source;
Described Approach by inchmeal control logic circuit comprises a shift register, a data register;
Described shift register has an input, an input end of clock, some outputs;
Described shift register is an array be made up of some shifting deposit units, and each described shifting deposit unit all has a data input pin, an output, an input end of clock;
The data input pin of each described shifting deposit unit is coupled to the output of upper level, the data input pin of first described shifting deposit unit is coupled to the input of described shift register, the input end of clock of each described shifting deposit unit is coupled to the input end of clock of described shift register, one of output some outputs being coupled to described shift register of each described shifting deposit unit;
Described data register comprises an array be made up of some data registration unit, and each described data registration unit all has a data input pin, an output;
The data input pin of each described data registration unit is coupled to the output of described comparator, one of output some inputs of being coupled to described digital to analog converter of each described data registration unit;
The output of described comparator comparator input signal and digital to analog converter;
Described clock source controls described comparator;
Its feature is:
Each described data registration unit also has first and second input end of clock;
Each described data registration unit all comprises first, second, third, fourth transistor, first and second current potential, a short circuit capacitance, a self-lock switch, first, second, third inverter;
Described first, second, third, fourth transistor has grid end, source and drain terminal;
The source of described the first transistor is coupled to the first current potential of described data registration unit;
The drain terminal of first and second transistor described is coupled to the output of described data registration unit after the first inverter;
The source of described transistor seconds and the drain terminal of third transistor are coupled to the second current potential of described data registration unit by described short circuit capacitance;
The source of described third transistor is coupled to the drain terminal of described 4th transistor;
The source of described 4th transistor is coupled to the second current potential of described data registration unit;
The grid end of described the first transistor is coupled to the first input end of clock of described data registration unit;
The grid end of described transistor seconds is coupled to the data input pin of described data registration unit;
The grid end of described third transistor and the grid end of the 4th transistor can exchange, and are coupled to the output of described first input end of clock or the 3rd inverter respectively;
The input of described 3rd inverter is coupled to described second clock input;
The output of described data registration unit is coupled to one end of described self-lock switch by described second inverter, the other end of described self-lock switch is coupled to the source of described transistor seconds and the drain terminal of third transistor;
Described self-lock switch is controlled by the second clock input of described data registration unit;
First input end of clock of each described data registration unit is coupled to the output of one of described shifting deposit unit, and the second clock input of each described data registration unit is coupled to the output of the next stage of one of described shifting deposit unit.
Described the first transistor is p-type MOS transistor, second, third, the 4th transistor is N-shaped MOS transistor.
Described the first transistor is N-shaped MOS transistor, second, third, the 4th transistor is p-type MOS transistor.
Described self-lock switch is cmos transmission gate.
Described short circuit capacitance is realized by mos capacitance.
Described shifting deposit unit is realized by d type flip flop.
The present invention and prior art have following beneficial effect: the present invention is directed to traditional gradually-appoximant analog-digital converter, significantly shorten from the logical time delay between the input outputting to digital to analog converter of comparator, the conversion speed of gradual approaching A/D converter can be significantly improved.
Accompanying drawing explanation
Fig. 1 is traditional gradual approaching A/D converter;
Fig. 2 is the delay path of conventional successive approach type analog to digital converter between comparator to DAC;
Fig. 3 gradual approaching A/D converter of the present invention;
Fig. 4 is the path that sparks in the input signal rising edge arriving moment of the data input pin of data registration unit in the present invention;
Fig. 5 is the auto-lock process schematic diagram of data registration unit in the present invention;
Fig. 6 is the signal path outputting to digital to analog converter control end from comparator.
Embodiment
As shown in figures 1 to 6, the scheme that circuit of the present invention is relatively traditional has following several change: first is the dynamic circuit 235 be transformed into by the d type flip flop in traditional data register inside Fig. 3 shown in dashed circle.Different from traditional d type flip flop only having a clock to input, new dynamic circuit (data registration unit hereinafter referred to as new) comprises two input end of clock: the first input end of clock Ck
iwith second clock input Ck
i+1, wherein, Ck
ibe coupled to the output 142-i of i-th shifting deposit unit, Ck
i+1be coupled to the output 142-i+1 of the i-th+1 shifting deposit unit.
New data registration unit 235 comprises the first transistor 300, transistor seconds 330, third transistor 320, the 4th transistor 325; Short circuit capacitance 315, self-lock switch 335, the first inverter 305, second inverter the 310, three inverter.The source of the first transistor 300 is coupled to power supply (the first current potential), and the first transistor 300 is coupled to the input of the first inverter 305 with the drain terminal of transistor seconds 330, and the output 302 of data registration unit is coupled in the output of the first inverter; The source of transistor seconds 330 and the drain terminal of third transistor 320 are coupling to ground (the second current potential) by short circuit capacitance 315; The source of third transistor 320 is coupled to the drain terminal of the 4th transistor 325; The source of the 4th transistor 325 is coupling to ground (the second current potential).The grid end of the first transistor 300 is coupled to the first input end of clock Ck of data registration unit 235
i.The grid end of transistor seconds is coupled to the data input pin D of data registration unit 235.The grid end of third transistor and the grid end of the 4th transistor can exchange, and are coupled to data registration unit 235 first input end of clock Ck respectively
ior second output of inverter.The input of the second inverter is second clock Cki+1.
The drain terminal of the first transistor and transistor seconds, after the time delay module be made up of first and second inverter, is coupled to one end of self-lock switch 335, and the other end of 335 is coupled to the source of transistor seconds and the drain terminal of third transistor; Self-lock switch is controlled by the second clock input of data registration unit; Ck
ibe coupled to the output 142-i of i-th shifting deposit unit, Ck
i+1be coupled to the output 142-(i+1) of the i-th+1 shifting deposit unit.
It is the control clock 131 that the clock input of shift register changes comparator into that the second of the scheme that circuit of the present invention is relatively traditional is changed.Like this, before comparator 105 Output rusults, shift register 120 is just ready.New data registration unit 235 is the ability gating when Cki=1, Cki+1=0 only, and that is the first transistor 300 disconnects, the 3rd, the 4th transistor turns, the state that self-lock switch 335 disconnects.This data registration unit 235 is in fact the dynamic circuit of precharge logical, as long as comparator 105 exports comparative result, node 301 just can export its anti-phase result.If but there is no short circuit capacitance 315, that discharging current will through three transistor, and the time delay caused is approximately 6 inverter time delays, and this is compared with traditional sequential logical circuit be made up of d type flip flop, and the advantage in speed is also not obvious.After adding short circuit capacitance 315, short circuit capacitance is equivalent to ac short circuit, and spark electric current will flow directly to ground by it, the logical time delay of this one-level narrowed down to an inverter time delay, will have compared traditional sequential logical circuit, have significant speed advantage.
But if the self-locking circuit be not made up of inverter 305,310 and self-lock switch 335, this data registration unit 235 can not keep this operation result always.Although next time before comparator Output rusults, Cki and Cki+1 is equal to 1, a meeting in three or four transistor disconnects, avoid the continuous discharge electric current on ground, but due to the existence of short circuit capacitance, electric charge on node 301 can carry out with the electric charge in short circuit capacitance redistributing (if transistor seconds conducting), causes the wrong Output rusults of this data registration unit 235.Therefore, the self-locking circuit of the present invention's design, while the 3rd or the 4th transistor cutoff, closed self-lock switch 335, forces to make the logic level of node 303 equal the logic level of node 301, like this, after the comparative result of next comparator arrives, no matter transistor seconds whether conducting, all can not the logic level of concept transfer 301, also would not change the Output rusults of this data registration unit 235.
Another circuit skill hidden is, when whole Approach by inchmeal logical circuit resets, Ck1-Ckn all becomes logical zero, comparator 105 also resets, the first transistor conducting, and transistor seconds ends, 3rd or the 4th transistor cutoff, node 301 is charged to logic high, and node 303 will retain logic level in the past instead of the logic low that the present invention wants.Only be strobed at data registration unit 235-i, the moment of Cki=1, Cki+1=0, the equal conducting of the three or four transistor, node 303 just can be discharged.So the size of short circuit capacitance has to pass through well-designed, to ensure that node 303 is completely discharged before comparator exports comparative result.
Because nmos pass transistor compares PMOS transistor, corresponding speed is faster, so the first transistor of the present invention is p-type MOS transistor, second, third, the 4th transistor is N-shaped MOS transistor.
In fact, the first transistor is designed to N-shaped MOS transistor, second, third, the 4th transistor is that p-type MOS transistor also can realize similar functions, but performance is slightly poor.In order to make this change normally work, needing the polarity of corresponding adjustment comparator, making it in the output of reset mode, transistor seconds can be made normally to end.
Shifting deposit unit in the present embodiment is realized by d type flip flop.
Non-elaborated part of the present invention belongs to techniques well known.
Specific embodiments of the invention are only above.According to technological thought provided by the invention, those skilled in the art can think and change, all should fall within the scope of protection of the present invention.
Claims (6)
1. a gradual approaching A/D converter, comprises a digital to analog converter, a comparator, an Approach by inchmeal logical circuit, a clock source;
Described Approach by inchmeal logical circuit comprises a shift register, a data register;
Described shift register has an input, an input end of clock, some outputs;
Described shift register is an array be made up of some shifting deposit units, and each described shifting deposit unit all has a data input pin, an output, an input end of clock;
The data input pin of each described shifting deposit unit is coupled to the output of upper level, the data input pin of first described shifting deposit unit is coupled to the input of described shift register, the input end of clock of each described shifting deposit unit is coupled to the input end of clock of described shift register, one of output some outputs being coupled to described shift register of each described shifting deposit unit;
Described data register comprises an array be made up of some data registration unit, and each described data registration unit all has a data input pin, an output;
The data input pin of each described data registration unit is coupled to the output of described comparator, one of output some inputs of being coupled to described digital to analog converter of each described data registration unit;
The output of described comparator comparator input signal and digital to analog converter;
Described clock source controls described comparator;
It is characterized in that:
Each described data registration unit also has first and second input end of clock;
Each described data registration unit all comprises first, second, third, fourth transistor, first and second current potential, a short circuit capacitance, a self-lock switch, first, second, third inverter;
Described first, second, third, fourth transistor has grid end, source and drain terminal;
The source of described the first transistor is coupled to the first current potential of described data registration unit;
The drain terminal of first and second transistor described is coupled to the output of described data registration unit after the first inverter;
The source of described transistor seconds and the drain terminal of third transistor are coupled to the second current potential of described data registration unit by described short circuit capacitance;
The source of described third transistor is coupled to the drain terminal of described 4th transistor;
The source of described 4th transistor is coupled to the second current potential of described data registration unit;
The grid end of described the first transistor is coupled to the first input end of clock of described data registration unit;
The grid end of described transistor seconds is coupled to the data input pin of described data registration unit;
The grid end of described third transistor and the grid end of the 4th transistor can exchange, and are coupled to the output of described first input end of clock or the 3rd inverter respectively;
The input of described 3rd inverter is coupled to described second clock input;
The output of described data registration unit is coupled to one end of described self-lock switch by described second inverter, the other end of described self-lock switch is coupled to the source of described transistor seconds and the drain terminal of third transistor;
Described self-lock switch is controlled by the second clock input of described data registration unit;
First input end of clock of each described data registration unit is coupled to the output of one of described shifting deposit unit, and the second clock input of each described data registration unit is coupled to the output of the next stage of one of described shifting deposit unit.
2. gradual approaching A/D converter according to claim 1, is characterized in that: described the first transistor is p-type MOS transistor, second, third, the 4th transistor is N-shaped MOS transistor.
3. gradual approaching A/D converter according to claim 1, is characterized in that: described the first transistor is N-shaped MOS transistor, second, third, the 4th transistor is p-type MOS transistor.
4. gradual approaching A/D converter according to claim 1, is characterized in that: described self-lock switch is cmos transmission gate.
5. gradual approaching A/D converter according to claim 1, is characterized in that: described short circuit capacitance is realized by mos capacitance.
6. gradual approaching A/D converter according to claim 1, is characterized in that: described shifting deposit unit is d type flip flop.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103929178B (en) * | 2014-04-29 | 2017-02-08 | 中国电子科技集团公司第二十四研究所 | Successive approximation analog-digital converter and conversion method thereof |
| CN104967450B (en) * | 2015-07-28 | 2018-01-16 | 西安电子科技大学 | Control logic circuit with low fan-in |
| CN105070318B (en) * | 2015-08-06 | 2019-01-11 | 中国电子科技集团公司第二十四研究所 | A kind of high speed shift register applied to gradual approaching A/D converter |
| CN109687872B (en) * | 2019-02-26 | 2020-09-15 | 中国电子科技集团公司第二十四研究所 | High-speed digital logic circuit for SAR _ ADC and sampling regulation method |
| CN110768674A (en) * | 2019-10-29 | 2020-02-07 | 湖南国科微电子股份有限公司 | Analog-to-digital conversion device, analog-to-digital conversion equipment and analog-to-digital conversion method |
| CN111030697B (en) * | 2019-12-31 | 2023-04-25 | 江苏科大亨芯半导体技术有限公司 | High-speed low-power-consumption successive approximation type analog-to-digital converter |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102118168A (en) * | 2011-04-08 | 2011-07-06 | 中国科学院半导体研究所 | Sequential-approximation analog-digital converter based on multi-bit serial conversion |
| CN102158231A (en) * | 2011-03-15 | 2011-08-17 | 上海宏力半导体制造有限公司 | Successive approximation type analog-to-digital converter |
| CN102355266A (en) * | 2011-07-28 | 2012-02-15 | 上海宏力半导体制造有限公司 | Successive approximation register analog-digital converter |
| CN102427368A (en) * | 2011-11-30 | 2012-04-25 | 香港应用科技研究院有限公司 | High-speed successive approximation register analog-digital converter |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4690105B2 (en) * | 2005-04-26 | 2011-06-01 | パナソニック株式会社 | Successive approximation type A / D converter |
| JP5554675B2 (en) * | 2010-09-29 | 2014-07-23 | 富士通株式会社 | Successive comparison A / D converter |
-
2013
- 2013-02-07 CN CN201310048708.XA patent/CN103199864B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158231A (en) * | 2011-03-15 | 2011-08-17 | 上海宏力半导体制造有限公司 | Successive approximation type analog-to-digital converter |
| CN102118168A (en) * | 2011-04-08 | 2011-07-06 | 中国科学院半导体研究所 | Sequential-approximation analog-digital converter based on multi-bit serial conversion |
| CN102355266A (en) * | 2011-07-28 | 2012-02-15 | 上海宏力半导体制造有限公司 | Successive approximation register analog-digital converter |
| CN102427368A (en) * | 2011-11-30 | 2012-04-25 | 香港应用科技研究院有限公司 | High-speed successive approximation register analog-digital converter |
Non-Patent Citations (1)
| Title |
|---|
| 一个10位逐次逼近式ADC电路;江利等;《上海电气技术》;20101231;第3卷(第4期);第39-43页 * |
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