CN103187489A - Semiconductor packaging method and semiconductor packaging structure - Google Patents
Semiconductor packaging method and semiconductor packaging structure Download PDFInfo
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- CN103187489A CN103187489A CN2011104505529A CN201110450552A CN103187489A CN 103187489 A CN103187489 A CN 103187489A CN 2011104505529 A CN2011104505529 A CN 2011104505529A CN 201110450552 A CN201110450552 A CN 201110450552A CN 103187489 A CN103187489 A CN 103187489A
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- layer
- hyaline layer
- led chip
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Abstract
The invention provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the following steps: firstly, providing a base plate and forming a groove and at least two penetrating holes in the base plate; secondly, arranging a circuit structure in the groove, wherein the circuit structure comprises a first electrode and a second electrode, and forming a first external electrode and a second external electrode on the bottom surface of the base plate through the penetrating holes; thirdly, arranging a first transparent layer in the groove, and forming a concaved portion on the first transparent layer through a removable barrier layer, wherein the concaved portion is positioned between the first electrode and the second electrode; fourthly, arranging a light-emitting diode (LED) chip in the concaved portion and enabling the LED chip to be electrically connected with the circuit structure; lastly, forming a packaging layer, wherein the packaging layer comprises a fluorescent layer and a second transparent layer, the fluorescent layer covers the LED chip, and the second transparent layer covers the fluorescent layer. The invention further provides a semiconductor packaging structure.
Description
Technical field
The present invention relates to a kind of semiconductor packing process and encapsulating structure thereof, relate in particular to semiconductor packing process and encapsulating structure thereof that a kind of mode with conformal coating (Conformal coating) forms fluorescence coating.
Background technology
The LED industry is one of industry that attracted most attention in recent years, development so far, that the LED product has had is energy-conservation, power saving, high efficiency, the reaction time is fast, the life cycle time is long and not mercurous, have advantage such as environmental benefit.Yet because the encapsulation procedure of LED structure can directly have influence on its serviceability and life-span, for example aspect optics control, can improve light extraction efficiency and optimize beam distribution by encapsulation procedure.At present on led chip, in a glue mode sealing that blending has fluorescent material is set, though described colloid and described fluorescent material are to have the effect of the LED of raising luminous efficiency, but because shape and the thickness of described the described sealing of the difficult control of glue mode, will cause the color of LED bright dipping inconsistent, inclined to one side blue light or inclined to one side gold-tinted occur.The unmanageable problem of the shape of relevant described sealing and thickness can solve by the mode with model, but can increase processing procedure and cost like this.In addition, described fluorescent material sealing is directly coated on the led chip, can make light extraction efficiency lower owing to have the problem of light scattering.So how from semi-conductive encapsulation procedure, to make the color of bright dipping more even, need continue to study improvement.
Summary of the invention
In view of this, be necessary to provide a kind of semiconductor packing process and encapsulating structure thereof of conformal coating.
A kind of semiconductor packing process, it comprises the steps;
A substrate is provided, at described substrate a groove and at least two perforation is set,
A circuit structure is set in described groove, described circuit structure comprises first electrode and second electrode, and forms first outer electrode and second outer electrode by described perforation in described substrate bottom surface,
Form first hyaline layer in described groove, form a recess by a removable barrier layer at described first hyaline layer, and make described recess between described first and second electrode,
A led chip is set at described recess, makes described led chip and described circuit structure reach electric connection, and
Form an encapsulated layer, described encapsulated layer comprises a fluorescence coating and second hyaline layer, and described fluorescence coating covers described led chip, and described second hyaline layer covers described fluorescence coating.
In the above-mentioned semiconductor packing process, because the described recess of described first hyaline layer is formed between first and second interior electrode of described substrate recess, described led chip can be reached electric connection at described recess and described circuit structure, and the described fluorescence coating that covers described led chip arranges in described recess, make described fluorescence coating have the structure of conformal coating, it is more even to make described semiconductor encapsulated element go out light color by the described fluorescence layer structure of conformal coating.
Description of drawings
Fig. 1 is the flow chart of steps of semiconductor packing process of the present invention.
Fig. 2 is the cutaway view that corresponding diagram 1 provides a substrate step.
Fig. 3 is the cutaway view that corresponding diagram 1 arranges a circuit structure step.
Fig. 4 is the cutaway view that corresponding diagram 1 forms first a hyaline layer step.
Fig. 5 is the cutaway view that corresponding diagram 1 arranges a led chip step.
Fig. 6 is the cutaway view that corresponding diagram 1 forms the semiconductor package of an encapsulated layer step.
The main element symbol description
| Semiconductor package | 10 |
| |
12 |
| |
120a |
| The | 120b |
| Groove | |
| 122 | |
| |
124 |
| |
14 |
| |
142 |
| |
144 |
| First |
146 |
| Second |
148 |
| First |
15 |
| The |
152 |
| Recess | 154 |
| Led |
16 |
| Encapsulated |
18 |
| |
182 |
| Second |
184 |
Following embodiment will further specify the present invention in conjunction with above-mentioned accompanying drawing.
Embodiment
Below in conjunction with accompanying drawing the present invention being done one specifically introduces.
See also Fig. 1, be depicted as the flow chart of steps of semiconductor packing process of the present invention, it comprises the steps;
S11 provides a substrate, at described substrate a groove and at least two perforation is set,
S12 arranges a circuit structure in described groove, and described circuit structure comprises first electrode and second electrode, and forms first outer electrode and second outer electrode by described perforation in described substrate bottom surface,
S13 forms first hyaline layer in described groove, and form a recess by a removable barrier layer at described first hyaline layer, and make described recess between described first and second electrode,
S14 arranges a led chip at described recess, makes described led chip and described circuit structure reach electric connection, and
S15 forms an encapsulated layer, and described encapsulated layer comprises a fluorescence coating and second hyaline layer, and described fluorescence coating covers described led chip, and described second hyaline layer covers described fluorescence coating.
Described step S11 provides a substrate 12, at described substrate 12 groove 122 and at least two perforation 124 are set, described substrate 12 comprises an end face 120a and a bottom surface 120b, described groove 122 is arranged on the end face 120a of described substrate 12, and described perforation 124 runs through described substrate 12 to described bottom surface 120b (as shown in Figure 2) in described groove 122.Described substrate 12 materials can be pottery (Ceramic) material or silicon (Si) material, and wherein silicon (Si) material substrate 12 is convenient to the follow-up manufacturing of carrying out micro electronmechanical processing procedure, helps the raising of precision.
Described step S12 arranges a circuit structure 14 in described groove 122, described circuit structure 14 comprises first electrode 142 and second electrode 144, and form first outer electrode 146 and second outer electrode 148 by described perforation 124 at described substrate bottom surface 120b, described first and second electrode 142,144 is oppositely arranged (as shown in Figure 3) in the bottom of described groove 122, and extend to the bottom surface 120b of described substrate 12 respectively by described perforation 124, form described first and second outer electrode 146,148.
Described step S13 forms first hyaline layer 15 in described groove 122, form a recess 154 by a removable barrier layer 152 at described first hyaline layer 15, and make described recess 154 be positioned at described first, between two electrodes 142,144, described barrier layer 152 is as described in a mould or a photoresist layer (shown in the dotted line position of Fig. 4) are arranged on first, between two electrodes 142,144, described first hyaline layer 15 is centered around around the described barrier layer 152 and is positioned at the bottom of described groove 122, the height of described first hyaline layer 15 less than or equal described barrier layer 152 height.After described first hyaline layer 15 solidifies, can carry out the running that removes on described barrier layer 152, will be between described first and second electrode at 152 places, described barrier layer after described barrier layer 152 removes 142,144 form described recess 154.If described barrier layer 152 moulds can directly remove, if described barrier layer 152 photoresist layers then can use etched mode to remove.In addition, form on the mode of a recess 154 at described first hyaline layer 15, except above-mentioned removable described barrier layer 152 modes, can directly utilize the mode of pressurising to form described recess 154.That is, directly form described first hyaline layer 15 earlier on the described circuit structure 14 of described groove 122 bottoms, 142,144 modes with pressurising form described recess 154 between described first and second electrode of described circuit structure 14 then.
Described step S14 arranges a led chip 16 at described recess 154, make described led chip 16 reach electric connection with described circuit structure 14, described recess 154 is owing to be formed between described first and second electrode of described circuit structure 14 142,144, therefore, described led chip 16 can directly be arranged on described first and second electrode 142,144 by described recess 154, see also shown in Figure 5, thereby described led chip 16 is reached electric connection with described circuit structure 14.Described led chip 16 and described first and second electrode 142,144 electric connection can routing (Wire Bonding) be covered crystalline substance (Flip Chip) or eutectic (Eutectic) mode is reached.
At last, described step S15 forms an encapsulated layer 18, described encapsulated layer 18 comprises a fluorescence coating 182 and second hyaline layer 184, described fluorescence coating 182 covers described led chip 16, described second hyaline layer 184 covers described fluorescence coating 182, described fluorescence coating 182 covers described led chip 16 at described recess 154, and makes cover height identical with described first hyaline layer 15.Described fluorescence coating 182 in described recess 154 to the covering fully of described led chip 16 outsides, thereby form the mode of conformal coating (Conformal coating), it is more even to make semiconductor element go out light color.Described second hyaline layer 184 covers described fluorescence coating 182 and comprises described led chip 16 and described first hyaline layer 15 (as shown in Figure 6).A fluorescence coating (not indicating among the figure) can be set in addition again, in order to promote the light output of semiconductor element in described second hyaline layer 184.The refractive index of described second hyaline layer 184 is less than the refractive index of described fluorescence coating 18 and described first hyaline layer 15.
The semiconductor package 10 that above-mentioned semiconductor packing process is made comprises a substrate 12, a circuit structure 14, first hyaline layer 15, a led chip 16 and an encapsulated layer 18.Have a groove 122 and at least two perforation 124 on the described substrate 12, described circuit structure 14 is arranged in the described groove 122, described circuit structure 14 comprises first electrode 142 and second electrode 144, and described first and second electrode 142,144 forms first outer electrode 146 and second outer electrode 148 by described perforation 124 at described substrate bottom surface 120b.Described first hyaline layer 15 is arranged on the bottom of described groove 122, and between described first and second electrode 142,144, has a recess 154, described led chip 16 is set in the described recess 154, described led chip 16 electrically connects with described first and second electrode 142,144, described encapsulated layer 18 comprises a fluorescence coating 182 and second hyaline layer 184, described fluorescence coating 182 covers described led chip 16, and described second hyaline layer 184 covers described fluorescence coating 182.Make described fluorescence coating 182 cover the outside of described led chip 16 by described recess 154, it is more even to make described semiconductor package 10 go out light color.
To sum up, semiconductor packing process of the present invention, described circuit structure 14 is set in the described groove 122 of described substrate 12, form described first hyaline layer 15 and have described recess 154 settings at described circuit structure 14, can make described led chip 16 electrically connect described circuit structure 14 by described recess 154, make described fluorescence coating 182 be covered in the outside of described led chip 16 simultaneously, have that processing procedure is simple, cost is low, can effectively promote semiconductor package goes out the uniform usefulness of light color.
In addition, those skilled in the art also can do other variation in spirit of the present invention, and certainly, the variation that these are done according to spirit of the present invention all should be included within the present invention's scope required for protection.
Claims (16)
1. semiconductor packing process, it comprises the steps:
A substrate is provided, at described substrate a groove and at least two perforation is set,
A circuit structure is set in described groove, described circuit structure comprises first electrode and second electrode, and forms first outer electrode and second outer electrode by described perforation in described substrate bottom surface,
Form first hyaline layer in described groove, form a recess by a removable barrier layer at described hyaline layer, and make described recess between described first and second electrode,
A led chip is set at described recess, makes described led chip and described circuit structure reach electric connection, and
Form an encapsulated layer, described encapsulated layer comprises a fluorescence coating and second hyaline layer, and described fluorescence coating covers described led chip, and described second hyaline layer covers described fluorescence coating.
2. semiconductor packing process as claimed in claim 1, it is characterized in that: described providing in the substrate step, described substrate comprises an end face and a bottom surface, and described groove is arranged on the end face of described substrate, and described perforation runs through described substrate to described bottom surface in described groove.
3. semiconductor packing process as claimed in claim 2 is characterized in that: described baseplate material can be pottery (Ceramic) material or silicon (Si) material.
4. semiconductor packing process as claimed in claim 1, it is characterized in that: in the step, described barrier layer is a mould or a photoresist layer to first hyaline layer of described formation in described groove.
5. semiconductor packing process as claimed in claim 1 is characterized in that: first hyaline layer of described formation in described groove in the step, the height of described first hyaline layer less than or equal described barrier layer height.
6. semiconductor packing process as claimed in claim 1, it is characterized in that: in the step, described first hyaline layer can directly utilize the mode of pressurising to form described recess to first hyaline layer of described formation in described groove.
7. semiconductor packing process as claimed in claim 1, it is characterized in that: describedly a led chip is set in described recess step, the electric connection of described led chip with routing (Wire Bonding), cover crystalline substance (Flip Chip) or the mode of eutectic (Eutectic) is reached.
8. semiconductor packing process as claimed in claim 1, it is characterized in that: in encapsulated layer step of described formation, the cover height that described fluorescence coating covers described led chip is identical with described first hyaline layer.
9. semiconductor packing process as claimed in claim 1 is characterized in that: in encapsulated layer step of described formation, in described second hyaline layer fluorescence coating can be set in addition again.
10. semiconductor packing process as claimed in claim 1, it is characterized in that: in encapsulated layer step of described formation, the refractive index of described second hyaline layer is less than the refractive index of described fluorescence coating and described first hyaline layer.
11. semiconductor package, comprise a substrate, a circuit structure, first hyaline layer, a led chip and an encapsulated layer, have a groove and at least two perforation on the described substrate, described circuit structure is arranged in the described groove, described circuit structure comprises first electrode and second electrode, described first hyaline layer is arranged on the bottom of described groove, and described first, has a recess between two electrodes, described led chip is set in the described recess, described led chip and described first, two electrodes electrically connect, described encapsulated layer comprises a fluorescence coating and second hyaline layer, described fluorescence coating covers described led chip, and described second hyaline layer covers described fluorescence coating.
12. semiconductor package as claimed in claim 11 is characterized in that: described substrate comprises an end face and a bottom surface, and described groove is arranged on the end face of described substrate, and described perforation runs through described substrate to described bottom surface in described groove.
13. semiconductor package as claimed in claim 11 is characterized in that: described baseplate material can be pottery (Ceramic) material or silicon (Si) material.
14. semiconductor package as claimed in claim 11 is characterized in that: described first and second electrode forms first outer electrode and second outer electrode by described perforation in described substrate bottom surface.
15. semiconductor package as claimed in claim 11 is characterized in that: the cover height that described fluorescence coating covers described led chip is identical with described first hyaline layer.
16. semiconductor package as claimed in claim 11 is characterized in that: described second hyaline layer covers described fluorescence coating and comprises described led chip and described first hyaline layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104505529A CN103187489A (en) | 2011-12-29 | 2011-12-29 | Semiconductor packaging method and semiconductor packaging structure |
| TW101103362A TWI467809B (en) | 2011-12-29 | 2012-02-02 | Method for manufacturing semiconductor package and structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104505529A CN103187489A (en) | 2011-12-29 | 2011-12-29 | Semiconductor packaging method and semiconductor packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103187489A true CN103187489A (en) | 2013-07-03 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011104505529A Pending CN103187489A (en) | 2011-12-29 | 2011-12-29 | Semiconductor packaging method and semiconductor packaging structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103187489A (en) |
| TW (1) | TWI467809B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1455960A (en) * | 2001-01-24 | 2003-11-12 | 日亚化学工业株式会社 | Light emitting diode, optical semiconductor element and epoxy resin composition suitable for optical semiconductor element and production methods therefor |
| US20080224162A1 (en) * | 2007-03-14 | 2008-09-18 | Samsung Electro-Mechanics Co., Ltd. | Light emitting diode package |
| TW201145609A (en) * | 2010-06-02 | 2011-12-16 | Advanced Optoelectronic Tech | Light-emitting diode package |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW554547B (en) * | 2001-01-24 | 2003-09-21 | Nichia Corp | Light emitting diode, optical semiconductor device, epoxy resin composition suited for optical semiconductor device, and method for manufacturing the same |
-
2011
- 2011-12-29 CN CN2011104505529A patent/CN103187489A/en active Pending
-
2012
- 2012-02-02 TW TW101103362A patent/TWI467809B/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1455960A (en) * | 2001-01-24 | 2003-11-12 | 日亚化学工业株式会社 | Light emitting diode, optical semiconductor element and epoxy resin composition suitable for optical semiconductor element and production methods therefor |
| US20080224162A1 (en) * | 2007-03-14 | 2008-09-18 | Samsung Electro-Mechanics Co., Ltd. | Light emitting diode package |
| TW201145609A (en) * | 2010-06-02 | 2011-12-16 | Advanced Optoelectronic Tech | Light-emitting diode package |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI467809B (en) | 2015-01-01 |
| TW201327930A (en) | 2013-07-01 |
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Application publication date: 20130703 |