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CN103165555A - 层叠封装的封装结构及其制法 - Google Patents

层叠封装的封装结构及其制法 Download PDF

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CN103165555A
CN103165555A CN2012102186275A CN201210218627A CN103165555A CN 103165555 A CN103165555 A CN 103165555A CN 2012102186275 A CN2012102186275 A CN 2012102186275A CN 201210218627 A CN201210218627 A CN 201210218627A CN 103165555 A CN103165555 A CN 103165555A
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encapsulating structure
electric contact
dielectric layer
setting area
insulating protective
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CN103165555B (zh
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詹英志
林俊廷
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Unimicron Technology Corp
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Abstract

一种层叠封装的封装结构及其制法，该层叠封装的封装结构包括基板、绝缘保护层、置晶连接端、电性连接端、介电层、铜柱、半导体芯片、焊球与封装结构，该基板上分别具有多个置晶垫与多个电性接触垫，该绝缘保护层形成于该基板、置晶垫与电性接触垫上，该置晶连接端与电性连接端分别对应电性连接各该置晶垫与电性接触垫，该介电层形成于该绝缘保护层、置晶连接端与电性连接端上，并具有对应该置晶区与各该电性连接端的介电层开孔，该半导体芯片设于该介电层开孔中的置晶连接端上，该铜柱形成于各该介电层开孔中，该焊球形成于靠该置晶区较近的一侧的各该铜柱上，该封装结构叠置并电性连接于该焊球上。本发明能有效缩减封装结构的体积。

Description

层叠封装的封装结构及其制法
技术领域
本发明有关一种层叠封装的封装结构及其制法，尤指一种具有铜柱的层叠封装的封装结构及其制法。
背景技术
随着电子产品的微型化发展趋势，封装基板表面可供设置半导体芯片或封装结构的面积越来越小，因此遂发展出一种半导体封装结构的立体堆栈技术，其通过于一半导体封装结构上形成有焊球，并将另一半导体封装结构叠置于该焊球上，而成为一层叠封装（Package-on-Package，简称PoP）的封装结构，以符合小型表面接合面积与高密度组件设置的要求。
请参阅图1A至图1E，其为现有层叠封装的封装结构及其制法的剖视图。
如图1A所示，提供一封装基板10，其一表面101上具有多个置晶垫11与围绕该等置晶垫11的多个电性接触垫12，于该表面101、置晶垫11与电性接触垫12上形成有绝缘保护层13，该绝缘保护层13具有多个对应外露各该置晶垫11与各该电性接触垫12的绝缘保护层开孔130，且于各该置晶垫11上设有第一焊球14。
如图1B所示，于该等第一焊球14上接置半导体芯片15。
如图1C所示，形成包覆该半导体芯片15的封装材料16。
如图1D所示，于各该电性接触垫12上形成第二焊球17。
如图1E所示，于该第二焊球17上接置另一封装结构18。
然而，上述现有的PoP封装结构需要于电性接触垫上形成较大的焊球，以使后来上层堆栈的封装结构不致接触下层的半导体芯片，而较大的焊球将占用过多的封装基板面积，且增加整体封装结构的厚度，进而对于电子产品的微型化相当不利。
因此，如何提出一种层叠封装的封装结构及其制法，以避免现有技术需要较大的焊球，导致最终封装结构的体积过大等问题，实已成为目前亟欲解决的课题。
发明内容
鉴于上述现有技术的封装结构的体积较大的缺点，本发明的主要目的在于揭露一种层叠封装的封装结构及其制法，以有效缩减封装结构的体积。
本发明的层叠封装的封装结构包括：第一基板，其具有相对的第一表面与第二表面，该第一表面定义有置晶区与围绕该置晶区的非置晶区，该置晶区与非置晶区的第一表面上分别具有多个置晶垫与多个第一电性接触垫；第一绝缘保护层，其形成于该第一表面、置晶垫与第一电性接触垫上，并具有多个对应外露各该置晶垫与各该第一电性接触垫的第一绝缘保护层开孔；多个置晶连接端与电性连接端，其形成于该第一绝缘保护层上，并分别对应电性连接各该置晶垫与第一电性接触垫；介电层，其形成于该第一绝缘保护层、置晶连接端与电性连接端上，并具有分别对应该置晶区与各该电性连接端的第一介电层开孔与第二介电层开孔；第一铜柱，其形成于该各该第二介电层开孔中；第一半导体芯片，其设于该第一介电层开孔中，并电性连接于该置晶连接端上；第一焊球，其形成于靠该置晶区较近的一侧的各该第一铜柱上；以及第一封装结构，其叠置并电性连接于该第一焊球上。
本发明还揭露一种层叠封装的封装结构的制法，其包括：提供一具有相对的第一表面与第二表面的第一基板，该第一表面定义有置晶区与围绕该置晶区的非置晶区，该置晶区与非置晶区的第一表面上分别具有多个置晶垫与多个第一电性接触垫，于该第一表面、置晶垫与第一电性接触垫上形成有第一绝缘保护层，该第一绝缘保护层具有多个对应外露各该置晶垫与各该第一电性接触垫的第一绝缘保护层开孔；于该第一绝缘保护层上形成多个分别对应电性连接各该置晶垫与第一电性接触垫的置晶连接端与电性连接端；于该第一绝缘保护层、置晶连接端与电性连接端上形成介电层，且该介电层具有分别对应该置晶区与各该电性连接端的第一介电层开孔与第二介电层开孔；于各该第二介电层开孔中印刷形成第一铜柱，并于该第一介电层开孔中的置晶连接端上电性连接第一半导体芯片；于靠该置晶区较近的一侧的各该第一铜柱上形成第一焊球；以及于该第一焊球上叠置并电性连接第一封装结构。
由上可知，因为本发明的封装结构通过于多个不同的电性连接端上形成有不同高度的铜柱，并利用该等铜柱定义出封装结构容置区，所以能在有限的空间中接置半导体芯片与另一封装结构，且能在最高的铜柱上再堆栈第二个封装结构，即本发明可使用较小的焊球来连接封装结构，故能有效缩小最终结构的平面尺寸与厚度；此外，本发明以模板印刷方式来形成铜柱，所以可提供高良率、细间距与高度均匀性佳的电性连接方式。
附图说明
图1A至图1E为现有层叠封装的封装结构及其制法的剖视图。
图2A至图2J为本发明的层叠封装的封装结构及其制法的剖视图。
主要组件符号说明
10                        封装基板
101                       表面
11,211                    置晶垫
12                        电性接触垫
13                        绝缘保护层
130                       绝缘保护层开孔
14,30                     第一焊球
15                        半导体芯片
16                        封装材料
17,40                     第二焊球
18                        封装结构
20                        第一基板
20a                       第一表面
20b                       第二表面
201                       置晶区
202                         非置晶区
203                         导电通孔
212                         第一电性接触垫
213                         第二电性接触垫
22a                         第一绝缘保护层
22b                         第二绝缘保护层
220a                        第一绝缘保护层开孔
220b                        第二绝缘保护层开孔
231                         置晶连接端
232                         电性连接端
24                          介电层
241                         第一介电层开孔
242                         第二介电层开孔
251                         第一铜柱
252                         第二铜柱
261,262                     模板
27                          第一半导体芯片
28                          底充材料
2                           焊料凸块
3                           第一封装结构
31                          第二基板
32                          第二半导体芯片
4                           第二封装结构
41                          第三基板
42                          第三半导体芯片。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“围绕”及“侧”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2J，其为本发明的层叠封装的封装结构及其制法的剖视图。
如图2A所示，提供一具有相对的第一表面20a与第二表面20b的第一基板20，该第一表面20a定义有置晶区201与围绕该置晶区201的非置晶区202，该置晶区201与非置晶区202的第一表面20a上分别具有多个置晶垫211与多个第一电性接触垫212，于该第一表面20a、置晶垫211与第一电性接触垫212上形成有第一绝缘保护层22a，该第一绝缘保护层22a具有多个对应外露各该置晶垫211与各该第一电性接触垫212的第一绝缘保护层开孔220a；此外，该第二表面20b上还具有多个第二电性接触垫213，于该第二表面20b与第二电性接触垫213上并形成有第二绝缘保护层22b，且该第二绝缘保护层22b具有多个对应外露各该第二电性接触垫213的第二绝缘保护层开孔220b，又该第一基板20中形成有贯穿该第一表面20a与第二表面20b且电性连接该置晶垫211、第一电性接触垫212与第二电性接触垫213的导电通孔203。
如图2B所示，于该第一绝缘保护层22a上形成多个分别对应电性连接各该置晶垫211与第一电性接触垫212的置晶连接端231与电性连接端232。
如图2C所示，于该第一绝缘保护层22a、置晶连接端231与电性连接端232上形成介电层24，该介电层24可为感旋光性材质。
如图2D所示，于该介电层24中形成有分别对应该置晶区201与各该电性连接端232的第一介电层开孔241与第二介电层开孔242。
如图2E所示，以模板（stencil）印刷方式借由模板261于各该第二介电层开孔242中印刷形成第一铜柱251。
如图2F所示，以模板印刷方式借由模板262于离该置晶区201较远的一侧的该第一铜柱251上印刷形成第二铜柱252。
如图2G所示，于该第一介电层开孔241中的置晶连接端231上电性连接第一半导体芯片27。
如图2H所示，于该第一半导体芯片27与第一表面20a之间形成底充材料28或封装胶体。
如图2I所示，于靠该置晶区201较近的一侧的各该第一铜柱251上形成第一焊球30，并于该第一焊球30上叠置并电性连接第一封装结构3，其中，该第一封装结构3包括第二基板31与覆晶接置其上的第二半导体芯片32，且该第二半导体芯片32位于该第二基板31与介电层24之间，另还于各该第二电性接触垫213上形成焊料凸块29。
如图2J所示，于各该第二铜柱252上形成第二焊球40，并于该第二焊球40上叠置并电性连接第二封装结构4，其中，该第二封装结构4包括第三基板41与覆晶接置其上的第三半导体芯片42，且该第三基板41位于该第三半导体芯片42与第二基板31之间。
本发明还提供一种层叠封装的封装结构，其包括：第一基板20，其具有相对的第一表面20a与第二表面20b，该第一表面20a定义有置晶区201与围绕该置晶区201的非置晶区202，该置晶区201与非置晶区202的第一表面20a上分别具有多个置晶垫211与多个第一电性接触垫212；第一绝缘保护层22a，其形成于该第一表面20a、置晶垫211与第一电性接触垫212上，并具有多个对应外露各该置晶垫211与各该第一电性接触垫212的第一绝缘保护层开孔220a；多个置晶连接端231与电性连接端232，其形成于该第一绝缘保护层22a上，并分别对应电性连接各该置晶垫211与第一电性接触垫212；介电层24，其形成于该第一绝缘保护层22a、置晶连接端231与电性连接端232上，并具有分别对应该置晶区201与各该电性连接端232的第一介电层开孔241与第二介电层开孔242，该介电层24为感旋光性材质；第一铜柱251，其形成于该各该第二介电层开孔242中；第一半导体芯片27，其设于该第一介电层开孔241中，并电性连接于该置晶连接端231上；第一焊球30，其形成于靠该置晶区201较近的一侧的各该第一铜柱251上；以及第一封装结构3，其叠置并电性连接于该第一焊球30上。
于前述的层叠封装的封装结构中，该第一封装结构3包括第二基板31与覆晶接置其上的第二半导体芯片32，且该第二半导体芯片32位于该第二基板31与介电层24之间。
依前所述的层叠封装的封装结构，还包括第二铜柱252、第二焊球40与第二封装结构4，该第二铜柱252形成于离该置晶区201较远的一侧的该第一铜柱251上，该第二焊球40形成于各该第二铜柱252上，且该第二封装结构4叠置并电性连接于该第二焊球40上。
于本发明的层叠封装的封装结构中，该第二封装结构4包括第三基板41与覆晶接置其上的第三半导体芯片42，且该第三基板41位于该第三半导体芯片42与第二基板31之间。
于前述的层叠封装的封装结构中，该第二表面20b上具有多个第二电性接触垫213，于该第二表面20b与第二电性接触垫213上并形成有第二绝缘保护层22b，且该第二绝缘保护层22b具有多个对应外露各该第二电性接触垫213的第二绝缘保护层开孔220b。
于本发明的层叠封装的封装结构中，该第一基板20中形成有贯穿该第一表面20a与第二表面20b且电性连接该置晶垫211、第一电性接触垫212与第二电性接触垫213的导电通孔203。
所述的层叠封装的封装结构中，还包括焊料凸块29，其形成于各该第二电性接触垫213上，且还包括底充材料28或封装胶体，其形成于该第一半导体芯片27与第一表面20a之间。
综上所述，不同于现有技术，由于本发明的封装结构通过于多个不同的电性连接端上形成有不同高度的铜柱，并利用该等铜柱定义出封装结构容置区，因而能在有限的空间中接置半导体芯片与另一封装结构，且能在最高的铜柱上再堆栈第二个封装结构，即本发明可使用较小的焊球来连接封装结构，故能有效缩小最终结构的平面尺寸与厚度；此外，本发明以模板印刷方式来形成铜柱，所以可提供高良率、细间距与高度均匀性佳的电性连接方式。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (15)

1.一种层叠封装的封装结构，其包括：
第一基板，其具有相对的第一表面与第二表面，该第一表面定义有置晶区与围绕该置晶区的非置晶区，该置晶区与非置晶区的第一表面上分别具有多个置晶垫与多个第一电性接触垫；
第一绝缘保护层，其形成于该第一表面、置晶垫与第一电性接触垫上，并具有多个对应外露各该置晶垫与各该第一电性接触垫的第一绝缘保护层开孔；
多个置晶连接端与电性连接端，其形成于该第一绝缘保护层上，并分别对应电性连接各该置晶垫与第一电性接触垫；
介电层，其形成于该第一绝缘保护层、置晶连接端与电性连接端上，并具有分别对应该置晶区与各该电性连接端的第一介电层开孔与第二介电层开孔；
第一铜柱，其形成于该各该第二介电层开孔中；
第一半导体芯片，其设于该第一介电层开孔中，且电性连接于该置晶连接端上；
第一焊球，其形成于靠该置晶区较近的一侧的各该第一铜柱上；以及
第一封装结构，其叠置并电性连接于该第一焊球上。
2.根据权利要求1所述的层叠封装的封装结构，其特征在于，该第一封装结构包括第二基板与覆晶接置其上的第二半导体芯片，且该第二半导体芯片位于该第二基板与介电层之间。
3.根据权利要求2所述的层叠封装的封装结构，其特征在于，该封装结构还包括第二铜柱、第二焊球与第二封装结构，该第二铜柱形成于离该置晶区较远的一侧的该第一铜柱上，该第二焊球形成于各该第二铜柱上，且该第二封装结构叠置并电性连接于该第二焊球上。
4.根据权利要求3所述的层叠封装的封装结构，其特征在于，该第二封装结构包括第三基板与覆晶接置其上的第三半导体芯片，且该第三基板位于该第三半导体芯片与第二基板之间。
5.根据权利要求1所述的层叠封装的封装结构，其特征在于，该第二表面上具有多个第二电性接触垫，于该第二表面与第二电性接触垫上并形成有第二绝缘保护层，且该第二绝缘保护层具有多个对应外露各该第二电性接触垫的第二绝缘保护层开孔。
6.根据权利要求5所述的层叠封装的封装结构，其特征在于，该第一基板中形成有贯穿该第一表面与第二表面且电性连接该置晶垫、第一电性接触垫与第二电性接触垫的导电通孔。
7.根据权利要求1所述的层叠封装的封装结构，其特征在于，该介电层为感旋光性材质。
8.一种层叠封装的封装结构的制法，其包括：
提供一具有相对的第一表面与第二表面的第一基板，该第一表面定义有置晶区与围绕该置晶区的非置晶区，该置晶区与非置晶区的第一表面上分别具有多个置晶垫与多个第一电性接触垫，于该第一表面、置晶垫与第一电性接触垫上形成有第一绝缘保护层，该第一绝缘保护层具有多个对应外露各该置晶垫与各该第一电性接触垫的第一绝缘保护层开孔；
形成多个分别对应电性连接各该置晶垫与第一电性接触垫的置晶连接端与电性连接端于该第一绝缘保护层上；
形成介电层于该第一绝缘保护层、置晶连接端与电性连接端上，且该介电层具有分别对应该置晶区与各该电性连接端的第一介电层开孔与第二介电层开孔；
形成第一铜柱于各该第二介电层开孔中；
电性连接第一半导体芯片于该第一介电层开孔中的置晶连接端上；
形成第一焊球于靠该置晶区较近的一侧的各该第一铜柱上；以及叠置并电性连接第一封装结构于该第一焊球上。
9.根据权利要求8所述的层叠封装的封装结构的制法，其特征在于，该第一封装结构包括第二基板与覆晶接置其上的第二半导体芯片，且该第二半导体芯片位于该第二基板与介电层之间。
10.根据权利要求9所述的层叠封装的封装结构的制法，其特征在于，于形成该第一铜柱之后，还包括形成第二铜柱于离该置晶区较远的一侧的该第一铜柱上，且于电性连接该第一封装结构之后，还包括形成第二焊球于各该第二铜柱上，叠置并电性连接第二封装结构于该第二焊球上。
11.根据权利要求10所述的层叠封装的封装结构的制法，其特征在于，该第二封装结构包括第三基板与覆晶接置其上的第三半导体芯片，且该第三基板位于该第三半导体芯片与第二基板之间。
12.根据权利要求10所述的层叠封装的封装结构的制法，其特征在于，形成该第二铜柱的方式为模板印刷。
13.根据权利要求8所述的层叠封装的封装结构的制法，其特征在于，该第二表面上具有多个第二电性接触垫，于该第二表面与第二电性接触垫上并形成有第二绝缘保护层，且该第二绝缘保护层具有多个对应外露各该第二电性接触垫的第二绝缘保护层开孔。
14.根据权利要求13所述的层叠封装的封装结构的制法，其特征在于，该第一基板中形成有贯穿该第一表面与第二表面且电性连接该置晶垫、第一电性接触垫与第二电性接触垫的导电通孔。
15.根据权利要求8所述的层叠封装的封装结构的制法，其特征在于，形成该第一铜柱的方式为模板印刷。
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