CN103138768B - The equipment of the channel in coding and decoding communication system and method - Google Patents

Abstract

The invention provides a kind of for producing equipment and the method for the parity check matrix of low-density checksum inspection (LDPC) code. A kind of method for decoding the channel using low-density checksum to check in the communication system of LDPC code, extracts the parity check matrix of LDPC code; Utilizing the parity check matrix of described extraction, perform LDPC decoding, wherein code check is 3/5 and code word size is 16200.

Description

The equipment of the channel in coding and decoding communication system and method

The divisional application of application for a patent for invention that the application is the applying date, and to be on February 18th, 2009, application number be 200980105340.8, denomination of invention is " for encoding and decode equipment and the method for the channel in the communication system using low-density checksum check code ".

Technical field

This invention relates generally to use the communication system of low-density checksum inspection (LDPC) code, more particularly, to being used for producing channel encoding/decoding device and the method for the LDPC code of specific type.

Background technology

In a wireless communication system, due to the multiple noise in channel, fade-out and intersymbol interference (ISI), link performance significantly reduces. Therefore, in order to realize requiring the high-speed digital communication system of high data throughout and reliability, for instance next generation mobile communication, digital broadcasting and mobile Internet, it is necessary to develop a kind of technology for overcoming noise, decline and ISI. Recently, to relating to error correcting code by there being the information of efficient recovery distortion to improve the use in communication reliability, conduct in-depth research.

LDPC code, is first proposed in nineteen sixties by Gallager, and due to its complicated realization that can not be solved by the technology in past, LDPC code is not fully utilized always. But, Berrou, Glavieux and Thitimajshima the Turbo code found in 1993, show the performance close to the Shannon channel limit. So, studied to the chnnel coding of repeat decoding and graphic based and to the performance of Turbo code and the analysis of characteristic. Due to this research, LDPC code was restudied in later stage nineteen nineties, if proving by applying based on the repeat decoding scheming in (special circumstances of factor graph) and long-pending (sum-product) algorithm at the Tanner corresponding to LDPC code, LDPC code is decoded, then LDPC code has the performance close to the Shannon channel limit.

LDPC code generally uses figure presentation technology to represent, graphic based is theoretical, the method for algebraical sum theory of probability, it is possible to analyze a lot of characteristic. Generally, the graph model of channel code is useful to the explanation of code. By by the summit (vertex) in the information MAP on the bit of coding to figure and by by the limit (edge) of the relationship map between bit to figure, it is possible to consider following communication network: the message that edge flip is predetermined is passed through on summit in the communications network. This makes it possible to derive natural decoding algorithm. Such as, the decoding algorithm derived from the grid (trellis) being taken as a kind of figure can include known Viterbi algorithm and Bahl, Cocke, Jelinek and Raviv(BCJR) algorithm.

LDPC code is normally defined parity check matrix, it is possible to utilizing bipartite graph (bipartitegraph) to represent, this bipartite graph refers to that Tanner schemes. In the bipartite graph summit constituting figure, figure is divided into two different types, and the bipartite graph that LDPC code is made up of summit represents, some bipartite graph called after variable nodes, and other bipartite graph called after checks node. Variable node is mapped to the bit of coding one to one.

With reference to Fig. 1 and Fig. 2, will be described for the graphical representation method of LDPC code.

Fig. 1 illustrates the parity check matrix H being arranged the LDPC code formed by 4 row 8₁Example. With reference to Fig. 1, owing to the number of row is 8, LDPC code produces the code word (codeword) of 8 bit lengths, and row are mapped to the bit of 8 codings.

Fig. 2 illustrates the H corresponding to Fig. 1₁The figure of Tanner figure.

With reference to Fig. 2, the Tanner figure of LDPC code is by 8 variable node x₁(202),x₂(204),x₃(206),x₄(208),x₅(210),x₆(212),x₇And x (214)₈(216) and 4 check node 218,220,222 and 224 composition. The parity check matrix H of LDPC code₁I-th row and jth row be respectively mapped to variable node x_iNode is checked with jth. Additionally, value 1, i.e. nonzero value, it is positioned at the parity check matrix H of LDPC code₁I-th row and the cross one another point of jth row on, it is indicated that the variable node x on Tanner figure as shown in Figure 2_iWith jth checks there is limit between node.

In the Tanner figure of LDPC code, the degree of variable node and inspection node is defined as the number on the limit being connected to each respective node, and degree is equal to the number corresponding to the non-zero input in the column or row of the node of association in the parity check matrix of LDPC code. Such as, in fig. 2, variable node x₁(202),x₂(204),x₃(206),x₄(208),x₅(210),x₆(212),x₇And x (214)₈(216) degree respectively 4,3,3,3,2,2,2 and 2, checks the degree of node 218,220,222 and 224 respectively 6,5,5 and 5. Additionally, the parity check matrix H of Fig. 1₁The row variable node of Fig. 2 (its corresponding to) in the number of non-zero input, equal to its degree 4,3,3,3,2,2,2 and 2. The parity check matrix H of Fig. 1₁The row inspection node of Fig. 2 (its corresponding to) in the number of non-zero input, equal to its degree 6,5,5 and 5.

Degree in order to express the node of LDPC code is distributed, degree-i(degree-i) ratio of the total number of number and the variable node of variable node is defined as f_i, degree-j(degree-j) and check that the number of node is defined as g with the ratio of the total number checking node_j. Such as, for the LDPC code corresponding to Fig. 1 and Fig. 2, f₂=4/8,f₃=3/8,f₄=1/8, the f when i ≠ 2,3,4_i=0;g₅=3/4,g₆=1/4, the g when j ≠ 5,6_j=0. Length when LDPC code, i.e. the number of row, is defined to N, and the number of row is defined to N/2, and the density such as formula (1) with the non-zero input in the overall parity check matrix of above-mentioned degree distribution calculates.

$\frac{2f_{2}N+3f_{3}N+4f_{4}N}{N\·N/2}=\frac{5.25}{N}...\left(1\right)$

In formula (1), when N increases, the decrease in density of ' 1 ' in parity check matrix. Generally for LDPC code, owing to the density of code length N with non-zero input is inversely proportional to, the LDPC code with big N has the density of low-down non-zero input. Word ' low-density ' in the title of LDPC code originates from above-mentioned relation.

It follows that with reference to Fig. 3, the characteristic of the parity check matrix of the structurized LDPC code that explanation is applied in the present invention. Fig. 3 diagrammatically illustrates and transmits, at second filial generation digital video broadcast satellite, the LDPC code adopted as standard technique in (DVB-S2), and DVB-S2 is one of European digital broadcast standard.

In figure 3, N₁Represent the length of LDPC code word, K₁Provide the length of information word (informationword), and (N₁-K₁) provide odd-even check length. Additionally, integer M₁It is determined to meet q=(N with q₁-K₁)/M₁. Preferably, K₁/M₁It is desirably also integer.

With reference to Fig. 3, the parity portion in parity check matrix, i.e. K₁Arrange (N₁-l) row, structure there is double diagonal line shape. Being distributed accordingly, as corresponding to the degree on the row of parity portion, all of row degree of having ' 2 ', except last string degree of having ' 1 '.

In parity check matrix, message part, namely, the 0th row are to (K₁-1) structure arranged utilizes following rule to draw.

Rule 1: by would correspond to the K of the information word in parity check matrix₁Individual row composition is each by M₁Multiple groups of row composition, produce K altogether₁/M₁Individual row group (columngroup). The method forming the row belonging to each row group follows following regular 2.

Rule 2: first determine i-th row group each 0th row ' 1 ' position (wherein i=1 ..., K₁/M₁). When the degree of each 0th row in i-th row group is by D_iDuring expression, if being the hypothesis on location of the row of 1 it isIt it is the position of the row of 1(K=1,2 ..., D_i) the jth of i-th row group arrange (wherein j=1,2 ..., M₁-1), as formula (2) defines.

$R_{i,j}^{\left(k\right)}=R_{i,(j-1)}^{\left(k\right)}+q\mathrm{mod}(N_1-k_1)$

K=1,2,...,D_i,i=1,...,K₁/M₁,j=1,...,M₁-1.......(2)

According to above-mentioned rule, it should be understood that belong to i-th row group (wherein i=1 ..., K₁/M₁) the degree of row be equal to D_i. In order to be best understood from the structure of the DVB-S2LDPC code of the information that stores on parity check matrix according to above-mentioned rule, following specific example will be described.

As specific example, for N₁=30, K₁=15, M₁=5 and q=3, in 3 row groups, three sequences of the 0th information being classified as on the position of the row of 1 can be expressed as follows. Herein, for facilitating this sequence to be called " weight-1 position sequence "

$R_{\mathrm{1,0}}^{\left(1\right)}=0,$ $R_{\mathrm{1,0}}^{\left(2\right)}=1,$ $R_{\mathrm{1,0}}^{\left(3\right)}=2$

$R_{\mathrm{2,0}}^{\left(1\right)}=0,$ $R_{\mathrm{2,0}}^{\left(2\right)}=11,$ $R_{\mathrm{2,0}}^{\left(3\right)}=13$

$R_{\mathrm{3,0}}^{\left(1\right)}=0,$ $R_{\mathrm{3,0}}^{\left(2\right)}=10,$ $R_{3,0}^{\left(3\right)}=14$

About weight-1 position sequence of the in each row group the 0th row, the position sequence only corresponding for each row group can be expressed as follows. Such as:

012

01113

01014

In other words, i-th weight-1 position sequence of the i-th row sequentially represents in i-th row group the information of the position of the row being 1.

Utilize the information corresponding to specific example and rule 1 and rule 2, by forming parity check matrix, it is possible to produce the LDPC code with the DVB-S2LDPC code same concept with Fig. 4.

The known DVB-S2LDPC code according to rule 1 and rule 2 design can utilize structurized shape to be efficiently encoded. To illustrate as follows by the mode of example in each step utilizing the parity check matrix based on DVB-S2 to perform in the method for LDPC coding.

In following, as specific example, to N₁=16200, K₁=10800,M₁=360 and the DVB-S2LDPC code of q=15 be encoded processing. For convenient, there is K₁The information bit of length is expressed asThere is (N₁-K₁) Parity Check Bits of length is expressed as

Step 1:LDPC encoder initializes Parity Check Bits as follows:

$p_0=p_1=...=p_{N_1-K_1-1}=0$

Step 2:LDPC encoder reads the information row from the 0th weight-1 position sequence outside the sequence of the storage representing parity check matrix, and in this row, 1 is arranged in row group.

0208416131548128614603196429724813369345146202622

$R_{\mathrm{1,0}}^{\left(1\right)}=0,$ $R_{\mathrm{1,0}}^{\left(2\right)}=2048,$ $R_{\mathrm{1,0}}^{\left(3\right)}=1613,$ $R_{\mathrm{1,0}}^{\left(4\right)}=1548,$ $R_{\mathrm{1,0}}^{\left(5\right)}=1286,$

$R_{\mathrm{1,0}}^{\left(6\right)}=1460,$ $R_{\mathrm{1,0}}^{\left(7\right)}=3196,$ $R_{\mathrm{1,0}}^{\left(8\right)}=4297,$ $R_{\mathrm{1,0}}^{\left(9\right)}=2481,$ $R_{\mathrm{1,0}}^{\left(10\right)}=3369,$

$R_{\mathrm{1,0}}^{\left(11\right)}=3451,$ $R_{\mathrm{1,0}}^{\left(12\right)}=4620,$ $R_{\mathrm{1,0}}^{\left(13\right)}=2622.$

LDPC encoder utilizes the information and first information bit i that read₀, update concrete Parity Check Bits p according to formula (3)_x. Herein, x representsValue, wherein k=1,2 ... 13.

$p_0=p_0\⊕i_0,$ $p_{2084}=p_{2064}\⊕i_0,$ $p_{1613}=p_{1613}\⊕i_0$

$p_{1548}=p_{1548}\⊕i_0,$ $p_{1286}=p_{1286}\⊕i_0,$ $p_{1460}=p_{1460}\⊕i_0$

$p_{3196}=p_{3196}\⊕i_0,$ $p_{4297}=p_{4297}\⊕i_0,$ $p_{2481}=p_{2481}\⊕i_0---\left(3\right)$

$p_{3369}=p_{3369}\⊕i_0,$ $p_{3451}=p_{3451}\⊕i_0,$ $p_{4620}=p_{4620}\⊕i_0,$

$p_{2622}=p_{2622}\⊕i_0$

In equation (3),Can also be expressed as Represent binary addition.

Step 3:LDPC encoder is first against i₀After 359 information bit i_m(wherein m=1,2 ... 359) find out the value of formula (4).

{x+(mmodM₁)×q}mod(N₁-K₁), M₁=360, m=1,2 ..., 359 ... (4)

In formula (4), x representsValue, wherein k=1,2 ..., 13. It should be noted that formula (4) has the concept identical with formula (2).

It follows that LDPC encoder utilizes the value found in formula (4) to perform similarly to the computing of formula (3). That is, LDPC encoder is i_mUpdateSuch as, m=1 is worked as, i.e. for i₁, LDPC encoder updates Parity Check BitsIn formula (5) defined.

$p_{15}=p_{15}\⊕i_1,$ $p_{2099}=p_{2099}\⊕i_1,$ $p_{1628}=p_{1628}\⊕i_1$

$p_{1563}=p_{1563}\⊕i_1,$ $p_{1301}=p_{1301}\⊕i_1,$ $p_{1475}=p_{1475}\⊕i_1$

$p_{3211}=p_{3211}\⊕i_1,$ $p_{4312}=p_{4312}\⊕i_1,$ $p_{2496}=p_{2496}\⊕i_1---\left(5\right)$

$p_{3384}=p_{3384}\⊕i_1,$ $p_{3466}=p_{3466}\⊕i_1,$ $p_{4635}=p_{4635}\⊕i_1,$

$p_{2637}=p_{2637}\⊕i_1$

It should be noted that in formula (5), q=15. LDPC encoder with identical method as implied above for m=1,2 ..., 359 perform above-mentioned process.

Step 4: as in step 2, LDPC encoder is the 361st information bit i₃₆₀Read the 1st weight-1 position sequence(k=1,2 ..., 13) information, and update concrete p_x, wherein x representsLDPC encoder is by applying formula (4) to i similarly₃₆₀Ensuing 359 information bits update afterwards $P_{\{x+\left({m\mathrm{mod}M}_1\right)\×q\}\mathrm{mod}(N_1-K_1)},$ M=361,362 ..., 719.

Step 5:LDPC encoder all of group (each having 360 information bits) is repeated step 2,3 and 4.

Step 6:LDPC encoder utilizes formula (6) finally to determine Parity Check Bits.

$p_i=p_i\⊕p_{i-1},i=\mathrm{1,2},...,N_1-K_1-1---\left(6\right)$

The Parity Check Bits of formula (6) is the Parity Check Bits through LDPC coding.

As it has been described above, in DVB-S2, LDPC encoder performs LDPC coding by the method for step 1 to step 6.

The ring property (cyclecharacteristics) of the performance of known LDPC code and Tanner figure is closely related. Specifically, when the number of known (short-length) ring short when length is very big in Tanner figure by experiment, it may occur that performance degradation. So, in order to design, there is high performance LDPC code, it is contemplated that the ring property of Tanner figure.

But, currently without the method proposed for designing the DVB-S2LDPC code with good ring property. For DVB-S2LDPC code, when being left out the optimization of ring property of Tanner figure, observe error floor phenomenon (errorfloorphenomenon) when high s/n ratio (SNR). For those reasons, it is necessary to a kind of method can be effectively improved ring property when design has the LDPC code of DVB-S2 structure.

Summary of the invention

Make the present invention to solve at least the above and/or shortcoming, and at least following beneficial effect is provided. Therefore, an aspect of of the present present invention provides channel encoding/decoding device and method, for in the communication system utilizing LDPC code, design the parity check matrix of quasi-circulation (quasi-cyclic) LDPC code based on cycle arrangement (circulantpermutation) matrix design, thus designing DVB-S2LDPC code.

Another aspect provides channel encoding/decoding device and method, for, in the communication system utilizing LDPC code, designing the parity check matrix of the LDPC code same with the DVB-S2LDPC code-phase with good Tanner figure characteristic.

According to an aspect of the present invention, it is provided that the method producing the parity check matrix of low-density checksum inspection (LDPC) code. Determine the parameter of design LDPC code. According to determined parameter, form the first parity check matrix of quasi-cyclic LDPC code. By removing the predetermined portions of the parity portion in the first parity check matrix, produce the second parity check matrix. The 3rd parity check matrix is produced by rearranging the second parity check matrix.

According to a further aspect in the invention, it is provided that for the method encoding the channel in the communication system using low-density checksum inspection (LDPC) code. Read the parity check matrix of storage. The signal received is carried out LDPC coding by the parity check matrix utilizing storage. Parity check matrix is divided into information word and even-odd check. When code check is 3/5, code word size is 16200, forms parity check matrix as definedly in following table;

According to another embodiment of the invention, it is provided that the method for decoding channel in the communication system using low-density checksum inspection (LDPC) code. Extract the parity check matrix of LDPC code. The parity check matrix extracted is utilized to perform LDPC decoding. The parity check matrix extracted is divided into parity check sum information word. When code check is 3/5, and when code word size is 16200, formation parity check matrix as defined in following table;

According to another aspect of the present invention, it is provided that the equipment of coding channel in the communication system using low-density checksum inspection (LDPC) code. LDPC code parity check matrix extractor reads the parity check matrix of storage. LDPC encoder utilizes the parity check matrix of storage that the signal received is carried out LDPC-coding. Parity check matrix is divided into parity check sum information word. When code check is 3/5, and when code word size is 16200, formation parity check matrix as defined in following table;

According to another aspect of the present invention, it is provided that the equipment of decoding channel in the communication system utilizing low-density checksum inspection (LDPC) code. LDPC code parity check matrix extractor reads the parity check matrix of storage. LDPC decoder utilizes the parity check matrix read to perform LDPC decoding. The parity check matrix read is divided into parity check sum information word. When code check is 3/5, and when code word size is 16200, as defined in following table forms the parity check matrix read;

Accompanying drawing explanation

By reference accompanying drawing, the above-mentioned feature with other of the present invention and beneficial effect become more apparent upon by being described below in detail, wherein:

Fig. 1 is the figure of the parity check matrix of the LDPC code that 8 bit lengths are described.

Fig. 2 is the figure of the Tanner figure of the parity check matrix of the LDPC code that 8 bit lengths are described.

Fig. 3 is the figure of the schematic structure that DVB-S2LDPC code is described.

Fig. 4 is the figure of the parity check matrix that DVB-S2LDPC code is described.

Fig. 5 is the figure that parity check matrix according to an embodiment of the invention is described, this parity check matrix according to predetermined rule, is generated by the columns and rows that rearrange in the parity check matrix of the DVB-S2LDPC code of Fig. 4.

Fig. 6 illustrates according to an embodiment of the invention for designing the figure of the parity check matrix of the quasi-cyclic LDPC code needed for DVB-S2LDPC code.

Fig. 7 illustrates according to an embodiment of the invention by deforming the figure of the result that the parity check matrix for the quasi-cyclic LDPC code needed for designing DVB-S2LDPC code obtains.

Fig. 8 is the flow chart illustrating to design according to an embodiment of the invention the process of DVB-S2LDPC code.

Fig. 9 illustrates figure to the Computer simulation results of DVB-S2LDPC code according to an embodiment of the invention.

Figure 10 is the block diagram of the structure of the transceiver illustrated according to an embodiment of the invention in the communication system using the DVB-S2LDPC code redesigned.

Figure 11 is the block diagram of the structure launching equipment illustrating to utilize according to an embodiment of the invention LDPC code.

Figure 12 is the block diagram of the structure receiving equipment illustrating to utilize according to an embodiment of the invention LDPC code.

Figure 13 is the flow chart receiving work illustrated according to an embodiment of the invention in the reception equipment utilizing LDPC code.

Detailed description of the invention

By reference accompanying drawing, will be described in the preferred embodiment of the present invention. Although illustrating in different drawings, but identical or similar element represents with identical or similar accompanying drawing labelling. The specific description of structure as known in the art and method can be omitted to avoid so that the main body of the present invention is inconspicuous.

The method that present invention provide for designing the DVB-S2LDPC code with good Tanner figure characteristic. Additionally, the invention provides the parity check matrix of the LDPC code utilizing above-mentioned design to produce method and the equipment thereof of LDPC code word.

The parity check matrix description of the characteristic utilization of the structure of DVB-S2LDPC code DVB-S2LDPC code as shown in Figure 4 is as follows. For parity check matrix as shown in Figure 4, N₁=30, K₁=15,M₁=5 and q3, and weight-1 position sequence of the row of the 0th row in three row groups is as follows:

012

01113

01014

At this, i-th weight-1 position sequence of the i-th row sequentially represents in i-th row group the information of the position of the row being 1.

The parity check matrix of Fig. 4 is re-constructed according to following rules. Fig. 4 is the figure of the parity check matrix that DVB-S2LDPC code is described.

Rule 3: rearrange the 0th row to (N₁-K₁-1) OK so that (q i+j) line position is in (M₁J+i) in row, wherein 0≤i≤M₁And 0≤j≤q.

Rule 4: keep the 0th to arrange (K₁-1) arrange constant, rearrange K₁Arrange (N₁-1) row make (K₁+ q i+j) row be positioned at (K₁+M₁J+i) row.

According to rule 3 and rule 4, by re-constructing the parity check matrix of Fig. 4, it is thus achieved that have the parity check matrix of shape as shown in Figure 5. Fig. 5 is the figure that parity check matrix according to an embodiment of the invention is described, this parity check matrix according to predetermined rule, is generated by the columns and rows that rearrange in the parity check matrix of the DVB-S2LDPC code of Fig. 4.

If it is assumed that Fig. 5 ' 1 ' is present in (N of the 0th row₁-1) row, it should be understood that the parity check matrix in Fig. 5 is corresponding to a kind of quasi-cyclic LDPC code, and it is by M₁×M₁, i.e. the cycle arrangement matrix composition of 5 × 5 sizes. ' cycle arrangement matrix ' is defined through in unit matrix to the right cyclic shift row and a kind of permutation matrix of producing one by one. Additionally, ' quasi-cyclic LDPC code ' is defined through to be divided into parity check matrix several has the block (block) of formed objects and a kind of LDPC code by cycle arrangement matrix or null matrix are mapped to block and are produced.

In sum, it should be understood that the parity check matrixes of DVB-S2LDPC code can be re-constructed by rule 3 and regular 4 and obtain the parity check matrix of similar quasi-cyclic LDPC code. Likewise it is possible to be contemplated that the inverse process by rule 3 and rule 4, it is possible to produce DVB-S2LDPC code from quasi-cyclic LDPC code.

Although there is no the known result of study to DVB-S2LDPC code, but there is a lot of known method for designing for quasi-cyclic LDPC code. The known method of the ring property for optimizing Tanner figure is included for the method for designing of quasi-cyclic LDPC code.

Embodiments of the invention propose the method for the known method design DVB-S2LDPC code of the ring property utilizing the Tanner figure improving quasi-cyclic LDPC code. But, the method owing to improving the ring property of quasi-cyclic LDPC code only indirectly relates to the present invention, omits its detailed description for simplification.

The explanation utilizing the method for quasi-cyclic LDPC code design DVB-S2LDPC code provides as follows. DVB-S2LDPC code has code word size N₁, message length K₁, and even-odd check length (N₁-K₁), and q=(N₁-K₁)/M₁。

The parity check matrix of quasi-cyclic LDPC code is as shown in Figure 6. Fig. 6 illustrates according to an embodiment of the invention for designing the figure of the parity check matrix of the quasi-cyclic LDPC code needed for DVB-S2LDPC code. Parity check matrix as shown in Figure 6 has (N₁-K₁) go and N₁Row, and it is divided into M₁×M₁Localized mass. For convenient, if t=K₁/M₁, the message part of the parity check matrix of Fig. 6 and parity portion include t row block (columnblock) and q row block respectively, have q row block (rowblock) altogether. This, N₁/M₁=t+q.

The block of the respective local of the parity check matrix of composition diagram 6 corresponds to cycle arrangement matrix or null matrix. At this, cycle arrangement matrix has M₁×M₁Size, and produce based on cycle arrangement matrix P, its definition is as follows:

In Fig. 6, a_ijIt is 0 to M₁The integer of-1 or the value of ∞, P⁰It is defined as unit matrix I, P^∞Represent M₁×M₁Null matrix. Additionally, the numeral ' 0 ' in parity portion represents M₁×M₁Null matrix.

The parity check matrix of Fig. 6 is characterised by, the row block corresponding to even-odd check has unit matrix I and cycle arrangement matrixAs shown in the figure. In other words, the row block corresponding to even-odd check is fixed as the structure shown in Fig. 6. Cycle arrangement matrixDefine as follows:

Quasi-cyclic LDPC code as shown in Figure 6 is the part remained unchanged in optimizing the method for the ring of quasi-cyclic LDPC code, because the structure corresponding to the row block of its parity portion is fixing. In other words, owing to the row block corresponding to parity portion is fixed in the parity check matrix of Fig. 6, corresponding to being connected on Tanner figure to be determined between the variable node of even-odd check, in order to optimize the ring of Tanner figure, therefore only need to optimize corresponding to the connection between the variable node of message part.

As it has been described above, there are many known methods of the ring property of the Tanner figure optimizing quasi-cyclic LDPC code. Method for designing owing to being used for having the quasi-cyclic LDPC code of the Tanner figure of the ring property of optimization only indirectly relates to the present invention, omits its detailed description at this.

Assuming that degree of certainty is distributed to show outstanding performance in following state: the structure of parity portion is by the method for designing for quasi-cyclic LDPC code in a state, the standard at Fig. 6 circulates in parity check matrix is fixed. The position of cycle arrangement matrix and null matrix is distributed in corresponding to being determined in the row block of message part according to degree. The ring property of Tanner figure is thus optimised.

The such as form shown in Fig. 7 is by cycle arrangement matrixThe first row last string in eliminate ' 1 ' and draw, this cycle arrangement matrixLast (the N of the first row block corresponding to the parity check matrix of Fig. 6₁/M₁) or (t+q) row block. Fig. 7 illustrates according to an embodiment of the invention by deforming the figure of the result that the parity check matrix for the quasi-cyclic LDPC code needed for designing DVB-S2LDPC code obtains.

It should be noted that cycle arrangement matrixIt is changed to following matrix Q in the figure 7.

Following regular 5 and regular 6 are defined as the processes adopting rule 3 contrary with rule 4.

Rule 5: keep the 0th to arrange (K₁-1) arrange constant, rearrange K₁To (N₁-1) row so that (K₁+M₁J+i) row are positioned at (K₁+ q i+j) row, wherein 0≤i≤M₁And 0≤j≤q.

Rule 6: rearrange the 0th row to (N₁-K₁-1) OK so that (M₁J+i) line position is in (q i+j) OK.

Such as, the parity check matrix of the LDPC code produced from the quasi-cyclic LDPC code of Fig. 6 becomes the parity check matrix of the form with the DVB-S2LDPC code shown in Fig. 3 by adopting the said process of rule 5 and rule 6. The above-mentioned method for designing DVB-S2 parity check matrix can be summarized as following step, wherein, and the code word of this DVB-S2 parity check matrix, information and even-odd check length respectively N₁、K₁, and (N₁-K₁), and q=(N₁-K₁)/M₁。

DVB-S2LDPC code design process

Fig. 8 is the flow chart illustrating to design according to an embodiment of the invention the process of DVB-S2LDPC code.

With reference to Fig. 8, the parameter needed for determining for the DVB-S2LDPC code of expected design in step 801. It is assumed herein that have determined that such as code word size and message length and the parameter of good degree distribution in advance for design DVB-S2LDPC code.

It follows that in step 803, according to determined parameter in step 801 formed as shown in Figure 6 by M₁×M₁The parity check matrix of the quasi-cyclic LDPC code of cycle arrangement matrix and null matrix composition. In figure 6, the row block corresponding to parity portion is always fixed into special form.

In step 805, by adopting the algorithm of the ring property of the Tanner figure for improving quasi-cyclic LDPC code to determine the cycle arrangement matrix of the row block corresponding to Fig. 6 message part. Any known algorithm for improving ring property can be used at this.

In step 807, by the last string of the first row of the parity check matrix in that obtained in step 805, Fig. 6 is removed ' 1 ' and obtained the such as parity check matrix shown in Fig. 7.

In step 809, by the parity check matrix application of Fig. 7 rule 5 and rule 6 being rearranged parity check matrix column and the row of Fig. 7. The parity check matrix finally obtained can be DVB-S2LDPC code as shown in Figure 3.

Code word is generated by LDPC code being applied above-mentioned DVB-S2LDPC cataloged procedure through above-mentioned steps.

In order to analyze the performance of DVB-S2LDPC code, devise the DVB-S2LDPC code with parameters described below. Such as:

N₁=648000, K₁=38880, M₁=360, q=72

There is the DVB-S2LDPC code of the code check-3/5 of above-mentioned parameter for design, by applying DVB-S2LDPC code design process, from having N altogether₁/M₁=180 row block and q=(N₁-K₁)/M₁The quasi-cyclic LDPC code of=72 row blocks, it is possible to obtain the parity check matrix shown in such as table 1 and table 2. I-th weight-1 position sequence of the i-th row sequentially represents in the i-th row group the information of the position of the row being 1.

Table 1

Table 2

Additionally, devise the DVB-S2LDPC code with parameters described below. Such as,

N₁=16200, K₁=9720, M₁=360, q=18

There is the DVB-S2LDPC code of the code check-3/5 of above-mentioned parameter for design, by applying DVB-S2LDPC code design process, from having N altogether₁/M₁=45 row block and q=(N₁-K₁)/M₁The quasi-cyclic LDPC code of=18 row blocks is obtained in that the such as parity check matrix shown in table 3 to table 6. It should be noted that i-th weight-1 position sequence of the i-th row sequentially represents in the i-th row group the information of the position of the row being 1.

Table 3

Table 4

Table 5

Table 6

Between the DVB-S2LDPC code recently designed and existing DVB-S2LDPC code performance relatively as shown in Figure 9. Fig. 9 illustrates figure to the Computer simulation results of DVB-S2LDPC code according to an embodiment of the invention.

It should be understood that when Additive White Gaussian Noise (AWGN) channel adopts binary phase shift keying (BPSK) modulation principle, at BER=10^-4Time, it is achieved about the performance of 0.15dB is improved. Improve by simply changing the performance of the DVB-S2LDPC code that the information about the parity check matrix shown in table 1 to table 6 can realize code check-3/5.

DVB-S2LDPC code design process described in reference diagram 8 is used not only for the code check of 3/5 and can be used in other code checks. As being used for designing the example of the DVB-S2LDPC code with other code checks, devise the DVB-S2LDPC code with parameters described below.

N₁=64800, K₁=43200, M₁=360, q=60

There is the DVB-S2LDPC code of the code check-2/3 of above-mentioned parameter for design, it is possible to by the DVB-S2LDPC code design process of application drawing 8, from having N altogether₁/M₁The quasi-cyclic LDPC code of=180 row blocks and q=60 row block, it is thus achieved that the such as parity check matrix shown in table 7 to table 10.

Table 7

Table 8

Table 9

Table 10

Figure 10 is the block diagram illustrating to use according to an embodiment of the invention the structure of the transceiver in the communication system of the DVB-S2LDPC code of redesign.

Before being sent to receiver 1030, the LDPC encoder 1011 in transmitter 1010 it is imported into reference to Figure 10, message u. Then, the message u of LDPC encoder 1011 coding input, and provide the signal c of coding to manipulator 1013. The signal of manipulator 1013 modulating-coding and send the signal s of modulation to receptor 1030 by wireless channel 1020. Then the demodulator 1031 in receiver 1030 demodulates the signal r sent by emitter 1010, and exports the signal x of demodulation to LDPC decoder 1033. Then, LDPC decoder 1033 calculates the estimated value of message from the data received by wireless channelu。

The detailed construction of the transmission equipment in the communication system of the DVB-S2LDPC code that utilization redesigns is as shown in figure 11. Figure 11 is the block diagram of the structure launching equipment of the LDPC code illustrating to utilize according to an embodiment of the invention redesign.

Transmitting equipment includes controller 1130, LDPC code parity check matrix extractor 1110 and LDPC encoder 1150.

LDPC code parity check matrix extractor 1110 extracts LDPC code parity check matrix according to the requirement of system. LDPC code parity check matrix can be extracted from the sequence information shown in table 1 to table 10, it is possible to stored therein the memorizer of parity check matrix be extracted by utilizing, it is possible to given or be generated in transmitting equipment in transmitting equipment.

Controller 1130 is adapted to determine that required parity check matrix is to meet the requirement of system according to code check, code word size or message length.

LDPC encoder 1150 performs coding based on the LDPC code parity check matrix information read by controller 1130 and LDPC code parity check matrix extractor 1110.

Figure 12 is the block diagram illustrating to receive according to an embodiment of the invention the structure of equipment.

Figure 12 describes the signal for receiving from the communication system transmitting utilizing the DVB-S2LDPC code redesigned and recovers the reception equipment of the intended data of user from the signal received.

Reception equipment includes controller 1250, parity check matrix decision device (decider) 1230, LDPC code parity check matrix extractor 1270, demodulator 1210 and LDPC decoder 1290.

The LDPC code that demodulator 1210 demodulation receives, it is provided that the signal of demodulation is to parity check matrix decision device 1230 and LDPC decoder 1290.

Parity check matrix decision device 1230, under the control of controller 1250, based on the parity check matrix of the LDPC code used in the signal deciding system of demodulation.

Controller 1250 provides determination result to LDPC code parity check matrix extractor 1270 and LDPC decoder 1290 from parity check matrix decision device 1230.

LDPC code parity check matrix extractor 1270, under the control of controller 1250, the parity check matrix of the LDPC code needed for extraction system, it is provided that the parity check matrix extracted is to LDPC decoder 1290. As mentioned above, the parity check matrix of LDPC code can be extracted from such as sequence information shown in table 1 to table 10, can pass through to utilize the memorizer that stored therein parity check matrix to be extracted, it is possible to given in transmitting equipment, or can be generated in transmitting equipment.

LDPC decoder 1290, under the control of controller 1250, based on the information of the signal of the reception provided from demodulator 1210 and the parity check matrix about LDPC code from the offer of LDPC code parity check matrix extractor 1270, performs decoding.

Figure 12 receives the workflow diagram of equipment as shown in figure 13.

In step 1301, decoder 1210 receives the signal from the communication system transmitting utilizing the DVB-S2LDPC code redesigned, and demodulates received signal. Hereafter, in step 1303, the parity check matrix of the LDPC code of use in system is made decision by parity check matrix decision device 1230 based on the signal of demodulation.

In step 1305, the determination result from parity check matrix decision device 1230 is provided to LDPC code parity check matrix extractor 1270. LDPC code parity check matrix needed for step 1307, LDPC code parity check matrix extractor 1270 extraction system, and provide this matrix to LDPC decoder 1290.

As mentioned above, the parity check matrix of LDPC code can be extracted from such as sequence information shown in table 1 to table 10, can pass through to utilize the memorizer that stored therein parity check matrix to be extracted, it is possible to given in transmitting equipment, or can be generated in transmitting equipment.

Hereafter, in step 1309, LDPC decoder 1290, based on the information of the parity check matrix of the LDPC code about providing from LDPC code parity check matrix extractor 1270, performs decoding.

From above-mentioned it is obvious that the present invention optimizes the characteristic of Tanner figure design DVB-S2LDPC code, thus optimize the performance of the communication system utilizing LDPC code.

Although some preferred embodiment by reference to the present invention show and describes the present invention, it will be apparent to an ordinarily skilled person in the art that, under the premise of the spirit and scope without departing from claims invention defined, it is possible to carry out different changes in form and details.

Claims (6)

1. the method being used for using the channel in low-density checksum inspection (LDPC) code decoding communication system, comprises the steps:

Extract the parity check matrix of LDPC code; With

Utilize the parity check matrix of described extraction, perform LDPC decoding;

Wherein code check is 3/5 and code word size is 16200, the parity check matrix of described extraction has 27 row groups by would correspond to the row of information word and be divided into group and having, each row group has 360 row, and the parity check matrix of described extraction is as shown in the table:

Every a line in wherein said table includes sequence information, and described sequence information is pointed out wherein ' 1 ' to be positioned at the position of the row of the corresponding row group of described parity check matrix.

2. the method being used for using the channel in low-density checksum inspection (LDPC) code decoding communication system, comprises the steps:

Extract the parity check matrix of LDPC code; With

Utilize the parity check matrix extracted, perform LDPC decoding;

Wherein code check is 3/5 and code word size is 64800, the parity check matrix of described extraction has 108 row groups by would correspond to the row of information word and be divided into group and having, each row group has 360 row, and the parity check matrix of described extraction is as shown in the table:

Every a line in wherein said table includes sequence information, and described sequence information is pointed out wherein ' 1 ' to be positioned at the position of the row of the corresponding row group of described parity check matrix.

3. the method being used for using the channel in low-density checksum inspection (LDPC) code decoding communication system, comprises the steps:

Extract the parity check matrix of described LDPC code; With

Utilize the parity check matrix extracted, perform LDPC decoding;

Wherein code check is 2/3 and code word size is 64800, the parity check matrix of described extraction has 120 row groups by would correspond to the row of information word and be divided into group and having, each row group has 360 row, and the parity check matrix of described extraction is as shown in the table:

,

Every a line in wherein said table includes sequence information, and described sequence information is pointed out wherein ' 1 ' to be positioned at the position of the row of the corresponding row group of described parity check matrix.

4. it is used for using an equipment for the channel in low-density checksum inspection (LDPC) code decoding communication system, including:

For reading the LDPC code parity check matrix extractor of parity check matrix; With

For utilizing the parity check matrix of described reading to perform the LDPC decoder of LDPC decoding;

Wherein code check is 3/5 and code word size is 16200, the parity check matrix of described extraction has 27 row groups by would correspond to the row of information word and be divided into group and having, each row group has 360 row, and the parity check matrix of described extraction is as shown in the table:

,

Every a line in wherein said table includes sequence information, and described sequence information is pointed out wherein ' 1 ' to be positioned at the position of the row of the corresponding row group of described parity check matrix.

5. it is used for using an equipment for the channel in low-density checksum inspection (LDPC) code decoding communication system, including:

For reading the LDPC code parity check matrix extractor of parity check matrix; With

For utilizing the parity check matrix of described reading, perform the LDPC decoder of LDPC decoding;

Wherein code check is 3/5 and code word size is 64800, the parity check matrix of described extraction has 108 row groups by would correspond to the row of information word and be divided into group and having, each row group has 360 row, and the parity check matrix of described extraction is as shown in the table:

Every a line in wherein said table includes sequence information, and described sequence information is pointed out wherein ' 1 ' to be positioned at the position of the row of the corresponding row group of described parity check matrix.

6. it is used for using an equipment for the channel in low-density checksum inspection (LDPC) code decoding communication system, including:

For reading the LDPC code parity check matrix extractor of parity check matrix; With

For utilizing the parity check matrix of described reading, perform the LDPC decoder of LDPC decoding;

Wherein code check is 2/3 and code word size is 64800, the parity check matrix of described extraction has 120 row groups by would correspond to the row of information word and be divided into group and having, each row group has 360 row, and the parity check matrix of described extraction is as shown in the table:

Every a line in wherein said table includes sequence information, and described sequence information is pointed out wherein ' 1 ' to be positioned at the position of the row of the corresponding row group of described parity check matrix.