CN103137671B - Multi-grid field effect transistor and manufacturing method thereof - Google Patents
Multi-grid field effect transistor and manufacturing method thereof Download PDFInfo
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- CN103137671B CN103137671B CN201110397366.3A CN201110397366A CN103137671B CN 103137671 B CN103137671 B CN 103137671B CN 201110397366 A CN201110397366 A CN 201110397366A CN 103137671 B CN103137671 B CN 103137671B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 98
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 98
- 239000010703 silicon Substances 0.000 claims abstract description 98
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 71
- 230000005669 field effect Effects 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 36
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 19
- 238000000059 patterning Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 3
- 229910000078 germane Inorganic materials 0.000 claims description 3
- 229910000077 silane Inorganic materials 0.000 claims description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 3
- 239000010409 thin film Substances 0.000 abstract 2
- 230000005012 migration Effects 0.000 abstract 1
- 238000013508 migration Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a multi-grid field effect transistor and a manufacturing method thereof. A fin-shaped structure of the multi-grid field effect transistor comprises a silicon layer and silicon-germanium layers which are placed on the upper surface and the side wall of the silicon layer. Due to the fact that the silicon-germanium layers are placed on the upper surface and the side wall of the silicon layer, a plurality of faces of the silicon layer is wrapped by the silicon-germanium layers, good stress effect on the silicon layer can be generated, migration rate of a channel zone in the fin-shaped structure is improved, and performance of the multi-grid field effect transistor is further improved. Meanwhile, aiming at the structure of the multi-grid field effect transistor, according to the manufacturing method, the characteristic that a first silicon-germanium thin-film is selectively deposited on the silicon layer and the characteristic that a second silicon-germanium thin-film can achieve epitaxial growth selectively are used, a structure that the silicon-germanium layers are placed on the upper surface and the side wall of the silicon layer and the plurality of faces of the silicon layer are wrapped is formed, technological processes are simplified, impurity introducing is lowered, and the performance of the multi-grid field effect transistor is further improved.
Description
Technical field
The present invention relates to a kind of semiconductor technology device and manufacture method thereof, particularly a kind of multiple gate field effect transistor and manufacture method thereof.
Background technology
Mos field effect transistor (MOSFET) is constantly to the trend development of minification in recent years, this is to gather way, improving Components integration degree and the cost reducing integrated circuit, transistor scales ground reduce, transistor reduce the limit reaching various performance.Wherein the thickness of gate oxide and source/drain junction depth all reach the limit.
Therefore, industry have developed multi gate fet (Multi-Gate Transistors), and multiple gate field effect transistor technology is a kind of novel circuit configuration technology.Conventional transistor be each transistor only have grid be used for controlling electric current between two construction units by or interrupt, and then formed calculate in required " 0 " and " 1 ".And multiple-gate transistor technology is each transistor two or three grid, thus improve the ability of transistor controls electric current, i.e. computing capability, and significantly reduce power consumption, decrease the mutual interference between electric current.Wherein, multiple gate field effect transistor is a kind of device architecture be incorporated into by more than one grid in the MOSFET of individual devices, this means, raceway groove is on multiple surfaces by several gate wraps, thus leakage current when can suppress " cut-off " state more, and the drive current that can strengthen under " conducting " state, so just obtain the device architecture of lower power consumption and performance enhancement.
J.P.Colinge is called in the Americana of " FinFETs and other Multi-Gate Transistors " one section of name and describes polytype multiple gate field effect transistor, comprise double-gated transistor (Double-Gate, FinFET), tri-gate transistors (Tri-Gate), ohm-shaped gate transistor (Ω-Gate) and quadrangle gate transistor (Quad-Gate) etc.
Wherein, for double-gated transistor, double-gated transistor employs two grids to control raceway groove, greatly inhibits short-channel effect.A concrete distortion of double-gated transistor is exactly fin transistor (FinFET), described FinFET comprises vertical fin structure and across the grid in described fin structure side, be respectively source electrode and drain electrode at the both ends of the fin structure of grid both sides, in the fin structure under grid, form raceway groove.As nonplanar device, the size of the fin structure of FinFET determines the length of effective channel of transistor device.FinFET is compacter compared with the MOS transistor of conventional plane, can realize higher transistor density and less overall microelectric technique.In addition, tri-gate transistors is another Common Shape of multiple-gate transistor, and wherein said grid, across at the side of described fin structure and top surface, controls raceway groove to form three, improves the overall performance of device further.
The vertical direction height of fin structure and horizontal direction width and length have tremendous influence to the performance of drive current, short-channel effect and leakage current etc.The fin structure that such as vertical direction height is higher provides higher drive current, the fin structure that horizontal direction width is less can suppress leakage current better, but, because size constantly reduces, fin structure vertical direction height reduces gradually, in device, the mobility of raceway groove can decrease, then the drive current of device can be affected.Therefore, how by a kind of structure and manufacture method thereof of new multiple gate field effect transistor, the mobility improving multiple gate field effect transistor becomes the problem that industry is urgently studied.
Summary of the invention
The object of this invention is to provide a kind of structure of multiple gate field effect transistor, and propose a kind of manufacture method of multiple gate field effect transistor for this structure, to improve the mobility of multiple gate field effect transistor.
For solving the problem, a kind of multiple gate field effect transistor of the present invention, comprising: a fin structure, be positioned on a base material, described fin structure has zone line; Gate dielectric, on the upper surface and sidewall of the zone line of described fin structure; Gate electrode, is positioned on described gate dielectric; Wherein, described fin structure comprises silicon layer and germanium-silicon layer, on the upper surface that described germanium-silicon layer is positioned at described silicon layer and sidewall.
Further, described base material comprises Semiconductor substrate and is positioned at the bottom oxide silicon layer in described Semiconductor substrate.
Further, the height of described fin structure is 30nm ~ 100nm, and the width of described fin structure is 10nm ~ 25nm.
Further, the height of described silicon layer is 20nm ~ 70nm, and the width of described silicon layer is 7nm ~ 15nm.
The present invention also provides a kind of manufacture method of multiple gate field effect transistor, comprises the following steps:
One base material is provided, forms silicon layer film and silicon nitride layer successively on the substrate;
Silicon nitride layer described in patterning, and with the silicon nitride layer of patterning for mask, the silicon layer film of etched portions thickness, forms the first groove;
Form the first germanium-silicon film in the trench;
With described first germanium-silicon film for mask, etching removes silicon nitride layer and the part silicon layer film of described patterning, and form silicon layer, described silicon layer is positioned at below described first germanium-silicon film;
Form the second germanium-silicon film at the sidewall of described silicon layer, described first germanium-silicon film and the second germanium-silicon film form germanium-silicon layer, and described silicon layer and described germanium-silicon layer form fin structure;
The surface and sidewall of the zone line of described fin structure form gate dielectric and gate electrode.
Further, described base material comprises Semiconductor substrate and is positioned at the bottom oxide silicon layer in described Semiconductor substrate.
Further, described first germanium-silicon film adopts superpiezochemistry vapour deposition process to be formed, and reacting gas comprises silane, germane and argon gas.
Further, silicon nitride layer described in wet etching and silicon layer film.
Further, the material of described silicon layer film is etched for alkalescence.
Further, at the described silicon nitride layer of etching and silicon layer film, formed in the step of described silicon layer, the level of described silicon layer is less than the horizontal width of described first germanium-silicon film to width.
Further, epitaxial growth method is adopted to form the second germanium-silicon film.
Further, the height of described fin structure is 30nm ~ 100nm, and the width of described fin structure is 10nm ~ 25nm.
Further, the height of described silicon layer is 20nm ~ 70nm, and the width of described silicon layer is 7nm ~ 15nm.
Compared to prior art, the fin structure of multiple gate field effect transistor of the present invention comprises silicon layer and germanium-silicon layer, on the upper surface that described germanium-silicon layer is positioned at described silicon layer and sidewall, because germanium-silicon layer is positioned at upper surface and the side of silicon layer, multiple are all wrapped up described silicon layer, therefore preferably effect of stress can be produced to silicon layer, improve the mobility of channel region in fin structure, further increase the performance of multi gate fet.
Simultaneously, for the structure of above-mentioned multiple gate field effect transistor, disclosed manufacture method utilizes the characteristic of the first germanium-silicon film selectivity deposition on silicon layer, and second germanium-silicon film can the characteristic of selective epitaxial growth, define upper surface and side that germanium-silicon layer is positioned at silicon layer, multiple structures of all wrapping up described silicon layer, and eliminate a step chemical mechanical milling tech, Simplified flowsheet step also reduces impurity introducing, improves the performance of multiple gate field effect transistor further.
Accompanying drawing explanation
Fig. 1 is the perspective view of multiple gate field effect transistor in one embodiment of the invention.
Fig. 2 is the flow chart of the manufacture method of multiple gate field effect transistor in one embodiment of the invention.
Fig. 3 a ~ Fig. 3 f is the manufacturing process schematic diagram of the multiple gate field effect transistor along X-direction in Fig. 1.
Fig. 4 a ~ Fig. 4 d is the manufacturing process schematic diagram of the multiple gate field effect transistor along Y-direction in Fig. 1.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
Fig. 1 is the perspective view of multiple gate field effect transistor in one embodiment of the invention.As shown in Figure 1, the invention provides a kind of multiple gate field effect transistor, comprise a base material 101, fin structure 105, gate dielectric 107 and gate electrode 106.
Wherein, described base material 101 can be silicon materials or silicon germanium material, and in preferred embodiment, described base material 101 comprises Semiconductor substrate 101a and is positioned at the bottom oxide Si layer structure 101b on described Semiconductor substrate 101a.Described fin structure 105 is formed on described base material 101, described fin structure 105 has zone line, on the upper surface that gate dielectric 107 is across the zone line of described fin structure 105 and sidewall, in described zone line, be formed with channel region (not indicating in figure); Gate electrode 106 is positioned on described gate dielectric 107.
Key of the present invention is, described fin structure 105 comprises silicon layer 103 and germanium-silicon layer 104, on the upper surface that described germanium-silicon layer 104 is positioned at described silicon layer 103 and sidewall, because germanium-silicon layer 104 can produce effect of stress, and germanium-silicon layer 104 is positioned at the upper surface of silicon layer 103 and multiple of side, wrap up described silicon layer 103, therefore preferably effect of stress can be produced to silicon layer 103, thus improve the mobility of channel region in fin structure 105, thus improve the performance of multi gate fet further.
In preferred embodiment, the height of described fin structure 105 is 30nm ~ 100nm, and the width of described fin structure 105 is 10nm ~ 25nm; Wherein, the height of described silicon layer 103 is 20nm ~ 70nm, and the width of described silicon layer is 7nm ~ 15nm.Fin structure in the size range of above-mentioned height and width has good drive current performance, and can suppress short-channel effect and leakage current.
Fig. 2 is the flow chart of the manufacture method of multiple gate field effect transistor in one embodiment of the invention.As shown in Figure 2, the invention provides a kind of manufacture method of multiple gate field effect transistor, comprise the following steps:
Step S01: provide a base material, forms silicon layer film and silicon nitride layer on the substrate successively;
Step S02: silicon nitride layer described in patterning, with the silicon nitride layer of patterning for mask, the silicon layer film of etched portions thickness, forms groove;
Step S03: form the first germanium-silicon film in the trench;
Step S04: with described first germanium-silicon film for mask, etching removes the silicon nitride layer of described patterning and the silicon layer film of below thereof, and form silicon layer, described silicon layer is positioned at below described first germanium-silicon film;
Step S05: form the second germanium-silicon film at the sidewall of described silicon layer, described first germanium-silicon film and the second germanium-silicon film form germanium-silicon layer, and described silicon layer and described germanium-silicon layer form fin structure;
Step S06: form gate dielectric and gate electrode on the surface and sidewall of the zone line of described fin structure.
Fig. 3 a ~ Fig. 3 f is the manufacturing process schematic diagram of the multiple gate field effect transistor along X-direction in Fig. 1, Fig. 4 a ~ Fig. 4 d is the manufacturing process schematic diagram of the multiple gate field effect transistor along Y-direction in Fig. 1, below in conjunction with above-mentioned accompanying drawing, describe the manufacture method of multiple gate field effect transistor in an embodiment in detail.
The manufacture method of the multiple gate field effect transistor described in one embodiment of the invention, comprises the following steps:
Step S01: as shown in Fig. 3 a and Fig. 4 a, one base material 101 is provided, in preferred embodiment, described base material 101 comprises semi-conductive substrate 101a, and in this Semiconductor substrate, depositing the bottom oxide silicon layer 101b of formation, described bottom oxide silicon layer 101b can adopt thermal oxidation method or chemical vapour deposition technique to be formed.Then, described base material 101 forms silicon layer film 103a and silicon nitride layer 102 successively; Described silicon layer film 103a can adopt chemical vapour deposition (CVD) or physical vaporous deposition to be formed, described silicon nitride layer 102 can adopt chemical vapour deposition technique to be formed, the thickness of described silicon layer film 103a can be 25nm ~ 80nm, the thickness of described silicon nitride layer 102 can be 2nm ~ 20nm, certainly can also select the thickness of silicon layer film 103a and silicon nitride layer 102a according to process conditions and device performance.
Step S02: silicon nitride layer 102 described in patterning, forms the silicon nitride layer 102a of patterning, and with the silicon nitride layer 102a of patterning for mask, the silicon layer film 103a of etched portions thickness, forms groove 200 as shown in Figure 3 b, detailed, in this step, first, described silicon nitride layer 102 surface-coated photoresist (not indicating in figure), by exposure, development forms the photoresist layer of patterning, with the photoresist layer of this patterning for mask, silicon nitride layer 102 described in the wet etching utilizing such as phosphoric acid, to form the silicon nitride layer 102a of patterning, again with the silicon nitride layer 102a of described patterning for mask, alkaline matter (such as ammoniacal liquor) is utilized to carry out the silicon layer film 103a of wet etching removal segment thickness, by controlling etch period, etching is made to remove part silicon layer film 103a, retain the silicon layer film 103a segment thickness being positioned at the first beneath trenches 200, the thickness of the silicon layer film 103a retained is determined according to the thickness of follow-up formation silicon layer.
Step S03: as shown in Figure 3 c, forms the first germanium-silicon film 104a in described groove 200; Described first germanium-silicon film 104a can adopt superpiezochemistry vapour deposition process to be formed, reacting gas comprises silane, germane and argon gas, formation due to the first germanium-silicon film 104a needs to be formed on silicon layer film 103a, therefore the process forming described first germanium-silicon film 104a is selectivity deposition, only in the first groove 200, form the first germanium-silicon film 104a, eliminate the technique of a step cmp, save the process time, and decrease the residual contamination of chemical mechanical planarization process generation.
Step S04: with described first germanium-silicon film 104a for mask, etching removes silicon nitride layer 102a and the part silicon layer film 103a of described patterning, form the silicon layer 103 as shown in Fig. 3 d and Fig. 4 b, described silicon layer 103 is positioned at below described first germanium-silicon film 104a, adopt silicon nitride layer 102a and the silicon layer film 103a of patterning described in wet etching, in etching process, can the silicon nitride layer 102a of patterning described in wet etching, utilize the wet etching material of alkalescence, such as Nitrogen trifluoride and ammonia mixture etch, because of the character that the isotropic of wet etching etches, part silicon layer film 103a below described first germanium-silicon film 104a can be returned etching and be removed, form " T " word structure, namely the level of described silicon layer 103 is less than the horizontal width of described first germanium-silicon film 104a to width, wherein, the scope of horizontal width difference T can be 1nm ~ 5nm.
Step S05: as shown in Fig. 3 e and Fig. 4 c, the second germanium-silicon film 104b is formed at the sidewall of described silicon layer 103, described first germanium-silicon film 103a and the second germanium-silicon film 104b forms germanium-silicon layer 104 jointly, and described silicon layer 103 forms fin structure 105 with described germanium-silicon layer 104; Wherein, the height H of final described fin structure 105
1for 30nm ~ 100nm, the width L of described fin structure 105
1for 10nm ~ 25nm.Second germanium-silicon film 104b adopts epitaxial growth method to be formed, containing in the atmosphere of germanium, in silicon layer 103, silicon self can form SiGe, due to when forming silicon layer 103, the level of described silicon layer 103 is less than the first germanium-silicon film 104a to width, form a kind of " T " word structure, the sidewall of silicon layer 103 is exposed in germanium atmosphere, thus on the sidewall of silicon layer 103, form the second germanium-silicon film 104b.The height H of described silicon layer 103
2for 20nm ~ 70nm, the width L of described silicon layer
2for 7nm ~ 15nm.
Step S06: as shown in Fig. 3 f and Fig. 4 d, the surface and sidewall of the zone line of described fin structure 105 form gate dielectric 107 and gate electrode 106.The material of described gate dielectric layer 107 can be a kind of in oxide layer, nitration case or its combination, and the material of described gate electrode 106 can be polysilicon layer, the technological means that its forming process is well known to those skilled in the art, therefore repeats no more.
In sum, compared to prior art, the fin structure of multiple gate field effect transistor of the present invention comprises silicon layer 103 and germanium-silicon layer 104, on the upper surface that described germanium-silicon layer 104 is positioned at described silicon layer 103 and sidewall, because germanium-silicon layer 104 is positioned at the upper surface of silicon layer 103 and multiple of side, wrap up described silicon layer 103, therefore preferably effect of stress can be produced to silicon layer 103, thus improve the mobility of channel region in fin structure 105, thus improve the performance of multi gate fet further.
Simultaneously, structure for above-mentioned multiple gate field effect transistor provides a kind of manufacture method, the method utilizes the characteristic of the first germanium-silicon film 104a selectivity deposition on silicon layer 103 and the second germanium-silicon film 104b can the characteristic of selective epitaxial growth, avoid a step chemical mechanical milling tech, Simplified flowsheet also reduces impurity introducing, improves the performance of multiple gate field effect transistor further.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (8)
1. a manufacture method for multiple gate field effect transistor, comprises
One base material is provided, forms silicon layer film and silicon nitride layer successively on the substrate;
Silicon nitride layer described in patterning, and with the silicon nitride layer of patterning for mask, the silicon layer film of etched portions thickness, forms groove;
Form the first germanium-silicon film in the trench;
With described first germanium-silicon film for mask, etching removes the silicon nitride layer of described patterning and the silicon layer film of below thereof, and form silicon layer, described silicon layer is positioned at below described first germanium-silicon film;
Form the second germanium-silicon film at the sidewall of described silicon layer, described first germanium-silicon film and described second germanium-silicon film form germanium-silicon layer, and described silicon layer and described germanium-silicon layer form fin structure;
The surface and sidewall of the zone line of described fin structure form gate dielectric and gate electrode.
2. the manufacture method of multiple gate field effect transistor as claimed in claim 1, it is characterized in that, described base material comprises Semiconductor substrate and is positioned at the bottom oxide silicon layer in described Semiconductor substrate.
3. the manufacture method of multiple gate field effect transistor as claimed in claim 1, is characterized in that, described first germanium-silicon film adopts superpiezochemistry vapour deposition process to be formed, and reacting gas comprises silane, germane and argon gas.
4. the manufacture method of multiple gate field effect transistor as claimed in claim 1, is characterized in that, silicon nitride layer described in wet etching and silicon layer film.
5. the manufacture method of multiple gate field effect transistor as claimed in claim 1, it is characterized in that, formed in the step of described silicon layer, the level of described silicon layer is less than the horizontal width of described first germanium-silicon film to width.
6. the manufacture method of multiple gate field effect transistor as claimed in claim 1, is characterized in that, adopts epitaxial growth method to form the second germanium-silicon film.
7. as the manufacture method of the multiple gate field effect transistor in claim 1 to 6 as described in any one, it is characterized in that, the height of described fin structure is 30nm ~ 100nm, and the width of described fin structure is 10nm ~ 25nm.
8. the manufacture method of multiple gate field effect transistor as claimed in claim 7, it is characterized in that, the height of described silicon layer is 20nm ~ 70nm, and the width of described silicon layer is 7nm ~ 15nm.
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| CN201110397366.3A CN103137671B (en) | 2011-12-02 | 2011-12-02 | Multi-grid field effect transistor and manufacturing method thereof |
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| CN201110397366.3A CN103137671B (en) | 2011-12-02 | 2011-12-02 | Multi-grid field effect transistor and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6800910B2 (en) * | 2002-09-30 | 2004-10-05 | Advanced Micro Devices, Inc. | FinFET device incorporating strained silicon in the channel region |
| CN1622336A (en) * | 2003-11-24 | 2005-06-01 | 三星电子株式会社 | Non-planar transistor having germanium channel region and method of manufacturing the same |
| US6921982B2 (en) * | 2003-07-21 | 2005-07-26 | International Business Machines Corporation | FET channel having a strained lattice structure along multiple surfaces |
| CN1742375A (en) * | 2003-01-23 | 2006-03-01 | 先进微装置公司 | Strained channel FinFET |
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| US7193279B2 (en) * | 2005-01-18 | 2007-03-20 | Intel Corporation | Non-planar MOS structure with a strained channel region |
| WO2008039495A1 (en) * | 2006-09-27 | 2008-04-03 | Amberwave Systems Corporation | Tri-gate field-effect transistors formed by aspect ratio trapping |
| US20090001415A1 (en) * | 2007-06-30 | 2009-01-01 | Nick Lindert | Multi-gate transistor with strained body |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6800910B2 (en) * | 2002-09-30 | 2004-10-05 | Advanced Micro Devices, Inc. | FinFET device incorporating strained silicon in the channel region |
| CN1742375A (en) * | 2003-01-23 | 2006-03-01 | 先进微装置公司 | Strained channel FinFET |
| US6921982B2 (en) * | 2003-07-21 | 2005-07-26 | International Business Machines Corporation | FET channel having a strained lattice structure along multiple surfaces |
| CN1622336A (en) * | 2003-11-24 | 2005-06-01 | 三星电子株式会社 | Non-planar transistor having germanium channel region and method of manufacturing the same |
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