CN103137659B - Memory element and manufacturing method thereof - Google Patents

Abstract

The invention relates to a memory element and a manufacturing method thereof. The memory device includes a gate, a gate dielectric layer and two charge storage layers. The grid is positioned on the substrate. The gate dielectric layer is located between the gate and the substrate. The width of the gate dielectric layer is smaller than that of the gate, and a gap is formed on two sides of the gate dielectric layer, below the gate and above the substrate. Each charge storage layer comprises a main body part, a first extension part and a second extension part. Each body portion is located in each void. Each first extension part is connected with each main body part and protrudes out of the side wall of each grid. Each second extension part is connected with each corresponding first extension part and extends upwards to the side wall of the grid electrode, wherein the edge area of each first extension part protrudes out of the side wall of the corresponding second extension part. The invention can provide a positioned charge storage area, so that the charge can be completely positioned and stored, the second bit effect is reduced, the program interference behavior is reduced, and the short channel effect can be reduced. The invention also provides a manufacturing method of the memory element.

Description

Memory element and manufacturing method thereof

technical field

The invention relates to an integrated circuit and its manufacturing method, in particular to a memory element and its manufacturing method.

Background technique

Memory is a semiconductor device used to store information or data. As computer microprocessors become more powerful, the programs and operations performed by the software also increase. Therefore, the demand for high-capacity memory is gradually increasing.

Among various memory products, non-volatile memory allows data to be programmed, read and erased multiple times, and the data stored in it can be preserved even after the memory's power supply is interrupted. Due to these advantages, non-volatile memory has become a widely used memory in personal computers and electronic equipment.

Well-known electrically programmable and erasable (electrically programmable and erasable) non-volatile memory technologies using charge storage structures, such as electronically erasable programmable read-only memory (EEPROM) and flash memory (flash memory) , have been used in various modern applications. Flash memory is designed in the form of an array of memory cells that can be programmed and read independently. A typical flash memory cell stores charge in a floating gate. Another type of flash memory uses a non-conductive material to form a charge-trapping structure, such as silicon nitride, to replace the conductive material of the floating gate. When a charge-trapping memory cell is programmed, charges are trapped and do not move through the nonconductive charge-trapping structure. In the absence of continuous power supply, the charge will remain in the charge trapping layer, maintaining its data state until the memory cell is erased. Charge trapping memory cells can be operated as two-sided cells. That is, since the charges do not move through the nonconductive charge trapping layer, the charges can be located at different charge traps. In other words, in the charge-trapping flash memory device, more than one bit of information can be stored in each memory cell.

Any memory cell can be programmed to store two completely separate bits in the charge trapping structure (in such a way that charges are concentrated near the source and drain regions, respectively). Memory cells can be programmed using channel hot electron injection, which generates hot electrons in the channel region. Hot electrons gain energy and are trapped in charge trapping structures. By reversing the applied bias voltages at the source and drain terminals, charge can be trapped to either part of the charge trapping structure (near the source region, near the drain region, or both).

Typically, a memory cell with a charge trapping structure can store four different bit combinations (00, 01, 10, and 11), each with a corresponding threshold voltage. During a read operation, the current flowing through the memory cell varies depending on the starting voltage of the memory cell. Typically, this current can have four different values, each of which corresponds to a different starting voltage. Therefore, by detecting this current, the bit combination stored in the memory cell can be determined.

The entire effective charge range or threshold voltage range can be classified as a memory operation window. In other words, the memory operating margin is defined by the difference between the program level (level) and the erase level. Since memory cell operations require good level separation between various states, large memory operating margins are required. However, the performance of 2-bit memory cells usually decreases with the so-called "second bit effect". Under the second-bit effect, the localized charges in the charge-trapping structure interact with each other. For example, during reverse read, a read bias is applied to the drain terminal and the charge stored near the source region (ie, the first bit) is detected. However, the bit near the drain region (ie, the second bit) then creates a potential barrier to read the first bit near the source region. This barrier can be overcome by applying an appropriate bias voltage, using the drain-induced barrier lowering (DIBL) effect to suppress the effect of the second bit near the drain region and allow detection of the storage state of the first bit. However, when the second bit near the drain region is programmed to a high threshold voltage state and the first bit near the source region is in an unprogrammed state, the second bit substantially raises the energy barrier. Therefore, as the threshold voltage for the second bit increases, the read bias voltage of the first bit is not enough to overcome the potential barrier generated by the second bit. Therefore, since the threshold voltage of the second bit is increased, the threshold voltage of the first bit is increased, thereby reducing the operating margin of the memory. The second bit effect reduces the operating margin of the binary memory.

It can be seen that the above-mentioned existing memory element and its manufacturing method obviously still have inconveniences and defects in product structure, manufacturing method and use, and need to be further improved urgently. In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and there is no suitable structure and method for general products and methods to solve the above-mentioned problems. This is obviously a problem that relevant industry players are eager to solve. Therefore, how to create a new memory element and its manufacturing method to suppress the second bit effect in the memory element is one of the current important research and development issues, and has become a goal that the industry needs to improve.

Contents of the invention

The purpose of the present invention is to overcome the defects of the existing memory elements and provide a new memory element. The technical problem to be solved is to provide a positioned charge storage area so that the charges can be completely positioned and stored. It can reduce the second bit effect, reduce the behavior of programming disturbance, and can reduce the short channel effect, which is very suitable for practical use.

Another object of the present invention is to overcome the defects of the existing memory element manufacturing method and provide a new memory element manufacturing method. The technical problem to be solved is to make the manufactured memory element The memory element can provide a positioned charge storage area, so that the charge can be completely positioned and stored, and a better second bit can be obtained, the behavior of program disturbance can be reduced, and the short channel effect can be reduced, so it is more suitable for practical use.

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. A memory device according to the present invention includes a gate, a gate dielectric layer and two charge storage layers. The gate is on the substrate. The gate dielectric layer is located between the gate and the substrate. There is a gap on both sides of the gate dielectric layer, below the gate and above the substrate. Each charge storage layer includes a main body, a first extension and a second extension. Each main body portion is located in each of the above-mentioned gaps. Each first extension part is connected to the main body part and protrudes from the sidewall of the gate. Each second extension part is connected with the corresponding first extension part and extends upward to the sidewall of the gate, wherein the edge region of each first extension part protrudes from the corresponding second extension part side wall.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned memory element, the materials of the main body, the first extension and the second extension are the same.

The aforementioned memory element further includes two doped regions located in the substrate on both sides of the gate, wherein the first extension and the second extension of each charge storage layer are located above the corresponding doped regions.

The aforementioned memory element further includes two liners and two spacers. The above two lining layers are respectively located between the gate and the second extension part of each charge storage layer. The two spacers are located above the first extension, and respectively sandwich the second extension between the corresponding liner and the spacer.

In the aforementioned memory element, the ratio of the length of the main body portion to the length of the first extension portion is 2:1 to 5:1.

The purpose of the present invention and the solution to its technical problem also adopt the following technical solutions to achieve. A memory device according to the present invention includes a gate, a gate dielectric layer, two charge storage layers and two lining layers. The gate is on the substrate. The gate dielectric layer is located between the gate and the substrate. There is a gap on both sides of the gate dielectric layer, below the gate and above the substrate. Each of the above-mentioned charge storage layers includes a main body portion and an extension portion. Each main body part is located in the above-mentioned gap. Each extension part is connected to the main body part and protrudes from the sidewall of the gate. Each lining layer is located on the sidewall of the gate, and the edge region of the extension part of each charge storage layer protrudes from the sidewall of the lining layer.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned memory element, the materials of the main body and the extension are the same.

The aforementioned memory element further includes two doped regions located in the substrate on both sides of the gate, wherein the extensions of the charge storage layers extend above the corresponding doped regions.

In the aforementioned memory element, the ratio of the length of the main body part to the length of the extension part is 2:1 to 5:1.

The purpose of the present invention and the solution to its technical problem are realized by adopting the following technical solutions again. A memory device according to the present invention includes a gate, a gate dielectric layer, two charge storage layers and two doped regions. The gate is on the substrate. The gate dielectric layer is located between the gate and the substrate. There is a gap on both sides of the gate dielectric layer, below the gate and above the substrate. Each of the above-mentioned charge storage layers includes a main body portion and an extension portion. Each main body part is located in the above-mentioned gap. Each extension portion is connected to the main body portion and protrudes from the sidewall of the gate. Each doped region is located in the substrate on both sides of the gate, and the extension of each charge storage layer extends above the corresponding doped region.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned memory element, the materials of the main body and the extension are the same.

In the aforementioned memory element, the ratio of the length of the main body part to the length of the extension part is 2:1 to 5:1.

The purpose of the present invention and the solution to its technical problems are realized by adopting the following technical solutions again. A method for manufacturing a memory element according to the present invention includes: forming a gate dielectric layer on a substrate and a gate located on the gate dielectric layer, wherein a gate dielectric layer is formed on both sides of the gate dielectric layer, below the gate and above the substrate. a gap. Then two charge storage layers are formed. Each charge storage layer includes a main body and a first extension, wherein each main body is located in the gap, and each first extension is connected to each main body and protrudes from the sidewall of the gate. Two doped regions are formed in the substrate on both sides of the gate, and the first extensions of each charge storage layer extend above the corresponding doped regions.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

The manufacturing method of the aforementioned memory element, wherein each charge storage layer further includes a second extension, each second extension is connected to the first extension, and extends upward to the sidewall of the gate, wherein the edge of the first extension The regions protrude beyond the sidewalls of the corresponding second extensions.

In the aforementioned manufacturing method of the memory element, the first extension portion and the second extension portion of each charge storage layer are located above the corresponding doped region.

The aforementioned manufacturing method of the memory element, wherein before forming the above-mentioned charge storage layer, it also includes forming a lining material layer to cover the surface of the above-mentioned substrate, the sidewall of the gate dielectric layer, the bottom, the sidewall and the upper surface of the gate, Edge regions of the first extensions of the above-mentioned charge storage layers protrude from the lining material layer located on the sidewall of the gate.

The manufacturing method of the aforementioned memory element, wherein the step of forming the charge storage layers includes: forming a charge storage material layer covering the above-mentioned liner material layer and filling the above-mentioned gaps, and then forming a spacer material layer to cover the above-mentioned charge storage material layer . Afterwards, the lining material layer, the charge storage material layer and the spacer material layer are removed by anisotropic etching to expose the surface of the gate and the substrate, leaving the liner layer, charge storage layer and two spacers.

The aforementioned manufacturing method of the memory device further includes forming a liner on the sidewall of the gate, wherein the first extensions of the charge storage layers protrude from the sidewall of the liner.

Compared with the prior art, the present invention has obvious advantages and beneficial effects. By virtue of the above technical solutions, the memory element and its manufacturing method of the present invention have at least the following advantages and beneficial effects:

The memory element of the present invention can provide a localized charge storage area, so that the charge can be completely localized and stored, reduce the second bit effect, reduce the behavior of programming disturbance, and can reduce the short channel effect.

The manufacturing method of the memory element of the present invention can make the manufactured memory element provide a positioned charge storage area through a simple process, so that the charge can be completely positioned and stored, a better second bit can be obtained, and the behavior of program disturbance can be reduced , and can reduce the short channel effect.

In summary, the present invention relates to a memory device and its manufacturing method. The memory device includes a gate, a gate dielectric layer and two charge storage layers. The gate is on the substrate. The gate dielectric layer is located between the gate and the substrate. The width of the gate dielectric layer is smaller than that of the gate, and a gap is formed on both sides of the gate dielectric layer, below the gate and above the substrate. Each charge storage layer includes a main body, a first extension and a second extension. Each main body portion is located in each of the above-mentioned gaps. Each first extension part is connected with each main body part and protrudes from the sidewall of each gate. Each second extension part is connected with each corresponding first extension part, and extends upward to the sidewall of the gate, wherein the edge region of the first extension part protrudes from the sidewall of the corresponding second extension part. Therefore, the present invention can provide a localized charge storage area, so that the electric charge can be completely localized and stored, reduce the second bit effect, reduce the program disturbance behavior, and can reduce the short channel effect. The invention also provides a manufacturing method of the memory element. The present invention has significant progress in technology, and has obvious positive effects, and is a novel, progressive and practical new design.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

1 to 7 are schematic cross-sectional views of a manufacturing method of a memory device according to an embodiment of the present invention.

FIG. 8 is a graph showing the relationship between programming speed and drain bias voltage when three different memory elements are programmed.

FIG. 9 is a schematic cross-sectional view of a conventional memory element.

FIG. 10 is a schematic cross-sectional view of another conventional memory element.

10: substrate 12: gate dielectric layer

14: gate conductor layer 14a: gate

16: Patterned hard mask layer 18: Patterned mask layer

20: Groove 20a: Void

22: lining material layer 22a: first part/tunneling dielectric layer

22b: second part/top dielectric layer 22c: third part/liner layer

24': charge storage material layer 24: charge storage layer

24a: main body part 24b: first extension part

24c: second extension 26: spacer material layer

26a: spacers 28, 30: doped regions

32: dielectric layer 34: word line

L1, L2: length 100, 200, 300: curve

detailed description

In order to further illustrate the technical means and effects that the present invention adopts to achieve the intended purpose of the invention, below in conjunction with the accompanying drawings and preferred embodiments, the specific implementation, structure, method, Steps, features and effects thereof are described in detail below.

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the drawings. Through the description of the specific implementation, it should be possible to obtain a deeper and more specific understanding of the technical means and effects of the present invention to achieve the intended purpose, but the attached drawings are only for reference and description, not for the purpose of the present invention. be restricted.

1 to 7 are schematic cross-sectional views of a manufacturing method of a memory device according to an embodiment of the present invention.

Referring to FIG. 1 , the manufacturing method of the memory element of the present invention is to form a gate dielectric layer 12 on a substrate 10 , and then form a gate conductor layer 14 on the gate dielectric layer 12 . The material of the substrate 10 is, for example, semiconductor, such as silicon, or silicon on insulating layer (SOI). The material of the substrate 10 can also be other compound semiconductors. The material of the gate dielectric layer 12 is, for example, silicon oxide, or other suitable materials for making the gate dielectric layer. The gate dielectric layer 12 is formed by thermal oxidation, chemical vapor deposition, or other suitable methods, for example. The material of the gate conductor layer 14 is, for example, doped polysilicon. The gate conductor layer 14 is formed by, for example, forming an undoped polysilicon layer by chemical vapor deposition, and then performing ion implantation. The method for forming the gate conductor layer 14 may also be to form a polysilicon layer by chemical vapor deposition and perform doping on site. Afterwards, a patterned hard mask layer 16 and a patterned mask layer 18 are formed on the gate conductor layer 14 . The material of the patterned hard mask layer 16 is, for example, APF, and the forming method is, for example, chemical vapor deposition. The material of the patterned mask layer 18 is, for example, photoresist. The pattern of the mask layer 18 can be formed through exposure and development. The pattern of the hard mask layer 16 can be formed by transferring the pattern of the mask layer 18 downward through an etching process.

Afterwards, as shown in FIG. 2 , the mask layer 18 and the hard mask layer 16 are used as masks, and the substrate 10 is used as an etch stop layer, and an etching process is performed to pattern the gate conductor layer 14 into a gate 14a, and Continue to pattern the gate dielectric layer 12 . The etching process used is, for example, an anisotropic etching process. The anisotropic etching process is, for example, a plasma etching process. Afterwards, the patterned mask layer 18 and the hard mask layer 16 are removed.

Thereafter, as shown in FIG. 3, an isotropic etching process is performed on the gate dielectric layer 12 to remove part of the gate dielectric layer 12, that is, an undercut is formed under the gate 14a to form a groove 20, The groove 20 is used as a local storage space.

Afterwards, as shown in FIG. 4 , a liner material layer 22 is formed to cover the top surface, sidewalls and bottom of the gate 14 a, the sidewalls of the gate dielectric layer 12 and the surface of the substrate 10 . In one embodiment, the liner material layer 22 conformally covers the top surface, sidewalls and bottom of the gate 14 a , the sidewalls of the gate dielectric layer 12 and the surface of the substrate 10 . The lining material layer 22 is filled in the groove 20 shown in FIG. 3 , but the groove 20 is not filled, leaving a gap 20a ( FIG. 4 ). The material of the lining material layer 22 is, for example, silicon oxide, and the formation method is, for example, thermal oxidation, in-situ steam generation (ISSG) oxidation, chemical vapor deposition (CVD), atomic layer deposition, or furnace tube oxidation.

Afterwards, as shown in FIG. 5 , a charge storage material layer 24' is formed to cover the upper surface, sidewalls and the surface of the lining material layer 22 above the substrate 10 and fill the gap 20a. The material of the charge storage material layer 24' is, for example, silicon nitride or doped polysilicon. The silicon nitride is formed by, for example, furnace tube deposition, chemical vapor deposition or atomic layer deposition. The method for forming doped polysilicon is, for example, to form a polysilicon layer by chemical vapor deposition and perform doping on site.

Afterwards, a spacer material layer 26 is formed on the charge storage material layer 24', covering the upper surface and sidewalls of the gate 14a and the charge storage material layer 24' above the substrate 10. In one embodiment, the spacer material layer 26 conforms to the top surface, sidewalls and the charge storage material layer 24' above the substrate 10 of the gate 14a. The material of the spacer material layer 26 is, for example, silicon oxide, and the forming method is, for example, furnace tube oxidation, chemical vapor deposition or high temperature thermal oxidation (HTO).

Afterwards, please refer to FIG. 6 , the spacer material layer 26 , the charge storage material layer 24 ′ and the liner material layer 22 are anisotropically etched to expose the surface of the gate 14 a and the substrate 10 . The remaining charge storage material layer 24' serves as the charge storage layer 24, which includes a main body portion 24a, a first extension portion 24b, and a second extension portion 24c. Each main body portion 24a is located in the gap 20a. The first extension portion 24b is connected to the main body portion 24a and protrudes from the sidewall of the gate 14a. The second extension portion 24c is located on the sidewall of the gate 14a, and extends downward to connect with the first extension portion 24b, so that the edge region of the first extension portion 24b protrudes from the corresponding sidewall of the second extension portion 24c.

The remaining liner material layer 22 comprises three portions 22a, 22b, 22c. The first portion 22a of the liner material layer 22 is located between the charge storage layer 24 and the substrate 10, serving as the tunneling dielectric layer 22a. The second portion 22b of the liner material layer 22 is located below the gate 14a, sandwiched between the gate 14a and the main portion 24a of the charge storage layer 24, and serves as the top dielectric layer 22b. The third portion 22c of the liner material layer 22 is located on the sidewall of the gate 14a, sandwiched between the gate 14a and the second extension 24c of the charge storage layer 24, and serves as the liner 22c. The remaining spacer material layer serves as a spacer 26a, located above the first extension 24b of the charge storage layer 24 and on the sidewall of the second extension 24c.

Ion implantation is then performed to form doped regions 28 and 30 in the substrate 10 . The dopants implanted in the doped regions 28 , 30 are of the same conductivity type and different from the conductivity type of the substrate 10 . In one embodiment, the substrate 10 is P-type doped; the doped regions 28 and 30 are N-type doped. In another embodiment, the substrate 10 is N-type doped; the doped regions 28 and 30 are P-type doped. The N-type dopant is, for example, phosphorus or arsenic; the P-type dopant is, for example, boron or boron difluoride. The doped regions 28, 30 can be used as source regions or drain regions of the memory. The doped regions 28 , 30 are located in the substrate 10 on both sides of the gate 14 a, wherein the first extension 24 b and the second extension 24 c of each charge storage layer 24 are located above the corresponding doped regions 28 , 30 .

Then, as shown in FIG. 7 , a dielectric layer 32 is formed on the substrate 10 . The dielectric layer 32 fills the gap between two adjacent gates 14a and has a flat surface, exposing the surface of the gates 14a. The material of the dielectric layer 32 is, for example, silicon oxide, and the method of forming it is, for example, using chemical vapor deposition to form a dielectric material layer, and then performing a planarization process. The planarization process is, for example, an etch-back process or a chemical mechanical polishing process (CMP).

Thereafter, word lines 34 are formed over dielectric layer 32 . The word line 34 is made of conductive material, which is electrically connected to the gate 14a. In one embodiment, the direction in which the word line 34 extends is different from the direction in which the doped regions 28 and 30 extend, for example, the two are substantially perpendicular. The method of forming the word line 34 is, for example, performing lithography and etching processes after forming the conductive material layer. The conductive material is, for example, doped polysilicon, metal, metal alloy or a combination thereof. The method for forming the doped polysilicon is, for example, to form the undoped polysilicon layer by chemical vapor deposition, and then perform ion implantation. The method for forming the doped polysilicon may also be to form a polysilicon layer by chemical vapor deposition and perform doping on site. The metal or metal alloy is formed by, for example, sputtering or chemical vapor deposition, or other suitable methods.

Referring to FIG. 7 , the memory device according to the embodiment of the present invention includes a gate 14 a, a gate dielectric layer 12 , two charge storage layers 24 , doped regions 28 , 30 and a word line 34 .

The gate 14a is located on the substrate 10 . The gate dielectric layer 12 is located between the gate 14 a and the substrate 10 . The width of the gate dielectric layer 12 is smaller than that of the gate 14 a , and there are gaps 20 a on both sides of the gate dielectric layer 12 , below the gate 14 a and above the substrate 10 .

The materials of the charge storage layer 24 and the gate dielectric layer 12 are different. Each charge storage layer 24 includes a main body portion 24a, a first extension portion 24b and a second extension portion 24c. Each body portion 24a is located in the void 20a. Each first extension portion 24b is connected to each main body portion 24a and protrudes from the sidewall of the gate 14a. Each second extension portion 24c is connected to the corresponding first extension portion 24b and extends upward to the sidewall of the gate 14a. In other words, the edge region of each first extension portion 24b protrudes from the sidewall of the corresponding second extension portion 24c, and its cross-section is an inverted T shape. If the length L1 of the main body 24a is too short, the programming efficiency will be limited. The longer the length L1 of the main body portion 24a is, the faster the programming speed is, but the influence of the second bit effect is greater. The longer the length of the first extension 24b is, the less it is controlled by the gate, so the influence of the second bit effect is smaller, but the programming speed can still be improved. The length L1 of the main body portion 24a is, for example, 50 angstroms to 150 angstroms; the length L2 of the first extension portion 24b is, for example, 10 angstroms to 75 angstroms. In one embodiment, the ratio of the length L1 of the main body portion 24 a to the length L2 of the first extension portion 24 b is about 2:1 to 5:1. The main body portion 24a, the first extension portion 24b and the second extension portion 24c are made of the same material.

The tunnel dielectric layer 22 a is located between the charge storage layer 24 and the substrate 10 . The top dielectric layer 22b is located below the gate 14a and sandwiched between the gate 14a and the main body 24a of the charge storage layer 24 . The liner 22c is located on the sidewall of the gate 14a and sandwiched between the gate 14a and the second extension 24c of the charge storage layer 24 . The spacer 26a is located above the first extension portion 24b of the charge storage layer 24 and on the sidewall of the second extension portion 24c. In one embodiment, the material of the tunneling dielectric layer 22 a , the top dielectric layer 22 b , the liner layer 22 c and the spacer 26 a is different from that of the charge storage layer 24 .

The conductivity type of the dopants in the doped regions 28 , 30 is different from the conductivity type of the substrate 10 . The doped regions 28 , 30 are located in the substrate 10 on both sides of the gate 14 a, and the first extension 24 b and the second extension 24 c of each charge storage layer 24 are located above the corresponding doped regions 28 , 30 . The dopants implanted in the doped regions 28 , 30 are of the same conductivity type and different from the conductivity type of the substrate 10 .

FIG. 8 is a graph showing the relationship between programming speed and drain bias voltage when three different memory elements are programmed.

Please refer to FIG. 8, the curve 100 shows the programming of the memory element according to the charge storage layer 24 (including the main body 24a, the first extension 24b and the second extension 24c, reverse T-shaped) according to the embodiment of the present invention shown in FIG. 7 the result of. The curve 200 is the programming result of a conventional memory element whose charge storage layer 24 only includes the main body 24a in FIG. 9 . The curve 300 is the programming result of a conventional L-shaped memory element whose charge storage layer 24 only includes the first extension 24 b and the second extension 24 c in FIG. 10 . The results of FIG. 8 show that the curve 100, when the same drain voltage is applied for programming, the charge storage layer is an inverted T-shaped memory element, which has a higher programming bit initial voltage change rate (dVt), namely Programming is faster. To sum up, the memory device of the present invention can provide a localized charge storage region, so that the charge can be stored in a localized manner, reduce the second bit effect, reduce the behavior of program disturb, and reduce the short channel effect. In addition, the manufacturing method of the memory element of the present invention has a simple process.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the method and technical content disclosed above to make some changes or modifications to equivalent embodiments with equivalent changes, but if they do not depart from the technical solution of the present invention, Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims (11)

1. A memory element, characterized in that it comprises: a gate located on a substrate; a gate dielectric layer between the gate and the substrate, with a gap on both sides of the gate dielectric layer, below the gate and above the substrate; and Two charge storage layers, each of which includes a main body, a first extension and a second extension, each of which is located in each of the gaps, each of the first extensions is connected to each of the main body and Protruding from the sidewall of the grid, each second extension is connected to the corresponding first extension, and extends upward to the sidewall of the grid, wherein the edge region of each first extension protrudes from the corresponding The sidewall of each of the second extension parts, and the ratio of the length of the main body part to the length of the first extension part is 2:1 to 5:1. 2. The memory device according to claim 1, further comprising two doped regions located in the substrate on both sides of the gate, wherein each of the first extension and the second extension of the charge storage layer The portion is located above the corresponding doped region. 3. The memory element according to claim 1, further comprising: two liners, respectively located between the gate and the second extension of each of the charge storage layers; and two spacers, located at the first Above one extension portion, the second extension portion is sandwiched between the corresponding lining layer and the gap wall. 4. A memory element, characterized in that it comprises: a gate located on a substrate; a gate dielectric layer located between the gate and the substrate, wherein a gap is formed on both sides of the gate dielectric layer, below the gate and above the substrate; two charge storage layers, each of which includes a main body and an extension, each of which is located in each of the gaps, each of the extensions is connected to each of the main parts and protrudes from the side wall of the gate, and the ratio of the length of the main body portion to the length of the extension portion is 2:1 to 5:1; and Two liners are located on the sidewalls of the grid, and edge regions of the extensions of each charge storage layer protrude from the sidewalls of the liners. 5. The memory element according to claim 4, further comprising two doped regions, located in the substrate on both sides of the gate, wherein the extension of each charge storage layer extends to the corresponding doped region. area above. 6. A method for manufacturing a memory element, characterized in that it comprises the following steps: forming a gate dielectric layer and a gate on the gate dielectric layer on a substrate, wherein a gap is formed on both sides of the gate dielectric layer, below the gate and above the substrate; forming two charge storage layers, each of the charge storage layers includes a main body and a first extension, each of the main body is located in each of the gaps, each of the first extensions is connected to each of the main body and protrudes from the gate and the ratio of the length of the main body portion to the length of the first extension portion is 2:1 to 5:1; and Two doped regions are formed in the substrate on both sides of the gate, and the first extension portion of each charge storage layer extends above the corresponding doped region. 7. The manufacturing method of the memory element according to claim 6, wherein each of the charge storage layers further comprises a second extension, each of the second extension is connected to the first extension, and extends upward to On the sidewall of the gate, the edge regions of each of the first extensions protrude from the corresponding sidewalls of each of the second extensions. 8 . The method for manufacturing a memory device according to claim 7 , wherein the first extension and the second extension of each charge storage layer are located above the corresponding doped region. 9. The manufacturing method of the memory element according to claim 6, further comprising forming a lining material layer to cover the surface of the substrate and the sidewall of the gate dielectric layer before forming the charge storage layers , the bottom, the sidewall and the upper surface of the gate, and the edge region of the first extension of each charge storage layer protrudes from the lining material layer located on the sidewall of the gate. 10. The manufacturing method of the memory element according to claim 9, wherein the step of forming the charge storage layers comprises: forming a charge storage material layer covering the liner material layer and filling the gap; forming a spacer material layer covering the charge storage material layer; and Anisotropic etching removes the spacer material layer, the charge storage material layer and the liner material layer to expose the gate and the surface of the substrate, leaving two spacers, the charge storage layers and the second liner layer . 11. The manufacturing method of the memory element according to claim 6, further comprising forming two liners on the sidewall of the gate, wherein the first extension of each charge storage layer protrudes from the corresponding liner layer side walls.