CN103098029A - Dynamic optimization of back-end memory system interface - Google Patents

Abstract

The architecture and corresponding operating techniques of the internal controller and memory circuit interface of a memory system such as a flash memory card or other similarly structured devices are given. The interface between the controller circuit and the memory circuit includes a feedback process where the amount of errors due to the controller-memory transfer is monitored and transfer characteristics (such as clock rate, drive strength, etc.) can be modified accordingly. Techniques for dynamically optimizing the performance of the controller-memory (or "background") interface of a non-volatile memory system are also presented. Memory systems are usually designed with some amount of error tolerance for errors that can then be corrected by ECC. In many cases, such as when the device is new, the ECC capability of the system exceeds what is needed to correct data storage errors. In these cases, the memory system internally allocates a non-zero portion of this error correction capability to the background interface. This allows the interface to operate eg at higher speed or at lower power, although this will most likely result in transmission path errors. The system can also calibrate the backend interface to determine the amount of error resulting from various operating conditions, allowing the operating parameters of the backend interface to be set according to the amount of error allocated to the transfer process.

Description

Dynamic Optimization of Background Memory System Interface

technical field

The present application relates to the operation of reprogrammable non-volatile memory systems, such as semiconductor flash memory, and more particularly, to the internal interface between the memory system's controller and the memory circuits.

Background technique

Solid state memory capable of non-volatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as small form factor cards, has recently become the storage of choice in a variety of mobile and handheld devices, especially information appliances and consumer electronics . Unlike RAM (Random Access Memory), which is also solid-state memory, flash memory is non-volatile and retains its stored data even after power is cut off. Also, unlike ROM (Read Only Memory), flash memory is rewritable similar to a disk storage device. Although more costly, flash memory is being used more in mass storage applications. Traditional mass storage based on rotating magnetic media such as hard drives and floppy disks is not suitable for mobile and handheld environments. This is because disk drives tend to be bulky, prone to mechanical failure, and have high latency and high power requirements. These undesirable properties make disk-based storage impractical for most mobile and portable applications. On the other hand, flash memory, both embedded and in the form of a removable card, is ideally suited for mobile and handheld environments due to its small size, low power consumption, high speed and high reliability features.

Flash EEPROM is similar to EPROM (Electrically Erasable Programmable Read Only Memory) in that it is a non-volatile memory that can be erased and have new data written or "programmed" into its memory cells. In a field effect transistor structure, both utilize a floating (unconnected) conductive gate over a channel region in a semiconductor substrate between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristics of the transistor are controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate to allow conduction between its source and drain regions before "turning on" the transistor. In particular, flash memory, such as flash EEPROM, allows an entire block of memory cells to be erased at the same time.

The floating gate can hold a range of charges and thus can be programmed to any threshold voltage level within the threshold voltage window. The size of the threshold voltage window is delimited by the device's minimum and maximum threshold levels, which in turn correspond to the range of charge that can be programmed onto the floating gate. The threshold window generally depends on the characteristics, operating conditions and history of the memory device. Each distinct range of resolvable threshold voltage levels within this window can in principle be used to specify a distinct memory state for the cell.

Transistors that function as memory cells are typically programmed to a "programmed" state by one of two mechanisms. In "hot electron injection", a high voltage applied to the drain accelerates electrons across the channel region of the substrate. At the same time, a high voltage applied to the control gate pulls hot electrons through the thin gate dielectric onto the floating gate. In "tunneling implantation", a high voltage is applied to the control gate relative to the substrate. In this way, electrons are pulled from the substrate to the intervening floating gate. Although the term "programming" has historically been used to describe writing to memory by injecting electrons into the memory cell's initially erased charge storage unit in order to change the state of the memory, it has now been used with terms such as "writing" or "programming" The more common term "record" is used interchangeably.

Memory devices can be erased by a variety of mechanisms. For EEPROM, it can be electrically erased by applying a high voltage to the substrate with respect to the control gate in order to induce electrons in the floating gate to tunnel through the thin oxide to the substrate channel region (i.e., Fowler-Nordheim tunneling) memory unit. Typically, EEPROMs are erased byte by byte. For flash EEPROM, the memory can be electrically erased all at once or one or more minimum erasable blocks at a time, where the minimum erasable block can be composed of one or more sectors, and each sector An area can store 512 bytes or more of data.

A memory device typically includes one or more memory chips that may be mounted on a card. Each memory chip includes an array of memory cells supported by peripheral circuits such as decoders and erase, write and read circuits. More complex memory devices also work with external memory controllers that perform intelligent and more advanced memory operations and interfaces.

There are many commercially successful non-volatile solid-state memory devices in use today. These memory devices may be flash EEPROMs, or other types of non-volatile memory cells may be used. Examples of flash memories and systems and methods of making them are given in US Pat. Specifically, flash memory devices having a NAND string structure are described in US Patent Nos. 5,570,315, 5,903,495, 6,046,935. Furthermore, non-volatile memory devices are also fabricated from memory cells having a dielectric layer for storing charges. Instead of the previously described conductive floating gate elements, a dielectric layer is used. "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell" by Eitan et al., IEEE Electron Device Letters, Vol.21, No.11, November 2000, pages 543-545 describe the use of dielectric memory elements of this memory device. The ONO dielectric layer extends across the channel between the source and drain diffusions. Charge for one data bit is located in the dielectric layer adjacent to the drain, and charge for the other data bit is located in the dielectric layer adjacent to the source. For example, US Patent Nos. 5,768,192 and 6,011,725 disclose non-volatile memory cells with a trapping dielectric sandwiched between two silicon dioxide layers. Multi-state data storage is achieved by separately reading the binary states of the spatially separated charge storage regions within the dielectric.

To improve read and program performance, multiple charge storage elements or memory transistors in the array are read or programmed in parallel. Thus, a "page" of memory elements are read or programmed together. In existing memory architectures, a row usually consists of several interleaved pages or it can constitute one page. All memory elements of a page will be read or programmed together.

In flash memory systems, erase operations can take almost an order of magnitude longer than read and program operations. Therefore, it is desirable to have erase blocks of sufficient size. In this way, the erase time can be amortized over a large group of memory cells.

The nature of flash memory dictates that data must be written to the memory locations to be erased. If data from a certain logical address of the host is to be updated, one way is to overwrite the updated data in the same network memory location. That is, the logical-to-physical address mapping does not change. However, this would mean that the entire eraseblock containing that physical location would need to be erased first and then rewritten with the updated data. This update method is inefficient because it requires erasing and rewriting the entire eraseblock, especially if the data to be updated occupies only a small portion of the eraseblock. It will also result in a higher frequency of erase recycling of memory blocks, which is undesirable in view of the effective endurance of this type of memory.

Data communicated through external interfaces of host systems, memory systems, and other electronic systems are addressed and mapped to physical locations in the flash memory system. Generally, addresses of data files generated or received by the system are mapped into different ranges of continuous logical address spaces established for the system according to logical blocks of data (hereinafter referred to as "LBA interfaces"). The address space is usually wide enough to cover the full range of addresses that the system can handle. In one example, a disk storage drive communicates with a computer or other host system through such a logical address space. This address space has a breadth sufficient to address the entire data storage capacity of the disk drive.

Efforts are ongoing to improve the performance of memory devices by reducing power consumption and increasing device speed. As mentioned above, a non-volatile memory device is typically formed of a controller circuit and one or more memory chips connected to each other by a bus structure. Settings of the controller/memory device interface such as voltage values and frequencies used are typically set according to expected worst-case scenarios in order to have sufficient safety margins to avoid device failure. Thus, in most cases the interface operates in sub-optimal conditions. This interface can therefore be the limiting factor in terms of device performance, so there is room for improvement in the design of this interface.

Contents of the invention

According to a general aspect of the invention, a method of operating a non-volatile memory system is presented. The non-volatile memory system includes: a controller circuit having a memory interface; a memory circuit having an array of non-volatile memory cells and the controller interface; and a bus structure connected to the memory interface of the controller circuit and the A controller interface of the memory circuit for transferring data and commands between the controller circuit and the memory circuit. The memory system is tolerant of a first non-zero amount of cumulative errors from the transfer of data from the controller to be written to the memory array until the data is received at the controller after being subsequently read back from the memory array. The method includes the controller circuit allocating a first non-zero portion of a first error amount to data transfers between the controller circuit and the memory circuit via a bus structure, the remainder of the first error amount being divided by Writing, storing and reading of data on the memory circuit is allocated. The controller circuit sets transfer characteristics between the controller circuit and the memory circuit to operate to tolerate up to a first portion of errors.

In other aspects, methods of operating a nonvolatile memory system having a controller circuit and a memory circuit are presented. The controller circuit performs transfer error calibration by processing each of a plurality of values of each of one or more operating parameters of a bus structure connecting the controller to the memory circuit. This process includes: transmitting a data set of known data pattern from the controller to the bus structure through the transmission circuit on the controller; and receiving the data from the bus structure through the receiving circuit on the memory circuit. data set. storing the received data set in a buffer memory on the memory circuit, and then transferring the data set stored in the buffer memory on the memory circuit to the bus structure via a transmission circuit on the memory circuit without writing to the array. A data set from the bus structure is received by receiving circuitry on the controller; and a comparison of the received data set to a known pattern is performed. Based on the comparison, an amount of error associated with the transmission is determined for the one or more parameters used. The memory system is then operated to allow a first non-zero amount of error in data transfer between the controller circuit and the memory circuit, wherein the controller circuit calculates a transfer error based on the determined associated error amount The calibration process selects values for operating parameters.

According to another general aspect of the invention, a non-volatile memory system has a controller circuit including a memory interface and logic; and a memory circuit including an array of non-volatile memory cells, the controller interface and logic. The memory system also includes a bus structure connected to the memory interface of the controller circuit and the controller interface of the memory circuit for transferring data and commands between the controller and the memory circuit. a feedback processing circuit connected to logic on the controller circuit and the memory circuit during data transfer between the controller and the memory circuit to receive information on the amount of error due to the transfer, and to to one or both of the memory interface and the controller interface to adjust a characteristic of a transfer between the controller circuit and the memory circuit in response to the error amount.

In other aspects, methods of operating a nonvolatile memory system including a nonvolatile memory circuit and a controller circuit are presented. A first hash value is generated from a data set in logic circuitry on a first of the controller circuitry and memory circuitry. transferring said data set and first hash value to a bus structure via an interface on a first of said controller circuit and memory circuit, and via an interface on a second of said controller circuit and memory circuit The data set and the first hash value are received from the bus structure. A second hash value is then generated from the received data set in logic circuitry on a second of said controller circuitry and memory circuitry, and the received hash value is then compared at a second of said controller circuitry and memory circuitry. The first hash value and the second hash value. Based on a comparison of the received first hash value and the second hash value by logic circuitry on a second of the controller circuit and the memory circuit, the system determines whether to alter the controller circuit and the second hash value. characteristics of data transfers between memory circuits.

Various aspects, advantages, features and embodiments of the invention are included in the following description of illustrative examples thereof, which description should be considered in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things cited herein are hereby incorporated by this reference in their entirety for all purposes. To the extent of any inconsistency or contradiction in the definition or usage of terms between any incorporated publication, document or matter and the present application, the definition or usage in the present application shall control.

Description of drawings

Figure 1 schematically illustrates the main hardware components of a memory system suitable for implementing the invention.

Fig. 2 schematically illustrates a non-volatile memory cell.

Figure 3 illustrates the relationship between source-drain current _ID and control gate voltage V _CG for four different charges Q1-Q4 that the floating gate can selectively store at any one time.

Figure 4A schematically illustrates a string of memory cells organized as a NAND string.

FIG. 4B illustrates an example of a NAND array 210 of memory cells composed of NAND strings 50 such as those shown in FIG. 5A.

Figure 5 illustrates a page of memory cells organized, eg, in a NAND configuration, being sensed or programmed in parallel.

6(0)-6(2) illustrate an example of programming a group of 4-state memory cells.

7A-7E illustrate the programming or reading of a 4-state memory encoded with a given 2-bit code.

FIG. 8 illustrates that memory is managed by a memory manager as a software component residing in the controller.

Figure 9 illustrates the software modules of the backend system.

10A(i)-10A(iii) schematically illustrate the mapping between logical groups and metablocks.

Fig. 10B schematically illustrates the mapping between logical groups and metablocks.

11 is a block diagram illustrating a feedback mechanism for determining interface integrity based on existing configurations.

Figure 12 is a block diagram illustrating an embodiment in which the feedback mechanism uses a hash engine to determine interface integrity.

FIG. 13 is a diagram showing an example of data transfer through a bus interface and generated hash values.

Figure 14 schematically illustrates contributors to bit errors in a memory system.

Figure 15 may be used to illustrate the operation of the pseudo-loopback method in the backend interface.

Figures 16 and 17 correspond to blocks 705 and 709 of Figure 15, respectively.

FIG. 18 is a simulated graph showing transmit BER versus data bus voltage and data transfer rate.

Figure 19 is a block diagram illustrating this crosstalk in a memory system whose bus structure uses multiple memory data buses.

Detailed ways

memory system

1 through 7 provide example memory systems in which various aspects of the present invention may be implemented or illustrated.

8-10 illustrate preferred memory and block architectures for implementing various aspects of the invention.

11-13 illustrate the use of an adaptive internal interface between a controller and one or more memory circuits.

Figure 1 schematically illustrates the main hardware components of a memory system suitable for implementing the invention. Memory system 90 typically operates with host 80 through a host interface. The memory system is usually in the form of a memory card or an embedded memory system. The memory system 90 includes a memory 200 whose operation is controlled by a controller 100 . Memory 200 includes one or more arrays of non-volatile memory cells distributed over one or more integrated circuit chips. Controller 100 includes interface 110 , processor 120 , optional coprocessor 121 , ROM 122 (read only memory), RAM 130 (random access memory) and optional programmable non-volatile memory 124 . The interface 110 has one component that interfaces the controller with the host and another component that interfaces to the memory 200 . Firmware stored in non-volatile ROM 122 and/or optional non-volatile memory 124 provides code for processor 120 to implement the functions of controller 100 . Error correction codes may be processed by processor 120 or optional coprocessor 121 . In an alternate embodiment, controller 100 is implemented by a state machine (not shown). In another embodiment, the controller 100 is implemented in a host.

physical memory structure

Fig. 2 schematically illustrates a non-volatile memory cell. The memory cell 10 may be realized by a field effect transistor having a charge storage unit 20 such as a floating gate or a dielectric layer. Memory cell 10 also includes source 14 , drain 16 and control gate 30 .

There are many commercially successful non-volatile solid-state memories in use today. These memory devices may employ different types of memory cells, each type having one or more charge storage elements.

Typical non-volatile memory cells include EEPROM and flash EEPROM. An example of an EEPROM cell and its method of manufacture is given in US Patent no. 5,595,924. Examples of flash EEPROM cells, their use in memory systems and their methods of manufacture are given in US Patent Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, 5,661,053, 5,313,421 and 6,222,762. Specifically, examples of memory devices having a NAND cell structure are described in US Patent Nos. 5,570,315, 5,903,495, and 6,046,935. Moreover, it has been published by Eitan et al. in "NORM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell", IEEE Electron Device Letters, Vol.21, No.11, November 2000, pages 543-545 and in US Patent Examples of memory devices utilizing dielectric storage elements are described in Nos. 5,768,192 and 6,011,725.

In practice, the memory state of a cell is typically read by sensing the conduction current across the cell's source and drain electrodes when a reference voltage is applied to the control gate. Thus, for each given charge on the cell's floating gate, a corresponding conduction current with respect to a fixed reference control gate voltage can be detected. Similarly, the range of charge programmable onto the floating gate defines a corresponding threshold voltage window or a corresponding conduction current window.

Alternatively, instead of detecting conduction current between divided current windows, it is possible to set a threshold voltage at the control gate for a given memory state under test and detect whether the conduction current is below or above the threshold current. In one embodiment, detection of conduction current relative to a threshold current is accomplished by examining the rate at which conduction current discharges through the capacitance of the bit line.

FIG. 3 illustrates the relationship between source-drain current _ID and control gate voltage V _CG for four different charges Q1-Q4 that the floating gate can selectively store at any one time. The four solid _ID versus _VCG curves represent four possible charge levels that can be programmed on the floating gate of a memory cell, corresponding to four possible memory states, respectively. As an example, the threshold voltage window for a group of cells may range from 0.5V to 3.5V. By dividing the threshold window into five regions at intervals of 0.5 V each, it is possible to demarcate the seven possible memory states "0", "1", "2" representing one erased and six programmed states, respectively. ", "3", "4", "5", "6". For example, if a reference current IREF of 2µA is used as shown, a cell programmed with Q1 can be considered to be in memory state "1" because its curve is in the region of the threshold window delimited by VCG = 0.5V and 1.0V with IREFs intersect. Similarly, Q4 is in memory state "5".

As can be seen from the above description, the more states the memory cell stores, the finer its threshold window is divided. For example, a memory device may have memory cells with a threshold window ranging from -1.5V to 5V. This provides a maximum width of 6.5V. If a memory cell were to store 16 states, each state could occupy from 200mV to 300mV in the threshold window. This will require higher precision in programming and reading operations in order to be able to achieve the required resolution.

Figure 4A schematically illustrates a string of memory cells organized as a NAND string. NAND string 50 includes a series of memory transistors M1 , M2 , . . . Mn (eg, n=4, 8, 16 or more) connected in daisy-chain through their sources and drains. A pair of select transistors S1, S2 controls the connection of the chain of memory transistors to the outside via source terminal 54 and drain terminal 56 of the NAND string respectively. In the memory array, when the source select transistor S1 is turned on, the source terminal is coupled to the source line (see FIG. 4B ). Similarly, when the drain select transistor S2 is turned on, the drain terminal of the NAND string is coupled to the bit line of the memory array. Each memory transistor 10 in the chain acts as a memory cell. It has a charge storage element 20 for storing a given amount of charge to represent a memory state of the map. A control gate 30 of each memory transistor allows control of read and write operations. As will be seen from Figure 4B, the control gates 30 of the corresponding memory transistors of a row of NAND strings are all connected to the same word line. Similarly, the control gate 32 of each select transistor S1, S2 provides controlled access to the NAND string via its source terminal 54 and drain terminal 56, respectively. Likewise, the control gates 32 of corresponding select transistors of a row of NAND strings are all connected to the same select line.

When an addressed memory transistor 10 within a NAND string is read or verified during programming, its control gate 30 is provided with an appropriate voltage. Simultaneously, the remaining unaddressed memory transistors in NAND string 50 are fully turned on by the application of sufficient voltage on their control gates. In this way, a conduction path is effectively established from the source of each memory transistor to the source terminal of the NAND string, and also from the drain of each memory transistor to the drain terminal 56 of the cell. Memory devices with such NAND string structures are described in US Patent Nos. 5,570,315, 5,903,495, 6,046,935.

FIG. 4B illustrates an example of a NAND array 210 of memory cells composed of NAND strings 50 such as those shown in FIG. 4A. Along each column of NAND strings, a bit line such as bit line 36 is coupled to drain terminal 56 of each NAND string. Along each row of NAND strings, a source line such as source line 34 is coupled to source terminal 54 of each NAND string. Also, the control gates along a row of memory cells in a row of NAND strings are connected to a word line, such as word line 42 . The control gates of select transistors along a row in a row of NAND strings are connected to a select line such as select line 44 . An entire row of memory cells in a row of NAND strings can be addressed by applying appropriate voltages on the word and select lines of that row of NAND strings. When a memory transistor within a NAND string is being read, the remaining memory transistors in the string are turned on hard via their associated word lines so that the current flowing through the string is substantially dependent on the memory transistor being read. Get the level of charge stored in the cell.

Figure 5 illustrates a page of memory cells organized, eg, in a NAND configuration, being sensed or programmed in parallel. Figure 5 generally shows a bank of NAND strings 50 in the memory array 210 of Figure 4V, where the details of each NAND string are explicitly shown in Figure 4A. A "page" such as page 60 is a group of memory cells that is enabled to be sensed or programmed in parallel. This is accomplished by the sense amplifier 212 of the corresponding page. The sensed results are latched in a corresponding set of latches 214, and each sense amplifier may be coupled to a NAND string via a bit line. A page is enabled by the control gates of the cells of the page being commonly connected to word line 42 , and each cell accessible by a sense amplifier is accessible via bit line 36 . As an example, when sensing or programming the page 60 of cells respectively, a sensing voltage or a programming voltage is applied to the common word line WL3, respectively, together with the appropriate voltage on the bit line.

physical organization of memory

An important difference between flash memory and other types of memory is that cells must be programmed from an erased state. That is, the floating gate must first be free of charge. Programming then adds the desired amount of charge back to the floating gate. It does not support removing a portion of the charge from the floating gate to go from a more programmed state to a less programmed state. This means that updated data cannot overwrite existing data and must be written to a location that was not previously written.

Furthermore, erasing removes all charge from the floating gate and typically takes a considerable amount of time. For this reason, erasing cell by cell or even page by page would be tedious and very slow. In practice, an array of memory cells is divided into a large number of blocks of memory cells. As is common for flash EEPROMs, a block is the unit of erase. That is, each block contains a minimum number of memory cells that are erased together. Although aggregating a large number of cells in a block to be erased in parallel will improve erase performance, the large size of the block also makes it necessary to deal with a large number of updates and obsolete data. Just before a block is erased, garbage collection is required to rescue non-obsolete data in the block.

Each block is usually divided into pages. A page is a unit of programming or reading. In one embodiment, individual pages may be divided into segments and a segment may contain the minimum number of cells that are written at one time as a basic programming operation. One or more pages of data are typically stored in one row of memory cells. A page can store one or more sectors. A sector includes user data and overhead data. Multiple blocks and pages distributed across multiple arrays can also be operated together as metablocks and metapages. If they are spread across multiple chips, they can be operated together as metablocks and metapages.

Example of Multi-Level Cell (“MLC”) memory partitioning

A nonvolatile memory in which each memory cell stores multiple bits of data has been described in connection with FIG. 3 . A specific example is a memory formed by an array of field effect transistors, each field effect transistor having a charge storage layer between its channel region and its control gate. A charge storage layer or cell can store a range of charges, resulting in a range of threshold voltages for each field effect transistor. The range span of possible threshold voltages is the threshold window. When the threshold window is divided into multiple sub-ranges or regions of threshold voltage, each distinguishable region is used to represent a different memory state of the memory cell. Multiple memory states can be encoded by one or more binary bits. For example, a memory cell divided into four regions can support four states that can be encoded as 2-bit data. Similarly, a memory cell divided into eight regions can support eight memory states that can be encoded as 3 bits of data, and so on.

All bits, full sequence MLC programming

6(0)-6(2) illustrate an example of programming a group of 4-state memory cells. Figure 6(0) illustrates the group of memory cells programmable to four different threshold voltage distributions representing memory states "0", "1", "2" and "3", respectively. Figure 6(1) illustrates the initial distribution of "erased" threshold voltages for an erased memory. Figure 6(2) illustrates an example of a memory after many memory cells have been programmed. Essentially, the cell initially has an "erased" threshold voltage and programming will move it to a higher value into one of the three regions delimited by verify levels vV ₁ , vV ₂ and vV ₃ . In this way, each memory cell can be programmed to one of three programmed states "1", "2" and "3" or remain unprogrammed in the "erased" state. As the memory gets more programmed, the initial distribution of "erased" states as shown in Figure 6(1) will become narrower and the erased states are represented by the "0" state.

Each of the four memory states can be represented using a 2-bit code with lower and upper bits. For example, "0", "1", "2" and "3" states are represented by "11", "01", "00" and "10", respectively. 2-bit data can be read from memory by sensing in "full sequence" mode by demarcating thresholds rV ₁ , rV ₂ and rV ₃ senses to sense two bits together.

Bit-by-bit MLC programming and reading

7A-7E illustrate programming and reading of a 4-state memory encoded with a given 2-bit code. 7A illustrates threshold voltage distributions for a 4-state memory array when each memory cell stores two bits of data using a 2-bit code. Such a 2-bit code has been disclosed in US Patent No. 7,057,939.

FIG. 7B illustrates upper page programming (upper bits) of a 2-pass programming scheme using a 2-bit code. In the second pass of programming the upper page bits to "0", if the lower page bits are at "1", as represented by programming the "unprogrammed" memory state "0" to "1" , the logical state (1,1) transitions to (0,1). If the lower page bit is at "0", the logic state (0,0) is obtained by programming from the "middle" state to "3". Similarly, if the upper page is to remain at a "1" and the lower page has been programmed to a "0", then it will be necessary to start from the "middle" state as represented by programming the "middle" state to a "2". Transformation to (1,0).

Figure 7C illustrates upper page programming (upper bits) in a 2-pass programming scheme using 2-bit codes. In the second pass of programming the upper bits to "0", if the lower page bits are at "1", as represented by programming the "unprogrammed" memory state "0" to "1", the logic State (1,1) transitions to (0,1). If the lower page bit is at "0", the logic state (0,0) is obtained by programming from the "middle" state to "3". Similarly, if the upper page is to remain at a "1" and the lower page has been programmed to a "0", then it will be necessary to start from the "middle" state as represented by programming the "middle" state to a "2". Transformation to (1,0).

Figure 7D illustrates the read operations required to discern the lower bits of a 4-state memory encoded with a 2-bit code. A read B operation is done first to determine if the LM flag can be read. If it can, the upper page has already been programmed and the read B operation will correctly produce the lower page data. On the other hand, if the upper page has not been programmed, the lower page data will be read by a read A operation.

Figure 7E illustrates the read operations required to discern the upper bits of a 4-state memory encoded with a 2-bit code. As is clear from the figure, a higher page read would require 3 read passes of Read _A , Read _B and Read _C with respect to the demarcation threshold voltages DA, DB and DC, respectively.

In a bit-by-bit scheme for 2-bit memory, a physical page of memory cells will store two logical pages of data: a lower data page corresponding to the lower bits and an upper data page corresponding to the upper bits.

Binary and MLC memory partitioning

6 and 7 illustrate examples of 2-bit (also referred to as "D2") memory. As can be seen, the D2 memory has its threshold range or threshold window divided into four regions, specifying 4 states. Similarly, in D3, each cell stores 3 bits (lower, middle, and upper bits), and there are 8 regions. In D4, there are 4 bits and 16 regions, and so on. As the memory's finite threshold window is divided into more regions, the programming and reading resolution will necessarily become finer. As memory cells are configured to store more bits, two problems arise.

First, programming or reading will be slower when the cell's threshold has to be programmed or read more accurately. In fact, in practice the sensing time (required in programming and reading) will increase as the square of the number of divided levels.

Second, flash memory has endurance issues as it ages with use. As the power source is repeatedly programmed and erased, charge travels to and from the floating gate 20 by tunneling across the dielectric (see FIG. 2 ). Each time some summation may become trapped in the dielectric and will modify the cell's threshold. In fact, with use, the threshold window will gradually narrow. Therefore, MLC memory is usually provided with a trade-off between capacity, performance and reliability.

In contrast, it will be seen that for binary memory, the threshold window of the memory is only divided into two regions. This will allow maximum margin for error. Thus, binary partitioning will provide maximum performance and reliability despite the reduction in storage capacity.

The multi-pass, bit-by-bit programming and reading technique described in connection with Figure 7 provides a smooth transition between MLC and binary partitioning. In this case, if the memory is programmed with only the lower bits, it effectively becomes a binary partitioned memory. Although this method does not fully optimize the range of the threshold window as in the case of single-level cell ("SLC") memory, it has the advantage of using a demarcation or sensing level that is different from the system in the operation of the lower bits of MLC memory. advantage. As will be described later, this approach allows MLC memory to be "commanded" for use as binary memory, or vice versa. However, it should be understood that MLC memories tend to have stricter usage specifications.

Binary memory and partial page programming

The charges programmed into the charge storage elements of individual memory cells generate electric fields that interfere with the electric fields of neighboring memory cells. This will affect the properties of adjacent memory cells which are actually field effect transistors with charge storage elements. Specifically, when sensed, a memory cell will appear to have a higher threshold level (or be more programmed) than if it were less disturbed.

Typically, if a memory cell is program-verified in a first field environment and later read again in a different field environment due to adjacent cells being subsequently programmed with a different charge, due to a phenomenon known as the "Yupin effect" In the phenomenon of coupling between adjacent floating gates, read accuracy may be affected. With ever-higher integration in semiconductor memories, perturbations in the electric field between memory cells due to stored charges (Yupin effect) become increasingly appreciable as the intercellular pitch shrinks.

The bit-by-bit MLC programming technique described above in connection with FIG. 7 is designed to minimize program disturb from team members along the same word line. As can be seen from Figure 7B, in the first pass of the two-pass programming, the cell's threshold moves at most half way above the threshold window. The influence of the first pass is overtaken by the final pass. In the final pass, the threshold moves only a quarter of the way. In other words, for D2, the charge difference between adjacent cells is limited to a quarter of its maximum. For D3, through three passes, the final pass will limit the charge difference to one-eighth of its maximum.

However, bit-by-bit multi-pass programming techniques will be compromised by partial page programming. A page is a group of memory cells, usually along a row of word lines, that are programmed together as a unit. Non-overlapping portions of a page can be programmed by multi-pass programming respectively. However, since not all cells of the page are programmed together in the final pass, large differences in programmed charge between cells may be created after a page is complete. Therefore, partial page programming will result in larger program disturb and will require a larger margin for sensing accuracy.

In the case where the memory is configured as a binary memory, the margin of operation is wider than that of MLC. In a preferred embodiment, the binary memory is configured to support partial page programming, in which non-overlapping portions of a page can be programmed in each of multiple pass programming passes of a page. Program and read performance can be improved by operating with large-sized pages. However, its use will be inefficient when the page size is much larger than the host's write unit (typically 512-byte sectors). Operating at a granularity finer than a page allows more efficient use of such pages.

Examples have been given between binary versus MLC. It should be understood that, in general, the same principles apply between a memory having a first number of ranks and a memory having a second number of ranks more than the first memory.

Logical and Physical Block Structure

FIG. 8 illustrates that memory units are managed by a memory manager as a software component residing in the controller. The memory 200 is organized into blocks, and each block unit is the minimum unit of erasing. Depending on the implementation, the memory system may operate with even large numbers of units of erase formed by aggregating blocks into "metablocks" and also "metablocks". For convenience, this description will refer to units of erasure as metablocks, although it will be understood that some systems operate with even larger units of erasure, such as "metablocks" formed by aggregation of metablocks.

The host 80 accesses the memory 200 when running applications under the file system of the operating system. Typically, the host system addresses data in units of logical sectors in which each sector stores 512 bytes of data. Moreover, the host generally reads or writes to the memory system in units of logical clusters, each logical cluster consisting of one or more logical sectors. In some host systems, there may be an optional host-side memory manager for lower-level memory management at the host. In most cases, during a read or write operation, the host 80 actually issues a command to the memory system 90 to read or write a segment of data containing a series of logical sectors with contiguous addresses.

The memory manager 300 on the memory side is implemented in the controller 100 of the memory system 90 to manage storage and retrieval of data of host logical sectors between metablocks of the flash memory 200 . The memory manager includes a foreground system 310 and a background system 320 . Foreground system 310 includes host interface 312 . Background system 320 includes a number of software modules for managing erase, read and write operations of metablocks. The memory manager also maintains system control data and directory data associated with its operation between flash memory 200 and controller RAM 130 .

Figure 9 illustrates the software modules of the backend system. The background system mainly includes two functional modules: media management layer 330 and data flow and sorting layer 340 .

The media management layer 330 is responsible for organizing logical data storage within the flash memory metablock structure. More details will be provided later in the section on Media Management.

The data flow and ordering layer 340 is responsible for the ordering and transfer of sectors of data between the foreground system and the flash memory. This layer includes command sequencer 342 , low level sequencer 344 and flash control layer 346 . More details will be provided later in the section on "Low-Level System Description".

The memory manager 300 is preferably implemented in the controller 100 . It translates logical addresses received from the host into physical addresses within the memory array where the data is actually stored, and then handles these address translations.

10A(i)-10A(iii) schematically illustrate the mapping between logical groups and metablocks. A metablock of physical memory has N physical sectors for storing data of a logical group of N logical sectors. FIG. 10A(i) shows data from a logical group LG _i , where the logical sectors are in consecutive logical order 0, 1, . . . , N-1. FIG. 10A(ii) shows that the same data is stored in the metablocks in the same logical order. Metablocks are said to be "sequential" when stored in this manner. In general, metablocks may have data stored in a different order, in which case the meta is said to be "out of order" or "out of order".

There may be an offset between the lowest address of a logical group and the lowest address of the metablock to which it is mapped. In this case, the logical sector address wraps around as a loop from the bottom of the logical group within the metablock back to the top of the logical group. For example, in FIG. 10A(iii), the metablock is stored in its first location starting with the data of logical sector k. When the last logical sector N-1 is reached, it wraps back to sector 0 and finally stores the data associated with logical sector k-1 in its last physical sector. In a preferred embodiment, a page tag is used to identify any offset, such as a logical sector address that identifies the beginning of the data stored in the first physical sector of the metablock. Two blocks are considered to have their logical sectors stored in a similar order when they differ only in the page label.

Fig. 10B schematically illustrates the mapping between logical groups and metablocks. Each logical group 380 is mapped to a unique metablock 370, except for a small number of logical groups where data is currently being updated. After a logical group has been updated, it can be mapped to a different metablock. Mapping information is maintained in logical-to-physical directory sets, which will be described in more detail later.

Adaptive Controller-Memory Interface

This section presents the use of feedback mechanisms and processing units that monitor the transfer integrity of the internal controller-memory interface of the memory system and can adjust interface settings accordingly. This allows the system to optimize interface performance. For example, the power of the system can be reduced or the bus clock of the interface can be sped up, since this is usually an internal performance bottleneck, this allows an increase in performance from the outside of the memory system (ie from the host). In case of a transmission error, with the help of interface integrity feedback and, depending on the embodiment, other sensors or parameters, the feedback processing unit can decide whether to adjust the interface settings, perform a transmission retry, or ignore the error. The following discussion will also be given in the context of memory cards using NAND-type architectures for memory arrays as shown in Figures 4A, 4B and 5, but can be easily extended to other architectures with similar internal interfaces, other forms of Memory and non-card use, such as embedded systems, SSDs, and so on.

Although the following discussion may be based on various example embodiments to provide specific examples, the techniques and structures herein are generally well applicable to memory systems having a controller and multiple heaps that can operate independently, where the heaps include some amount of available Whether it is flash or some other kind of non-volatile memory that stores system data, the controller can use the system data to manage the memory system. These may include, in addition to the other references listed above, the various memory systems given in the following US patents, patent publications and patent numbers: 7,840,766; US-2005-0154819-A1; US-2007-0061581-A1; US-2007-0061597-A1; US-2007-0113030-A1; US-2008-0155178-A1; US-2008-0155228-A1; 0155227-A1; US-2008-0155175A1; 12/348,819; 12/348,825; 12/348,891; 61/142,620.

This section will begin by further considering the problems overcome above before discussing example embodiments. Data is transferred between the controller (100, FIG. 1) and one or more NAND (in example embodiments) devices (200, FIG. 1) using a controller-memory device interface. (Note that this discussion refers to the internal interface on memory system 90 between controller 100 and flash memory 200, while interface 110 is the host interface used by the control to communicate externally with the memory system.) Various NAND interface mode to increase interface performance for tradeoffs in speed, power consumption, etc. Since this interface is often the performance bottleneck, these interfaces are pushed to the limit for maximizing system performance. To avoid data errors, interface settings (such as voltage, frequency, drive strength, and slew rate control) are being set for worst-case scenarios (extreme temperature, extreme load capacitance, extreme voltage, etc.). Thus, devices are usually designed with a worst-case safety margin, which becomes a large margin under usual conditions. Under such typical conditions, the interface settings can be optimized to a much higher interface performance without compromising product reliability. Without mechanisms such as those presented below, the memory device will continue to operate at worst case performance settings.

For example, a simple comparison between the burst transfer times for 16-bit normal mode at nominal bus frequencies of 33MHz to overboosted 40MH to overboosted 50MHz and super overboosted 60MHz yields approximately 17%, 33%, and Huge wait time reduction of 45%. This is shown in Table 1, where the columns are frequency, corresponding cycle (t _cyc ), time to transfer 2142 bytes of data, and speed ratio relative to speed at 33 MHz.

In the prior art, for a given product, the performance of the flash interface is usually set as a fixed performance. Then, the design takes into account the worst case design. In some products, the flash interface is configured for "near worst case", allowing some optimization of interface performance, but at the risk of some lower device yield or increased data errors.

This section presents a feedback mechanism and processing unit that monitors interface performance integrity and adjusts interface settings accordingly in order to optimize interface performance. In case of a transmission error, the feedback processing unit (via interface integrity feedback and possibly with the help of other sensors or parameters) can decide whether to adjust the interface settings, retry the transmission, or ignore the error. In the absence of transmission errors, the feedback processing unit may decide to leave the interface settings as they are or to modify the interface settings in order to increase interface performance. In addition, the interface integrity feedback mechanism can be designed in such a way that the feedback processing unit can get different levels of information, such as binary pass/fail indication, pass/fail plus the number of errors or pass/fail plus the number of errors plus wrong position.

Depending on the embodiment, the feedback mechanism may utilize existing session infrastructure or may be further optimized by a dedicated mechanism such as a hash engine. Such dedicated mechanisms may be implemented in hardware, software or a combination thereof. The hashing engine can also be supplemented by an error correction engine capable of correcting transmission errors. Such an approach would allow the interface to cope with a level of bit error rate while still achieving optimal performance. The transfer correction capability is valuable because the design of ECC for NAND bit failures in the prior art only considers errors on the memory itself, and does not consider the interface that may occur when data is transferred between the controller and the memory device mistake. As the performance of the interface increases, the possibility of transmission errors increases. Having legacy ECC cope with interface errors reduces the capabilities of legacy ECC in terms of performance and probability for unrecoverable errors. Designing a dedicated interface error correction engine allows for “divide and conquer” where legacy ECC only focuses on NAND-generated errors. (Additional background details on ECC can be found in the following US patents, patent publications and patent application numbers: 2009/0094482; 7,502,254; 2007/0268745; 2007/0283081; 7,310,347; ; 2007/0091677; 2007/0180346; 2008/0181000; 2007/0260808; 2005/0213393; 6,510,488; 7,058,818; 2008/0244338;

Figure 11 is a block diagram illustrating such a feedback mechanism but based on a common prior art existing NAND/controller infrastructure. This will help further illustrate some of the concepts involved as well as provide alternative embodiments of adaptive interfaces. In FIG. 11, only elements relevant to this discussion are explicitly shown, and other elements are deleted to simplify this discussion. On the controller 100 are an ASIC core 411 , an ECC circuit 413 , an output buffer 415 , an input buffer 425 , a transmission circuit 417 and a reception circuit 427 . Although shown here as separate, in actual implementation this may not be the case: input or output buffers may overlap or may be identical; transmit and receive may be shared elements or may even be identical; ECC circuitry may be implemented as an ASIC core software in ; etc. On the memory side 200, the elements shown are a read circuit 431 and a transfer circuit 441 (which again may partially or completely overlap), an input data buffer 433 and an output data buffer 443 (similarly, they may be a single buffer), and NAND core435. The controller 100 and the memory circuits are then connected via the bus structure 401 .

The general flow for a host data set once received at controller 100 is from ASIC core 411 , through transmit circuit 417 and onto bus structure 401 to output data buffer 415 . On the memory 200 , data is transferred from the bus by the receiving circuit 431 into the input data buffer 433 , and then written into the NAND core 435 . Subsequently, when the host wants to access the data, the data is read from the NAND core 435 to the output data buffer 443, transmitted to the bus structure 401 by the transmission circuit 441, and then read from the bus to the controller by the receiving circuit 427 In the input data buffer 425. The memory system usually uses error correction code (ECC) to detect and correct errors that may enter the data, wherein the controller generates the corresponding ECC, which is transmitted with the data and written to the NAND core , and then read it back along with the data. The ECC engine 413 then has access to the data and its corresponding ECC, allowing the data to be checked and corrected, if necessary, before being passed on to the host.

Although ECC can be used to correct data errors, it can only correct a limited amount of errors, where the amount is a design choice. Within these capabilities, the ECC engine 413 can call any errors that are accumulating during the round trip, including transmission errors as well as errors associated with the NAND core 435 itself, such as write errors, read errors, and disturbances and other losses of data while storing However, the choice of ECC is usually only based on the consideration of errors related to NAND core 435 . In some arrangements, such as those with "strong ECC" disclosed in some of the above-listed references for ECC, the code is based on the characteristics of the memory and how the data states are mapped into the memory. Transfers between the controller and memory were largely ignored and considered free of error additions. Thus, the interface needs to be set accordingly, resulting in setting parameters according to worst case or near worst case, as described above.

The first set of embodiments is based on the elements of Figure 11 to provide feedback for optimizing interface characteristics. The data set is sent with the corresponding ECC in a round trip from the controller to the memory and back to the controller, much like the standard write followed by a read described above, except the data (and corresponding ECC) are not actually written into the memory core. While a write transfer is being issued from controller 100 to memory circuit 200, the controller can use buffer latches 433 and 443 to read the data back. This is represented by path 437, although if the input and output buffer system, then there will be no actual transfer. Since this round trip removes errors associated with the array 435 itself, this isolates the effects of the transfer and allows the ECC engine 413 to determine the integrity of the memory interface. Interface parameters can then be modified and the process can be reissued. In this way, both reading and writing interface parameters can be optimized.

Figure 12 is a block diagram illustrating another set of embodiments, but where the feedback mechanism uses a hash engine and an optional data correction engine specific to the interface. Instead of referring to the controller and memory chips, Figure 12 is given in terms of circuitry on the transmitter side 520 and receiver side 530, because as described further below, depending on whether it is a read or a write process and whether symmetry is required on both sides, these Either one can be a controller and the other a memory.

The transmitter side 520 will again include a write data buffer 521 and a transmission interface circuit 529 . A hash generator 525 and a multiplexer 527 will also be included. In the transfer process, the data to be written ( 523 ) is transferred from the write buffer 520 to both the hash value generator 525 and the MUX 527 . A hash value generator 525 accordingly generates a hash value from the data, which is then passed to MUX 527 . The multiplexer then provides the data followed by its hash value to the transport interface circuit 529 and then onto the bus structure 550 .

The receiver side again includes receiver interface circuitry and read data buffer 535 plus some additional elements. After the read interface circuit 532 fetches the data and the corresponding hash value from the bus 550, the demultiplexing circuit 533 separates the hash value from the data, and the read data is sent to the buffer 535 and also sent to the receiver side hash hash value generator 539, the receiver-side hash value generator 539 generates a hash value from the data set. The hash value generated on the receiver side is then compared with the received hash value in comparison circuit 541 . Depending on the embodiment, the result of the comparison may simply determine whether the values match or further determine the amount of error due to the transfer process. A data correction engine 537 may also be included in some embodiments to correct interface errors without data retransmission. In an example embodiment, the hash generator (and optional data correction engine on the receiver side) is separate from the ECC for NAND core errors used, although there may be some overlap in the circuit; and, in fact, Both can be implemented on the same logic circuit of the controller, but through different firmware codes. (Although considered separate for this discussion, the two error detection/calling parts may also interact in a more general embodiment as described below.) Typically, this will be based on the entirety of the information being sent (user data, corresponding ECC, header information, etc.), but in alternative embodiments, the hash value may be generated from a portion by, for example, removing various overheads and using only the user data itself used to generate the hash value.

FIG. 12 also includes a feedback processing unit 560 connected to receive the output of the hash comparison circuit 541 . This feedback is then analyzed at 561, which, depending on the embodiment, may take into account one or more of temperature, supply voltage level, and pre-processing related properties of the NAND core. At 563, the results of this feedback may then be used to adjust the transfer process and interface to one or both of the transfer interface circuit 529 and the read interface circuit 531 accordingly. For write operations (where the controller is the sender side), after a write transfer is issued from the controller to the memory device, the feedback processing unit may simply read back a comparison of the resulting hash values and determine write direction memory interface integrity from this. Based on this, the interface write parameters can be modified and the process can be re-issued if desired. Symmetrically, the same operation can be employed for the read direction where the memory is the transmitter side.

FIG. 13 is a diagram showing an example for transferring data through a bus interface and a generated hash value. As shown in the upper part, the corresponding hash values are automatically appended to the data so that they will be transmitted together when the device operates in this mode. In the second option shown in the lower part, the data payload is transmitted, the receiving side requests the corresponding hash value, which is then generated and transmitted. The data payload can be a predetermined length or a random length. If the data payload length is predetermined, a hash value can be appended to the data as in the first option, or the hash value can be sent on request. If the data payload length is random, the hash can be sent after the specific command is issued.

Many variations are possible to the technique and corresponding circuitry described with respect to FIG. 12 . Regarding the hash engine and the hash value, the hash engine may be a parity check code (cyclic redundancy check or CRC), ECC, or the like. For example, a "binary" embodiment that would return pass/fail could be used, which could be built on error bit count (CRC) and have the benefit of a low gate count for implementation. Alternatively, a "soft" embodiment could return the Errored Bit Count (EBC), and optionally the position of the failed bit, and it could be built based on an ECC code such as BCH or Reed-Solomon code, providing more information to help The system makes accurate decisions. The hash engine optionally also has complementary features such as correcting interface failures, similar to correcting flipped bits from memory cores, as represented by data correction engine 537 of FIG. 12 . Based on feedback from the transfer, the system can repeat the transfer. Delivery retries may be decided based on binary delivery status or based on soft delivery status. In addition, transfer retries can be decided based on a combination of the transfer state and the number of NAND flips; for example, if the interface introduces N errors and the NAND introduces M errors and the controller error correction capability is P, and P>N+ M, the system can decide not to retransmit.

The system can also be configured in various other ways. The configuration can be symmetric, where the hash engines on the controller and memory side are the same or symmetric. In a symmetric configuration, different configurations are used for different transfer directions; for example, faster mechanisms may be involved for read transfers while more reliable mechanisms are designed for write transfers. Also, it should be noted that even if the interface is configured symmetrically, it may behave asymmetrically with respect to a given data set because settings may change during the interval between the initial write of the data and the subsequent read.

The feedback processing unit 530 may be variously located on the controller 100, on the memory 200, on both, or distributed between the two. It can also be formed on a separate circuit. In many applications, it will be most practical to implement the feedback processing unit on the controller because the controller circuitry often includes higher levels of processing capabilities and also because memory systems are often formed from multiple memory chips, but the techniques presented here It is not limited to this. In either of these variations, it is the responsibility of the Feedback Processing Unit to check the status phase of the data transfer.

Consider further the example where the feedback processing unit is on the controller side: in the read direction, after it reads the data and hash over the air, they will be passed through the feedback mechanism, and the controller will determine the pass/device state and can adjust accordingly ( or not adjusted) interface settings. Since the controller has already read the data and the hash, there is no further need for information from the flash side to determine the state, as this can be done in the logic of the controller. In the write direction, the data payload and corresponding hash value are sent to the memory side, and the controller can then operate in several different ways: read pass/fail status from the memory side; read back the hash value and determine pass /fail; read back error bit count (EBC) from memory; read back EBC and error location from NAND; or read pass/fail status and number of corrected bits from memory side.

The feedback processing unit may decide to modify the interface settings. For example, the following interface settings can be modified: drive strength; bus frequency or other timing parameters; interface voltage; interface mode (e.g. switching from normal/legacy to trigger mode); etc. These interface settings can then be modified in an adaptive feedback manner. Because factors such as process variations, supply voltage levels, and temperature affect the likelihood of interface errors, these factors may also be included as inputs to the feedback analysis 561 on FIG. 12 .

Bus frequency and other parameter settings can be based on earlier remissions, and calibration parameter settings can also be set in various ways. For example, a look-up table (LUT) with different values for different bus sizes/NAND configurations may be used. Such look-up tables (LUTs) may also have different values for different operational process parameters, voltage supply levels, temperatures, and the like. Instead of being predetermined in the LUT, process parameters, voltage supply levels and temperature can also be variable as a function (formula).

Optimization tasks can be set in the background operation interface. Special events such as voltage supply or temperature changes can also be used to trigger interface setup training tasks. The interface training task may also use known patterns of transfer across the NAND core without writing to the NAND core, such as described above with respect to FIG. 11 and path 437 . The interface settings can also be different, and can be based on read and write directions, or on different data retention requirements.

The above discussion has primarily considered a memory system as having a controller and a single memory device circuit. More generally, the system may include several memory chips that may be connected to the controller (and the feedback processing unit - if it is a separate circuit) using various bus topologies. For example, all memory chips could share a single system bus; or each memory circuit could have its own controller-memory bus; or various hybrid arrangements could be used. Different interface settings can then be applied to this multiple NAND devices (eg if interfacing several devices this can be done in parallel). Based on the specific NAND device being accessed, different interface settings may also be used, as the interface properties may be a function of the load and/or cell/block properties of the specific NANF device). Furthermore, within a given memory device, different interface settings may also apply to blocks within a NAND core, as the interface properties may be a function of the properties of the specific block.

More details on the techniques of the above sections can be found in US Patent Application No. 12/835,292, filed July 13, 2010.

Dynamic Optimization of Background Memory System Interface

This section will further consider the memory system's controller-memory (or "background") interface and present guidelines for dynamically optimizing background read and write performance suitable for high-speed memory systems, including those with multiple memory data buses. some way. As discussed above, memory systems are typically designed to have some amount of error tolerance; and while this error can occur both in the controller-to-memory transfer process as well as in the actual on-memory store process, traditionally for ECC processes Only the latter of the two is considered, and the background interface is usually optimized to eliminate or at least minimize transmission channel errors as much as possible. However, in many cases, data errors resulting from storage processing (including read and write errors) may be well below the system's ECC capabilities. For example, while a heavily cycled device may require full usable data correction, a new device may have relatively few errors, leaving excess error correction capability for the system. This section gives the method for internally allocating a non-zero portion of this error correction capability to a transport channel by its memory system. This allows the interface to operate eg at higher speeds or at lower power even though this would most likely result in transmission path errors. Allocation can be dynamically adjusted when a higher amount of error correction is required for a memory portion. In a complementary aspect, the system can calibrate the transmission path to determine the resulting amount of transmission error for different operating parameters, and then select parameters based on how much is allowed.

Considering further the background interface between the controller and the memory section, a typical memory system consists of a memory controller and memory devices such as NAND flash memory modules. The background interface is the data bus between the memory and its controller. This interface is typically established in one of two ways. In a first approach, if the controller and memory devices are discrete components, the background interface is established by tracing on a printed circuit board (PCB) on which these components are arranged. In a second approach, the controller and memory can be packaged in a single package, such as a system in package (SIP) or a multi-chip package (MCP). In this second case, the background interface is established through the packaging substrate.

As discussed in the previous sections, the overall bit error rate (BER) in a memory system can be contributed by two main factors: the reliability of data retention in a memory device such as NAND flash memory; and the imperfection of the background interface, This may cause transmission errors. Error Correction Coding (ECC) can then be employed in the memory system to account for this overall BER. Figure 14 schematically illustrates contributors to bit errors in a memory system.

As shown in Figure 14, one of the main sources of overall bit error rate BER605. The effect of this error and any errors introduced in the read and write process due to data loss of the stored data (from charge leakage, disturbance, etc.) is shown at NAND hold 601 . Traditionally, data correction is used to only account for this factor, which is observed when the data is read. Errors due to channel defects are shown at 603 and affect both data reads and writes, but the effect will again be observed on reads. Sources of channel-influenced errors can include intersymbol interference (ISI), crosstalk on the same data bus (intra-bus), crosstalk between buses (on multiple data bus designs), printed circuit board (PCB) noise, silicon wafer noise, packaging noise, etc. wait. On the other side, the ECC607 can correct errors up to a certain level of error.

As the data transfer rate between the controller and memory increases, the background interface becomes more susceptible to signal integrity-related issues that contribute to 603, such as crosstalk between signals within the same data bus (memory data bus crosstalk ) and intersymbol interference (ISI). In addition, the introduction of memory topologies (multiple memory data bus designs) where a controller can simultaneously access multiple memory devices causes background interfaces to experience simultaneous switching noise and crosstalk between data buses (inter-memory data bus crosstalk). In addition to the bus speed, factors such as the voltage amplitude of the data bus and the temperature (the ambient temperature of the PCB line and the junction temperature of the system package (SIP) or multi-chip package (MCP)) may also affect the signal of the background interface integrity. Thus, the inherent weakness of the background interface becomes a bottleneck that determines the overall system performance of the high speed memory system. The pin capacitance of a memory device increases with the number of memory dies. High-capacity memory devices constructed of multiple memory dies exhibit high capacitance on their data input/output (I/O), which further degrades the edge rate and signal integrity of the data bus structure.

Signal integrity related issues on the signal lines can be minimized by increasing the separation of the signal lines from each other to minimize crosstalk; however this approach is limited by the available area on the PCB or substrate. This can also be reduced by choosing PCB materials with low dielectric constant and low dissipation factor (loss tangent). So while there are ways to reduce this error by slowing down the bus speed or compromising the output of operating bus parameters, these ways suffer from disadvantages.

This section presents dynamic optimization techniques for addressing these signal integrity issues in the background interface and also addressing process variations between the controller and memory devices. In addition to process changes, the voltage settings and temperatures at which the memory system operates may also change. A static approach does not account for variations in process, voltage, and temperature, so may not be the best approach.

This section uses a pseudo-loopback approach to dynamically optimize the background performance of memory systems, including memory systems with multiple memory data buses. This can be done using a predetermined data pattern through a similar sorting mechanism as described in the previous section. An example embodiment will use a pseudorandom bit pattern (PRBS). Dynamically optimizing data bus settings can help maximize the reliability of data transfers between the controller and memory devices. This may allow the memory system to distinguish transmission errors from errors caused on the memory device. These aspects are particularly advantageous for products equipped with high-speed background memory interfaces and multiple memory data buses.

Traces on a PCB or packaging substrate have limited bandwidth, which causes inter-symbol interference (ISI). The impact of ISI depends on the edge rate (rise time and fall time), data rate and data pattern. In digital communications, pseudo-random bit pattern (PRBS) patterns are sometimes used to exploit the worst-case ISI effects of data links because such patterns are rich in frequency content. A PRBS pattern is a repeating pattern that has similar properties to a random sequence and is used to measure jitter and eye masks of transmitted data in electrical data links. PRBS is often denoted as 2X-1PRBS or PRBS-X, where the power (X) represents the length of the shift register used to create the pattern. It is desirable to use the longest PRBS pattern that is practical, since it places the most stress on the signal link and provides a better representation of random data.

Although the example embodiment uses a pseudo-random bit pattern, other patterns can be used, as long as the system knows the pattern of the data set that is used so that it can be compared with the data coming back at the end of the loopback process. Example embodiments use the PRBS pattern because its random-like characters can maximize the ISI impact of the signal link. In addition to PRBS patterns, other types of data patterns can be utilized in the present invention, and each respective pattern can produce different results.

PRBS patterns can be applied to each signal link in the parallel background interface. Ideally, although a pattern would repeat infinitely, which is not practically feasible in a memory system, this should not be a major disadvantage if the pattern is repeated enough times by using short patterns. For example, if the page size of the NAND flash memory is 16kB, a PRBS-7 pattern with a pattern length of 127b can be completely repeated 129 times on each signal link of an 8-bit data bus. The remaining bits (16384b-127bx129=1b) constitute an incomplete copy of PRBS-7. This incomplete PRBS pattern at the end should not cause serious problems, since most transport connection effects are already resolved by 129 cycles of the complete PRBS pattern.

Figure 15 may be used to illustrate the operation of the loopback method in the backend interface. In Fig. 15, the flow is on the left and the corresponding controller-memory interaction is schematically illustrated on the right. At 701, the controller turns off its data scrambling and error correction coding (ECC) capabilities, where on the right, this is shown by these elements being crossed. Thus, all data transferred from and to the controller is in its original format without any scrambling or correction. At 703, the controller sends a command to the memory device telling the memory device to store and hold the received data in its data latch detector without transferring them to the memory cells. That is, this data set is not programmed into the memory cells. At 705, the controller sends the known data patterns (here individual PRBS-7 patterns) on each data link in the data bus structure to the memory device. The memory device holds the data in the data latch register until it becomes full.

At 707, the controller sends a command to the memory device telling the memory device to continuously send back the data stored in its data latch register until the controller instructs it to stop. That is, after the data latch registers have been emptied of all 16kb of data on each link, it will start sending back the same data again. Therefore, the PRBS-7 pattern is repeated on each signal link of the data bus. The reason for the continuous operation of the example embodiments using PRBS style transmission is that bit errors introduced by signal linking are probabilistic events. The greater the amount of data transferred across the link, the more accurate and representative is the transmission bit error rate (BER), a statistical measure of inherent connection performance. At 709, the controller receives a repeated PRBS-7 pattern (or other used data pattern) on each signal link of the data bus.

At 711 the controller compares the received data to the transmitted data pattern (here the standard PRBS-7 pattern) and reports any errors as a transmit BER. The controller then sends a command to the memory device to stop sending the PRBS-7 pattern (713) and exit pseudo-loopback mode (715).

FIG. 16 corresponds to block 705 of FIG. 15 , where the controller sends the data pattern to the memory device, and FIG. 17 corresponds to block 709 . In both figures, a specific example of the bus structure 811 is shown, in which several lines for command and control signals are shown in the upper part, and a plurality of data lines are shown in the lower part. Again, CLE = Command Latch Enable, ALE = Address Latch Enable, RE = Read Enable, WE = Write Enable, DQS = Data Strobe, and there are eight input/output lines (IO0-IO7). These block diagrams are simplified for the purpose of this discussion, only the ECC block 805 and PRBS generator 803 are shown on the memory controller, only the data register REG 833 is shown on the memory device 831, other elements including the non-volatile permanent memory array) not explicitly shown. When the controller 801 sends a data pattern to the memory device 831 in FIG. 16, the write enable signal and the Yes select will be asserted and each signal line will carry the data pattern. Again, each IO line carries an independent style. Again, these are all individual replicas of the PRBS, but may have different timings, as shown by their relative offsets in the figure. On memory 831, the data pattern is then stored in register 833 as it is received. In FIG. assignment. Once the data pattern has been round-tripped (without being written to non-volatile memory) and back on the controller 801, it can be checked against its original form and see how much corruption has occurred. Although the bus structure 811 is a parallel bus interface with multiple signal lines, this is only a specific example and other bus structures may be used for the transmission channel, such as a serial data arrangement.

The performance of a memory system is characterized by the data transfer rate (bus operating frequency) versus power consumption, which is directly related to the data bus voltage. By varying the voltage magnitude of the data bus (determined by the I/O of the device driving the data bus) and the data transfer rate, a 3-dimensional representation as a shmoo plot can be created, with the transfer rate plotted along the x-axis and the data bus Voltage is plotted along the y-axis, and transmission BER is plotted along the z-axis. Again, the data transfer rate may refer to the data transfer rate applied during a write operation when data is transferred from the controller circuit to the memory circuit, as in 705 of FIG. The data transfer rate of the application, as in 709. The data represented in such a simulation plot has covered worst case, typical case and best case cases, which can be measured at various output drive impedances (drive strengths) and temperatures. Thus, for a given amount of allowable transmission errors, an optimal operating point can be determined at a given combination of parameters such as data bus voltage, output drive impedance, slew rate, line capacitance, transmission rate, temperature, and power consumption. An example of a simulation graph is shown in FIG. 18 .

18 is an example of a simulated graph showing transfer BER versus data bus voltage and data transfer rate at fixed output drive impedance, slew rate, line capacitance, and temperature for a specific example of a memory system. The data bus voltage is V _DD on the vertical axis, and the transfer rate is on the horizontal axis. The amount of transmitted BER is indicated by the color on the graph, and the control (key) is on the right side of the graph. In this black-and-white representation, the representations for very low and very high error amounts look the same, but the lower error areas in the main image are toward the left of the lightly divided area, while the higher error areas are toward the right. Based on such data, a combination of operating parameters may be selected for the allowed amount of transmitted data, where as usual this will generally involve compromises. For example, if the allowable BER for the desired amount is 10 ^-5 , if maximum speed is the main concern, then V _DD would be taken to be about 3.1-3.2V, allowing a transfer rate of about 170-180Mb/s. If power consumption is a more important consideration, a lower value of V _DD can be used, say 2.8V, which will then allow about 150Mb/s transfer rate for the same transfer BER. If the BER assigned to the transmitted signal is reassigned to a different value based on eg how much the memory has cycled or just the combined contribution to the BER is approaching the maximum capability of the system, then the bus system's BER can then be adjusted by the controller based on this data operating parameters.

Thus, after calibrating the system by capturing data at various output drive impedances, slew rates, line capacitances, temperatures, etc. represented in the simulation graph, the memory system can operate according to various conditions. For example, given a desired transfer BER, the memory system finds and selects the optimum data bus voltage, data transfer rate, output drive impedance, and slew rate. (This data from the calibration process can be kept in non-volatile memory or in memory space (RAM) in the controller circuit.) For example, it can choose the lowest data bus voltage, highest data transfer rate and the ultimate output drive impedance. In another example, given a specific combination of data bus voltage, data transfer rate, output drive impedance, slew rate, line capacitance, and temperature, what BER can be expected from a memory system. Alternatively, the memory system can choose operating conditions that balance all factors—data bus voltage, data transfer rate, output drive strength, and transfer BER.

Because the design of the I/O buffers in the controller and the memory device may be different, the optimal read and write performance of the memory system can be determined separately. In addition to differences due to different memory system designs, there will also be differences for individual instances of the same device due to process variations and differences in operating conditions. To account for device aging, changes in operating conditions, etc., the calibration process may also be repeated. For example, an initial calibration may be performed at test time prior to shipment of the device, and then the controller may recalibrate the system periodically or in response to, for example, period cycles, erroneous results, significant changes in operating conditions, and the like. Thus, in addition to changes in the proportion of total errors assigned to the transmitted signal, the corresponding operating parameters for a given assignment can be changed dynamically.

As mentioned above, performance can be optimized during both read and write transactions. Returning to FIG. 15 , for performance optimization during memory reads, at 705 the system tops up the transfer rate of the data pattern being written into the data latch register of the memory device to maximize the integrity of the transfer of the data pattern. For example, at a transfer rate of 10MHz, it will take 1.6ms to fill a 16kb data latch register. At 709 and 711, the system measures the transfer BER incurred during a read operation, where the I/O of the memory device is the driver and the controller is the receiver. The graph data is then simulated to show the relationship between the I/O voltage and the read frequency of the memory device.

For performance optimization during memory writes, at 705 the system varies the voltage and transfer rate of the data pattern being written into the data latch register of the memory device. At 709, the system will then slow down the transfer rate of the data from the memory device to the controller to prevent the injection of additional bit errors through the signal link. The measured transmit BER is then the transmit BER incurred during the write operation in 705 . The simulation graph data thus represents the relationship between the I/O voltage of the controller and the write frequency.

So far, the various aspects presented herein have been presented in the context where this is simply a single bus between a controller circuit and a single memory circuit. However, a memory system can include multiple devices with multiple data topologies, and when multiple buses are present, the interaction between these buses can lead to additional sources of error. The techniques herein may provide the ability to offset each signal link within the data bus in the background interface to a specified resolution, eg 100 ps. Such offset capability can be introduced by a controller or memory in the driver or receiver. Introducing skew into the data bus allows the system to compensate for length mismatches of the signal lines in the PCB or packaging substrate. Introducing skew can reduce the impact of near-end and far-end crosstalk in the background interface, thereby reducing the transmit BER. Two types of crosstalk are involved: intra-memory data bus crosstalk; and inter-memory data bus crosstalk. Such crosstalk causes jitter in the data bus. A typical memory system uses a clock sent by the driver to sample each individual signal in the parallel data bus at the same instant. Therefore, an increase in jitter on each signal in the data bus will result in an increase in the transmit BER. Inter-memory data bus crosstalk can be reduced by skewing data across multiple memory data buses so that they are not aligned relative to each other.

Figure 19 is a block diagram illustrating this crosstalk in a memory system where the bus structure uses multiple memory data buses. The memory system includes a controller 901 and a plurality, here four, of memory devices 931-1, 931-2, 931-1, 931-2, 932-3, 931-4. For each bus 911, they will have one or more IO lines as shown in detail as IO1 through IOX. Prior to entry, these individual buses could be various numbers of IO lines operating in parallel, serial, or combinations of these for transferring data. Such multi-bus arrangements are commonly implemented in SSD type devices (see for example US Patent 7,376,034, US Patent 7,763,339 or the paper "A High Performance Controller for NAND Flash-based Solid Sate Disk (NSSD)" Park et al., Samsung, Non-Volatile Symposium on Sexual Semiconductors, 2006, IEEE, NVSMW2000, 21, vol.no., pp. 17-20, Feb. 12-16, 2006) for improved performance, but also found in some memory cards and other memory systems This type of multi-bus arrangement. In addition to this type of intra-memory data bus crosstalk between the IO lines of a given bus, there will now also be inter-memory data bus crosstalk signals on different word lines. Given a certain combination of data bus voltage, transfer rate, temperature, output drive impedance, slew rate, line capacitance, and power dissipation when combined with the use of the PRBS pattern and pseudo-loopback mode described above, one can be sure to produce the least crosstalk and thus The best offset that yields the lowest transmit BER.

The various aspects presented herein provide the lowest cost solution for optimizing backend interface performance in the presence of various signal integrity issues. Performance can be improved as described by dynamically allocating "unused" ECC capacity to transport processing. As noted above, some memory systems use a type of "strong" ECC that exploits the properties of multi-state memory devices, in which case the error correction capabilities that are conveyed for use with the transmission channel may not be conveyed in a 1-to-1 manner . It should also be noted that although memory systems incorporate ECC to compensate for data errors, commands are generally not equally equipped, and memory devices will generally not accept commands with errors, so that while errors may be intentionally allowed in data transfers, for command This will also not exist. Thus, while providing these mechanisms may allow higher transfer rates for data, slower, safer settings for transfer rates (or other parameters) may be incorporated so as not to cause errors for control signals.

in conclusion

The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best illustrate the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use intended . It is intended that the scope of the invention be defined by the claims appended hereto.

Claims (66)

1. A method of operating a non-volatile memory system comprising: a controller circuit with a memory interface; a memory circuit with an array of non-volatile memory cells and a controller interface; and a bus structure, connected to the memory interface of the controller circuit and the controller interface of the memory circuit, for transferring data and commands between the controller circuit and the memory circuit, wherein the memory system is tolerant from A first non-zero cumulative error amount of data transferred from the controller to be written to the memory array until the data is received at the controller after being subsequently read back from the memory array, the method comprising: allocating, by the controller circuit, a first non-zero portion of a first error amount to data transfers between the controller circuit and the memory circuit via the bus structure, the remainder of the first error amount being allocated to all writing, storing and reading data on the memory circuit; and A transfer characteristic between the controller circuit and the memory circuit is set by the controller circuit to operate to tolerate up to a first fraction of errors. 2. The method of claim 1, wherein said transfer characteristic comprises a voltage magnitude of said bus structure. 3. The method of claim 1, wherein said transfer characteristic comprises a data transfer rate on said bus structure. 4. The method of claim 1, wherein the transfer characteristic comprises signal drive strength. 5. The method of claim 1, wherein said transfer characteristic comprises a signal slew rate. 6. The method of claim 1, wherein the memory system includes error code and correction (ECC) circuitry, and the first error amount is based on a capability of the ECC circuitry. 7. The method of claim 6, wherein the ECC circuit is on said controller circuit. 8. The method of claim 6, further comprising: receiving the data from a host at the controller circuit; Generate a corresponding ECC code for the data; transferring the data and the corresponding ECC code from the controller circuit to the memory circuit over the bus structure according to the transfer characteristic; and The data received at the memory circuit and the corresponding ECC code are then written to the array of memory cells. 9. The method of claim 1, further comprising: subsequently reallocating, by the controller circuit, a second portion of the first error amount to data transfers between the controller circuit and the memory circuit via the bus structure; and A transfer characteristic between the controller circuit and the memory circuit is set by the controller circuit to operate to tolerate up to the second portion of errors. 10. The method of claim 9 , wherein the controller circuit reallocates the erroneous portion from the first amount to the second amount in response to a number of program-erase cycles experienced by the memory circuit. quantity. 11. The method of claim 9 , wherein in response to an amount of errors detected in data read back from the memory array, the controller circuit reallocates the portion of the errors from the first amount to the second amount. 12. The method of claim 1, wherein said memory system maintains values for one or more operating parameters of said bus structure and communications between said controller circuit and said memory circuit via said bus structure Correspondence between resulting error quantities of data transmissions, wherein setting said transmission characteristics comprises: A value is selected, by the controller circuit, for the one or more operating parameters based on the correspondence. 13. The method of claim 12 , wherein the correspondence is for a plurality of operating parameters, and selecting values for the plurality of operating parameters comprises allowing up to a first fraction of errors according to one or more predetermined performance criteria Selecting among multiple combinations of the multiple parameters. 14. The method of claim 13, wherein said operating parameters include a voltage magnitude of said bus structure and a data transfer rate on said bus structure. 15. The method of claim 13, wherein said operating parameters include signal drive strength. 16. The method of claim 13, wherein said operating parameter includes a signal slew rate. 17. The method of claim 12, further comprising: The correspondence is established by the controller circuit prior to selecting the value for the one or more operating parameters. 18. The method of claim 17, wherein establishing a correspondence comprises: For each of said values of an operating parameter, transmitting a known pattern of data from said controller circuit to said memory circuit and back over said bus structure without writing the data to a non-volatile memory cell array, and compares the data received back at the controller circuit with the transmitted data pattern. 19. The method of claim 17, wherein said memory system comprises a plurality of memory circuits, and said bus structure comprises a corresponding plurality of buses whereby each memory circuit is respectively connected to a controller circuit, and wherein said control The converter circuit establishes the correspondence including determining crosstalk errors between the buses. 20. A method of operating a non-volatile memory system having a controller circuit and a memory circuit comprising an array of non-volatile memory cells, the method comprising: Transmission error calibration is performed by the controller circuit by processing each of a plurality of values of each of one or more operating parameters of a bus structure connecting the controller to the memory circuit, the processing comprising: transmitting a data set of known data pattern from the controller to the bus structure via a transmission circuit on the controller; receiving a data set from the bus structure via a receive circuit on the memory circuit; storing the received data set in a buffer memory on said memory circuit; transferring the data set stored in the buffer memory on the memory circuit to the bus structure via a transfer circuit on the memory circuit without writing it to the array; receiving a data set from the bus structure via a receiving circuit on the controller; performing a comparison of the received data set with a data set of known pattern; and Based on the comparison, determining an error amount associated with the transmission process for the one or more parameters used; and The memory system is then operated to allow a first non-zero amount of error in the data transfer between the controller circuit and the memory circuit, wherein the controller circuit calculates the transfer error based on the determined associated error amount A calibration process selects values for the operating parameters. 21. The method of claim 20, wherein said operating parameters include voltage magnitudes of the bus structure. 22. The method of claim 20, wherein said operating parameter includes a data transfer rate on the bus structure. 23. The method of claim 20, wherein said operating parameters include signal drive strength. 24. The method of claim 20, wherein said operating parameter includes a signal slew rate. 25. The method of claim 20, further comprising: The memory system is then operated to allow a second amount of error in data transfer between the controller circuit and the memory circuit, wherein the controller circuit calibrates according to the transfer error based on the determined associated amount of error Handle to select the value of the action parameter. 26. The method of claim 20, further comprising: The transmission error calibration process is then redone. 27. The method of claim 20, wherein after the transmission error calibration process is performed, the memory system stores the results thereof in non-volatile memory. 28. The method of claim 20 , wherein said transmission error calibration is performed for a plurality of operating parameters, and said controller circuit allows up to a first amount of error for the plurality of operating parameters according to one or more predetermined performance criteria. Choose between multiple combinations. 29. The method of claim 20, wherein said memory system comprises a plurality of memory circuits, and said bus structure comprises a corresponding plurality of buses whereby each of said plurality of memory circuits is respectively connected to said controller The circuit, and wherein transmitting a data set of a known data pattern includes transmitting data for determining bus crosstalk errors. 30. A non-volatile memory system comprising: Controller circuitry, including memory interface and logic circuitry; memory circuits, including arrays of non-volatile memory cells, controller interfaces, and logic circuits; a bus structure connected to the memory interface of the controller circuit and the controller interface of the memory circuit for transferring data and commands between the controller circuit and the memory circuit; and a feedback processing circuit connected to a logic circuit of one of the controller circuit and the memory circuit to receive information on an amount of error due to the transmission during data transfer between the controller circuit and the memory circuit , and connected to one or both of the memory interface and the controller interface to adjust a characteristic of a transfer between the controller circuit and the memory circuit in response to the error amount. 31. The non-volatile memory system of claim 30, wherein said transfer of data is from said controller circuit to said memory circuit. 32. The non-volatile memory system of claim 30, wherein said transfer of data is from said memory circuit to said controller circuit. 33. The non-volatile memory system of claim 30, wherein the logic circuit of each of the controller circuit and the memory circuit includes a hash value generator, wherein in a transfer process from a first of said memory circuit and said controller to a second of them, the first transfers a data set over said bus structure and is transferred by said first logic circuit from The data set produces a first hash value, and the second one receives the data set and the first hash value from the bus structure, and the logic circuit of the second one based on the received the data set generates a second hash value derived from the data set; and Wherein the logic circuit of the second of the memory circuit and the controller further includes a comparison circuit connected to receive a second hash value and compare the received first hash value with the second hash value A comparison is made to the value, and the error amount is based on the result of that comparison. 34. The non-volatile memory system of claim 33, wherein the circuits used to generate the respective hash values on the memory circuit and the controller are identical. 35. The non-volatile memory system of claim 33, wherein the circuits used to generate the respective hash values on the memory circuit and the controller are not identical. 36. The non-volatile memory system of claim 30 , wherein the comparing determines whether the first and second hash values are equal, and in response to determining that the first and second hash values are not equal, the memory circuit and The logic of the circuitry of a second of the controllers further quantifies the amount of error. 37. The non-volatile memory system of claim 30, wherein the feedback processing unit is formed on the same integrated circuit as the controller. 38. The non-volatile memory system of claim 30, wherein the feedback processing unit is formed on the same integrated circuit as the memory circuit. 39. The non-volatile memory system of claim 30, wherein the feedback processing unit is formed on an integrated circuit separate from both the controller and the memory circuit. 40. The non-volatile memory system of claim 30, wherein the memory circuit is formed from a plurality of integrated circuits, each integrated circuit including an array of non-volatile memory cells, a controller interface, and a logic circuit. 41. The non-volatile memory system of claim 40, wherein each integrated circuit of said memory circuit is connected to said controller by a different bus. 42. The non-volatile memory system of claim 40, wherein one or more of the integrated circuits of the memory circuits are connected to the controller by a shared bus. 43. The non-volatile memory system of claim 40, wherein characteristics of transfers between the controller and the plurality of integrated circuits of the memory circuit can be adjusted independently. 44. A method of operating a non-volatile memory system comprising a controller circuit and a non-volatile memory circuit, the method comprising: generating a first hash value from the data set in logic circuitry on a first of said controller circuitry and memory circuitry; transmitting the data set and the first hash value to a bus structure via an interface on a first of the controller circuit and the memory circuit; receiving the data set and the first hash value from the bus structure through an interface on a second of the controller circuit and the memory circuit; generating a second hash value based on the received data set in logic circuitry on a second of said controller circuitry and memory circuitry; comparing the received first hash value with the second hash value at a second of the controller circuit and the memory circuit; and Based on a comparison of the received first hash value and the second hash value by logic circuitry on a second of the controller circuit and memory circuit, determining whether to modify the Characteristics of data transfer between memory circuits. 45. The method of claim 44, wherein a first of said controller circuit and said memory circuit is a controller circuit. 46. The method of claim 44, wherein a first of said controller circuit and said memory circuit is a memory circuit. 47. The method of claim 44, wherein logic circuits on said memory circuit and said controller for generating respective hash values are identical. 48. The method of claim 44, wherein logic circuits on said memory circuit and said controller for generating respective hash values are not identical. 49. The method of claim 44, wherein the characteristic of data transfer between said controller circuit and said memory circuit includes a frequency at which data is transferred. 50. The method of claim 44, wherein a characteristic of data transfer between said controller circuit and said memory circuit includes a clock frequency of said bus structure. 51. The method of claim 44, wherein a characteristic of a data transfer between said controller circuit and said memory circuit includes a slew rate used in said transfer. 52. The method of claim 44, wherein the characteristic of data transfer between said controller circuit and said memory circuit includes an interface voltage at which data is transferred. 53. The method of claim 44, wherein the characteristic of data transfer between said controller circuit and said memory circuit includes a drive strength for transferring data. 54. The method of claim 44, wherein the hash value is established based on a cyclic redundancy check. 55. The method of claim 44, wherein the hash value is established based on an error correction code. 56. The method of claim 44 , wherein prior to transmitting the data set and the first hash value through an interface on a first of the controller circuit and the memory circuit, the characteristics of the data transfer are determined by The settings are an initial set of values determined from a lookup table based on the bus structure and characteristics of the memory circuits of the memory system. 57. The method of claim 44 , wherein prior to transmitting the data set and the first hash value through an interface on a first of the controller circuit and the memory circuit, the characteristics of the data transfer are determined by is set to an initial set of values determined from a lookup table based on the one or more parameters. 58. The method of claim 44 , wherein prior to transmitting the data set and the first hash value through an interface on a first of the controller circuit and the memory circuit, the characteristics of the data transfer are determined by set to an initial set of values determined from the quality of previous data transfers between the controller circuit and the memory circuit. 59. The method of claim 58, wherein the one or more parameters include a supply voltage level. 60. The method of claim 58, wherein the one or more parameters include temperature. 61. The method of claim 58, wherein one or more parameters include processing values for one or both of the controller circuit and the memory circuit. 62. The method of claim 44, generating and transmitting a first hash value in response to a request from one of said controller circuit and said memory circuit. 63. The method of claim 44, further comprising: In response to said determining, altering characteristics of data transfers between said controller circuit and said memory circuit, wherein with respect to transfers from said controller circuit to said memory circuit and from said memory circuit to said control circuit Transmitter circuit changes symmetrically. 64. The method of claim 44, further comprising: In response to said determining, altering characteristics of data transfers between said controller circuit and said memory circuit, wherein with respect to transfers from said controller circuit to said memory circuit and from said memory circuit to said control circuit Transmitter circuit changes asymmetrically. 65. A method of operating a non-volatile memory system comprising a controller circuit and a memory circuit comprising an array of non-volatile memory cells, the method comprising: transferring a data set from a buffer memory on a controller through a transmission circuit on the controller to a bus structure connecting the controller to the memory circuit; receiving a data set from the bus structure via a receive circuit on the memory circuit; storing the received data set in a buffer memory on said memory circuit; transferring a data set stored in a buffer memory on the memory circuit to the bus structure via a transfer circuit on the memory circuit without writing to the array; receiving a data set from the bus structure via a receiving circuit on the controller; subsequently storing the received data set in buffer memory on said controller; A characteristic of the data transfer between the controller circuit and the memory circuit is then adjusted based on the amount of error of the data set received and stored in a buffer memory on the controller. 66. The method of claim 65, wherein the amount of error is determined by an ECC circuit on the controller.

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