CN103036685A - DP83849C-based AFDX interface converter - Google Patents

Abstract

The invention discloses an interface converter for an avionics device and an AFDX network. As the backbone network protocol of civil aircrafts, the AFDX has the characteristics of high band width, high error-tolerant rate and high reliability; as the civil aircrafts use a large amount of avionics devices with ARINC429 protocol interfaces, the access of the avionics devices into the AFDX network becomes more important. The invention designs an interface converter based on FPGA (Field Programmable Gate Array), DP83849C and HI3585; the converter mainly comprises three parts of an FPGA core circuit and a peripheral circuits, a DP83849C-based AFDX protocol interface circuit and an HI3585-based 429 protocol interface circuit, wherein the FPGA core circuit adopts a spartan6 serial chip for finishing the analysis of data frames and the data interaction between 429 and AFDX; the AFDX interface circuit adopts DP83849C as a physical layer chip for connecting the converter wit the AFDX network; and the 429 interface circuit adopts an HI3585 chip for finishing the data analysis of 429 protocol and the framing. The interface converter, designed by the invention, is used for accessing the avionics and electric devices into the aircraft backbone network, is convenient to realize, and is high in reliability.

Description

AFDX interface convertor based on DP83849C

One, technical field

The invention provides a kind of Aerial Electronic Equipment and AFDX network interface converter design of ARINC429 interface, this design is for all adopt the terminal equipment access backbone network of 429 interfaces that significant application value is arranged in the civil aircraft.

Two, background technology

At present, the information transmission bus ARINC429 of extensive use in the avionics system information transmission network of aircarrier aircraft, its bus transfer rate only is 100kb/s, can only realize point-to-point communication mode, can not satisfy the scale demand of modern avionics system, and be difficult to guarantee that the transmission information kind increases rear requirement to high speed data transfer.AFDX is that Airbus France is complicated in order to solve the inner traditional data communication network wiring of commercial aircraft, and line is heavy excessive, a kind of novel aeronautical communications network that forms of improving at commercial Basic Ethernet that communication speed proposes slowly.Keeping traditional ethernet at a high speed in (100Mb/s), the characteristics such as general and low-cost, increasing and be used for guaranteeing network reliability and deterministic special mechanism.Because novel civil avionics equipment uses the ARINC429 interface in a large number, for making such Aerial Electronic Equipment access AFDX network, the research of carrying out interface convertor seems very necessary.

Three, summary of the invention

1, goal of the invention: the purpose of this invention is to provide a kind of interface convertor that can finish between long-range ARINC429 end system and the AFDX network, this interface is so that tradition 429 equipment on the civil aircraft can carry out real time communication with the AFDX network.

2, technical scheme: in order to reach the foregoing invention purpose, the present invention proposes a kind of based on FPGA 429 with the design of AFDX protocol interface transducer, this interface convertor mainly comprises AFDX protocol interface circuit, ARINC429 protocol interface circuit, core FPGA processing module and relevant controlling and driving circuits.

429 and AFDX signal converter circuit design proposed by the invention is based on the AFDX physical layer block of ethernet transceiver chip DP83849C, the binary channels of this chip shares same group of management interface (MDC, MDIO), and address wire and receive data line are multiplexing, compare with AFDX physical chip LXT973 commonly used and have saved the FPGA resource and be easy to configuration.This physical chip is connected with management interface (MDC, MDIO) by standard MII interface with the MAC nuclear of FPGA, realizes the physical layer of AFDX agreement, and wherein the MII interface is used for transfer of data between the two; Management interface is used for work, the reading state of control chip and enables interrupting.The form with software in FPGA such as AFDX protocol data link layer, IP layer, UDP layer realizes, thus the AFDX agreement of complete.

ARINC429 protocol interface circuit adopts HI3585 as agreement and drives chip, and this chip internal is integrated, and 429 protocol contents and output carry 429 bus drivers, and its output can be directly and 429 network connections.Utilize address, data wire to communicate by letter with traditional 429 protocol chips and compare, HI3585 communicates by letter with FPGA by four line SPI interfaces, has improved communication speed and has simplified control strategy.By the HI3585 internal register is configured, determine speed, the label configuration of 429 buses etc.

The FPGA processing module comprises spartan6 Series FPGA and relevant controlling and driving circuits, comprising: based on the clock module of CDCE913, be mainly used in providing the clock reference of the inner microblaze processor of FPGA work; Based on the power module of TPS74701, be used for to input 5V voltage and be converted into 3.3V, 1.8V, 1.2V for FPGA and other chips; Based on the DDR data memory module of MT46H16M32LF, be used for program carry out with and the AFDX protocol stack resolve; Based on the FLASH download module of N25Q128A, be used for configuration FPGA and storage file; Based on the serial ports of CP2102-USB debugging module, the RS232 signal that is used for debug process is exported converts usb signal to, thus the development board of realizing the present invention's design and mobile computing device alternately.

The operation principle of circuit topology of the present invention is as follows: because AFDX is based on the Generation of Airborne bus of commercial Ethernet, meet the OSI seven layer model, and ARINC429 can only realize point-to-point communication mode as traditional airborne-bus, host-host protocol is relatively simple, between the two can not direct communication, and consider owing to also remain with a large amount of ARINC429 application apparatuss in the novel A380 aircraft, seem very necessary for these ARINC429 bus apparatus dispose respective communication terminals with access AFDX network.The present invention finishes ARINC429 bus and AFDX backbone network interactive interface based on FPGA by the research to ARINC429 and ARINC664 agreement, has realized the conversion between ARINC429 physical layer and the ARINC664 physical layer.

For making system safety normal operation of the present invention, usually also need to design the auxiliary circuits such as some control circuits, delay circuit, overvoltage crowbar.

3, beneficial effect: describe above comprehensive, the AFDX Interface design circuit following features based on DP83849C of the present invention: this circuit has been realized the conversion between ARINC429 physical layer and the ARINC664 physical layer; 429 physical layers connect employing SPI interface, have simplified control logic and have improved efficient; 429 agreements and driving are integrated in the same chip, have shortened the construction cycle; The AFDX agreement is mainly realized by software, is easy to debugging and revises.

Four, description of drawings

Accompanying drawing 1 is the electric circuit constitute structure of the present invention

Accompanying drawing 2 (a) is to realize based on the AFDX function of DP83849C (b)

Accompanying drawing 3 is to realize based on the ARINC429 hardware of HI3585

Accompanying drawing 4 is the fpga core circuit diagram

Accompanying drawing 5 is that the software of interface convertor is realized framework map

Designation in the above-mentioned accompanying drawing: FPGA adopts spartan6, transformer adopting TG110-E050N5, and RJ45 adopts mini RJ45.

Five, embodiment

Circuit of the present invention (as shown in Figure 1) forms structure and comprises: DP83849C chip (AFDX physical layer) and FPGA interface circuit (as shown in Figure 2), FPGA and HI3585 chip (429 protocol section) interface circuit (as shown in Figure 3), FPGA operating circuit (as shown in Figure 4), control circuit and associated driver circuitry.Because FPGA adopts GBA to encapsulate and AFDX is higher to the requirement of signal, so adopt multiple sliding cover; And 429 semaphore requests are relatively low, adopt double panel structure, and both connect by isometric holding wire.The main circuit design process of hardware:

DP83849C chip and FPGA interface circuit mainly are responsible for the circulation of AFDX formatted data is changed into the signal of telecommunication and passes through Double-strand transmission.The FPGA operating circuit is mainly finished the self-starting of FPGA, and the AFDX procotol is processed and to the control of ARI NC429 protocol groups chip.FPGA and HI3585 chip interface circuit are finished the transfer of data of data between FPGA and 429 buses. and the data in the FPGA are converted to the ARINC429 data format of standard, and send to bus and communicate by letter with the aviation electronics model system.

DP83849C is connected as shown in Figure 2 with FPGA's, be described as follows: chip is connected by A, B two channel standard MII interfaces with FPGA, transmitting network data under the 25MHz clock control, data in FPGA inside by the MAC nuclear control, mutual by AXI bus and FPGA internal processor.The initialization of chip can be finished by some specific pin, also can be by FPGA by management interface (MDC, MDIO) configuration.AN_EN sets to 0, and AN_0 and AN_1 put 1 and force chip operation at the 100Mbps of AFDX protocol requirement, full-duplex mode, and can not select the Auto-matching pattern; The passive crystal oscillator of the external 25MHz of X1, X2; Difference output needs to draw 49.9 ohm of build-out resistors.

The HI3585 pin configuration is connected as shown in Figure 3 with FPGA's, be described as follows: RINB, RINA and RINB-40, RINA-40 are respectively as one group of 429 differential signal input, can directly access 429 buses, rear one group of pin has increased the 40K pull-up resistor in some special occasions lightning protection; In like manner, AOUT, BOUT and AOUT27, BOUT27 are respectively the output of one group of 429 differential signal.During chip operation, can only select one group of use in two groups of input and output pins.This chip is connected by four line SPI interfaces with FPGA, and FPGA is main device, and HI3585 is from device, according to SCK clock swap data.ACLK receives the 1MHz clock signal from FPGA output, and TFLAG and RFLAG are used for indicating chip internal and receive and the state that sends buffering.To notice when powering on that first order and two groups of pins can only be used one group.

Owing to be used in the signal conversion occasions, so do not consider the problem of label and parity check, FPGA sends 8 write control register orders (0x10) and 16 bit data positions (0x2820) thereby enables chip operation at 100kps; Enable the 1MHz external clock; Do not use label, check bit sum SDI; Use normal 429 data order; Enable bus driver; Transmission is controlled by CS; Thereby TFLAG and RFLAG set high the conducting light-emitting diode when send and receive FIFO is sky.Thereby the data that will send by data transmission instruction 0x0E after chip configuration is finished write the transmission buffering area.Read 429 data that receive by sending the 0x08 instruction.

FPGA in house software and workflow as shown in Figure 5, operating system is selected the Xilkernel that supports the XILINX FPGA of company, adopts round robin, does not set priority under this round robin, operating system travels through all tasks, carries out in order.The LWIP agreement of using in the design is the open source code ICP/IP protocol stack that a cover of Switzerland computer science institute exploitation is used for embedded system.

The AFDX agreement mainly realizes by software, and is in addition perfect on the basis of LWIP agreement, practical function.To be received as example, after decoding via physical chip DP83849, the AFDX data are transferred to the MAC nuclear of FPGA inside by the MII interface, and MAC nuclear receives the AFDX data and can operate data according to the lwip agreement.The Ethernet head of AFDX frame has defined virtual link, and the FPGA program number is processed the data of requirement passage by virtual link relatively.In data link layer, at first relatively application layer data if this data segment sequential bits is continuous, then carries out Redundancy Management, such as discontinuous then error of transmission, abandons this frame.In the Redundancy Management link, read the sequential bits of next frame, if identical with the sequential bits of a upper frame, represent that this frame is redundant frame, otherwise mistake.The frame that meets above-mentioned requirements enters the IP layer, and the IP layer has mainly defined source address and the destination address of frame, then enters the UDP layer, and this layer mainly defined the port numbers of frame, finally obtains AFDX valid data section.

Above-mentioned said AFDX data are stored in the buffer memory, restart HI3585, at first carry out the 0x01 instruction and carry out the software reset, empty input into/output from cache, according to above said transmission 0x0E instruction, the AFDX application layer data that is stored in the buffer memory is exported 429 formatted datas again.Finish the conversion of AFDX and 429 signals.

Claims (3)

1. 429-AFDX bus interface transducer proposed by the invention, it is characterized in that this circuit comprises AFDX interface section, 429 interface processing sections and FPGA related peripheral circuit part, wherein the AFDX interface section is connected with FPGA internal mac nuclear by MI I mode based on the DP83849C chip; 429 interface sections are connected with the SPI nuclear of FPGA by common SPI four-wire interface based on the HI3585 processing unit; FPGA adopts the spartan6 family chip, and peripheral circuit comprises: clock division, voltage transitions, FLASH, SDRAM, serial ports etc., be connected with FPGA by the desired interface of respective chip, thus the system of complete.

2. interface convertor as claimed in claim 1 is characterized in that the 429 protocol chip HI3585 that use adopt the SPI interface, are convenient to design and built-in 429 bus drivers; The employing of DP83849C can make AFDX binary channels interface share one group of management pin, and the binary channels configuration synchronization is high.

3. interface convertor as claimed in claim 1 is characterized in that adopting unitary core processor FPGA, and this processor is finished all software functions that comprise interface chip management, protocal analysis and processing, data transaction and register configuration etc.

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