CN103022043B - P+ single polycrystalline and the non-volatility memory and preparation method thereof not being lightly doped - Google Patents
P+ single polycrystalline and the non-volatility memory and preparation method thereof not being lightly doped Download PDFInfo
- Publication number
- CN103022043B CN103022043B CN201210579974.0A CN201210579974A CN103022043B CN 103022043 B CN103022043 B CN 103022043B CN 201210579974 A CN201210579974 A CN 201210579974A CN 103022043 B CN103022043 B CN 103022043B
- Authority
- CN
- China
- Prior art keywords
- type
- region
- barrier layer
- doped region
- interarea
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 120
- 239000004065 semiconductor Substances 0.000 claims abstract description 53
- 239000003990 capacitor Substances 0.000 claims abstract description 34
- 238000003860 storage Methods 0.000 claims abstract description 7
- 230000004888 barrier function Effects 0.000 claims description 121
- 239000000463 material Substances 0.000 claims description 11
- 230000005611 electricity Effects 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 2
- 238000002955 isolation Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 24
- 238000000034 method Methods 0.000 description 18
- 239000012535 impurity Substances 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 12
- 230000008569 process Effects 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000013078 crystal Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 241000790917 Dioxys <bee> Species 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 150000001768 cations Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 150000001450 anions Chemical class 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention relates to a kind of P+ single polycrystalline architecture with selector transistor and without lightly doped region and the embedded non-volatile memory body and preparation method thereof mutually compatible with CMOS technology, it includes semiconductor substrate and memory body cell, and memory body cell includes PMOS transistor, control capacitor and the PMOS selector transistor of no light doped region；Gate dielectric layer is deposited on the surface of semiconductor substrate, gate dielectric layer is equipped with floating gate electrode, and floating gate electrode covers and run through corresponding gate dielectric layer above the PMOS transistor and control capacitor of no light doped region, and the two sides of floating gate electrode are deposited with lateral protection layer；The PMOS transistor for not having light doped region includes the first n-type region and p-type source area and p-type drain region, and control capacitor includes the second p type island region domain and the first P-doped zone domain and the second P-doped zone domain.Structure of the invention is compact, can be compatible with CMOS technology, reduces chip cost, improves the security reliability of storage.
Description
Technical field
It is especially a kind of with selector transistor the present invention relates to a kind of non-volatility memory and preparation method thereof
P+ single polycrystalline architecture and without lightly doped region and the embedded non-volatile memory body mutually compatible with CMOS technology and its system
Preparation Method belongs to the technical field of integrated circuit.
Background technique
System on chip (SoC) is applied, it is many functional blocks to be integrated into an integrated circuit.Most common
Upper system includes a microprocessor or microcontroller, static random access memory (SRAM) module, non-volatility memory
And the logical block of various specific functions.However, the process in traditional non-volatility memory, this is usually using gatestack or divides
Grid storage unit is split, it is incompatible with traditional logic process.
Non-volatility memory (NVM) technique and traditional logic process are different.Non-volatility memory (NVM)
If technique and traditional logic process are combined, technique will be made to become an increasingly complex and expensive combination；Due to SoC
The typical usage of the nonvolatile memory of application is to be related to whole chip size small, therefore this way is undesirable
's.Simultaneously as the working principle of existing non-volatility memory make be written data be easily lost, influence using it is reliable
Property.For the embedded non-volatile memory body of system on chip (SoC) application, capacity is not generally very greatly, just tens yet
Between a bit and several megabits.In this case, the area specific gravity that peripheral control route accounts for will be very big.In order to make periphery
Control circuit surface product does the simplification small, control line route road will be done.In bit, there are the transistor of a selector, meeting
The control line appearance of a street of periphery is allowed easily to design and simplify.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, a kind of P+ single polycrystalline and it is not lightly doped non-
Volatile memory and preparation method thereof does not have the PMOS transistor of lightly doped region not have lightly doped region, the write-in made
Voltage when thermoelectron reduces, and improves designability when design circuit, compact-sized, can be compatible with CMOS technology, reduces
Chip cost improves the security reliability of storage.
According to technical solution provided by the invention, the P+ single polycrystalline and the non-volatility memory not being lightly doped,
Including semiconductor substrate；Top in the semiconductor substrate is equipped with several memory body cells for storage, the memory body
Cell includes the PMOS transistor of not lightly doped region, controls capacitor and PMOS selector transistor；It is described not to be lightly doped
It is mutually isolated by the field areas of dielectric in semiconductor substrate between the PMOS transistor and control capacitor in region；Semiconductor substrate
Surface on be deposited with gate dielectric layer, the gate dielectric layer is equipped with floating gate electrode, and the floating gate electrode, which covers and runs through, not to be had
Corresponding gate dielectric layer above the PMOS transistor and control capacitor of lightly doped region, the two sides of floating gate electrode are deposited with side guarantor
Sheath, lateral protection layer cover the side wall of floating gate electrode；The PMOS selector transistor and the not PMOS of lightly doped region
Transistor is concatenated connection；PMOS crystal of the p-type source area of the PMOS selector transistor with not lightly doped region
The p-type drain region of the not lightly doped region of pipe 210 is connected；The gate electrode of the PMOS selector transistor is not with mixing gently
Floating gate electrode in the PMOS transistor in miscellaneous region is independent of each other；The floating gate electrode of the PMOS selector transistor is custom
The WL of title；On the PMOS transistor of the not lightly doped region includes the first n-type region and is located in first n-type region
Portion does not have the p-type drain region of the p-type source area of lightly doped region with not lightly doped region, and control capacitor includes the second p type island region
Domain and the first P-doped zone domain positioned at second p type island region domain internal upper part and the second P-doped zone domain；First P-doped zone
Domain, the second P-doped zone domain, p-type source area and p-type drain region are corresponding with the floating gate electrode of top, and respectively with it is corresponding
Gate dielectric layer and field areas of dielectric are in contact, and PMOS selector transistor is including the first n-type region and is located at first N-type
The p-type source area of region internal upper part and p-type drain region.
The material of the semiconductor substrate includes silicon, and semiconductor substrate is P conduction type substrate or N conduction type substrate.
When the semiconductor substrate is P conduction type substrate, the PMOS transistor and PMOS of the not lightly doped region
Selector transistor passes through the first n-type region above the second n-type region and the second n-type region in P-type conduction type of substrate
It is isolated with P-type conduction type of substrate.The control capacitor transistor passes through the second n-type region in P-type conduction type of substrate
And second the second p type island region domain above n-type region is isolated with P-type conduction type of substrate.
First P-doped zone domain includes the first p-type heavily doped region and the first p-type corresponding with lateral protection layer
Lightly doped region, the first p-type heavily doped region connect after extending from the end of the first p-type lightly doped region with field areas of dielectric
Touching.
Second P-doped zone domain is including the second p-type heavily doped region and in corresponding second p-type of lateral protection layer
Lightly doped region, the second p-type heavily doped region connect after extending from the end of the second p-type lightly doped region with field areas of dielectric
Touching.
The floating gate electrode includes conductive polycrystalline silicon.The gate electrode includes conductive polycrystalline silicon.The gate dielectric layer
Material include silica；The lateral protection layer is silicon nitride or silica.
The preparation method of the P+ single polycrystalline and the non-volatility memory not being lightly doped, the preparation method include
Following steps:
A, semiconductor substrate is provided, the semiconductor substrate includes the first interarea and the second interarea；
B, growth obtains field areas of dielectric in semiconductor substrate；Needed for being carried out on the first interarea of semiconductor substrate
Barrier layer deposition, barrier etch and autoregistration ion implanting, to form the first required N-type region in semiconductor substrate
Domain, the second n-type region, the second p type island region domain；
C, gate dielectric layer is deposited on corresponding first interarea of above-mentioned semiconductor substrate, the gate dielectric layer covers semiconductor
First interarea of substrate；
D, floating gate electrode is deposited on the first interarea of above-mentioned semiconductor substrate and gate electrode, the floating gate electrode are covered in
On gate dielectric layer and on corresponding gate dielectric layer above the second p type island region domain, the first n-type region, the gate electrode is covered in
Above first n-type region on corresponding gate dielectric layer；
E, the 4th barrier layer is deposited on above-mentioned gate dielectric layer, and selectively shelters and etch the 4th barrier layer, removal
4th barrier layer of the corresponding covering floating gate electrode and gate electrode of the first n-type region, the second p-type overlying regions；
F, the autoregistration injecting p-type foreign ion above above-mentioned 4th barrier layer, the top in the second p type island region domain obtain
First p-type lightly doped region and the second p-type lightly doped region, the top in the first n-type region obtain the 5th p-type lightly doped district
Domain, the 6th p-type lightly doped region；
G, above-mentioned 4th barrier layer is removed, and deposits lateral protection material on the first interarea, in floating gate electrode and grid
The two sides of electrode form lateral protection layer；
H, the 5th barrier layer is deposited on above-mentioned first interarea, and selectively shelters and etches the 5th barrier layer, to go
Except the 5th barrier layer of deposit covering corresponding above the second p type island region domain, the first n-type region；
I, the autoregistration injecting p-type foreign ion again above above-mentioned 5th barrier layer, the top in the second p type island region domain
The first p-type heavily doped region and the second p-type heavily doped region are obtained, it is heavily doped that the top in the first n-type region obtains third p-type
Miscellaneous region, the 4th p-type heavily doped region, the 5th p-type heavily doped region and the 6th p-type heavily doped region；
J, the 5th barrier layer on the first interarea is removed.
In the step a, when semiconductor substrate is P conduction type substrate, the step b includes
B1, deposit the first barrier layer on the first interarea of P conduction type substrate, and selectively shelter and etch described in
First barrier layer, N-type impurity ion is injected in autoregistration above the first barrier layer, to obtain the second N-type in semiconductor substrate
Region；
B2, growth obtains field areas of dielectric in semiconductor substrate；
The first barrier layer on b3, corresponding first interarea of the above-mentioned P conduction type substrate of removal, and deposited on the first interarea
Second barrier layer；
B4, selectively shelter and etch the second barrier layer, and above the second barrier layer autoregistration injection N-type impurity from
Son, to form the first n-type region in semiconductor substrate, the first N-type region is located at the top of the second n-type region；
The second barrier layer on b5, corresponding first interarea of the above-mentioned P conduction type substrate of removal, and deposited on the first interarea
Third barrier layer；
B6, selectively shelter and etch third barrier layer, and above third barrier layer autoregistration injecting p-type impurity from
Son, to form the second p type island region domain above the second n-type region.
In the step a, when semiconductor substrate is N conduction type substrate, the step b includes
S1, growth obtains field areas of dielectric in semiconductor substrate；
S2, the second barrier layer is deposited on the first interarea, and selectively shelter and etch the second barrier layer；
N-type impurity ion is injected in s3, the top autoregistration on above-mentioned second barrier layer, in N conduction type substrate
Top obtains the first required n-type region；
The second barrier layer on s4, the first interarea of removal, and third barrier layer is deposited on the first interarea；
S5, selectively shelter and etch third barrier layer, and above third barrier layer autoregistration injecting p-type impurity from
Son, to obtain the second p type island region domain in N conduction type substrate.
4th barrier layer and the 5th barrier layer are silica or silicon nitride.The field areas of dielectric is dioxy
SiClx.
Field dielectric layer in the step b2 and s1 is the electrode gate oxide of the I/O transistor in CMOS technology；Institute
The thickness for stating the electrode gate oxide of the I/O transistor in CMOS technology is usually 7 nanometers.
The P+ single polycrystalline and the non-volatility memory not being lightly doped, also comprising being following several.Described half
Top in conductor substrate is equipped with several memory body cells for storage, and the memory body cell includes no lightly doped region
PMOS transistor, control capacitor and the not no PMOS selector transistor of lightly doped region；Or the memory body cell includes
There is no the PMOS transistor of lightly doped region, not the control capacitor of lightly doped region and not the PMOS selection of lightly doped region
Device transistor；Or the memory body cell includes the PMOS transistor of not lightly doped region, controls electricity without lightly doped region
Hold and PMOS selector transistor.
Advantages of the present invention: at least one memory body cell of setting, memory body cell include without light in semiconductor substrate
The PMOS transistor of doped region controls capacitor and PMOS selector transistor, not the PMOS transistor of lightly doped region and
It is mutually isolated by field areas of dielectric to control capacitor, not the PMOS transistor of lightly doped region and PMOS selector transistor
It is to be connected in series；Floating gate electrode and gate electrode are set on the gate dielectric layer of semiconductor substrate, and the floating gate electrode connection is not through
The gate dielectric layer of PMOS selector transistor is arranged in the PMOS transistor and control capacitor, the gate electrode for having lightly doped region
On；When the gate electrode of PMOS selector transistor is located at 0v and when floating gate electrode and the not PMOS transistor of lightly doped region
Not having voltage difference between the p-type source area of lightly doped region and not the p-type drain region of lightly doped region is analog value and p-type
When voltage difference is analog value between source area and p-type drain region, data can be written into floating gate electrode；Or it will be in floating gate electrode
Data erasing, flow through the electric current of the not PMOS transistor of lightly doped region by detecting and can know that volume locating for floating gate electrode
Journey write state or erase status, the entire preparation flow for remembering body cell can be mutually compatible with existing CMOS logic technique, structure
It is compact, it can reduce processing cost, improve the adaptability of nonvolatile memory and CMOS logic circuit；Pass through no lightly doped district
The p-type drain region of the p-type source area of the not lightly doped region of the PMOS transistor internal upper part in domain and not lightly doped region, control
The first P-doped zone and the second P-doped zone of capacitor internal upper part processed enable to write-in data to keep more long, improve non-
The safety and reliability of volatile memory.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the embodiment of the present invention 1.
Fig. 2 is the structural schematic diagram of the embodiment of the present invention 2.
Fig. 3~Figure 13 is the specific implementation process cross-sectional view of the embodiment of the present invention 1, in which: Fig. 3 is P conductive-type of the present invention
The cross-sectional view of type substrate.
Fig. 4 is to obtain the cross-sectional view after the second n-type region.
Fig. 5 is to obtain the cross-sectional view after the areas of dielectric of field.
Fig. 6 is to obtain the cross-sectional view after the first n-type region and third n-type region.
Fig. 7 is to obtain the cross-sectional view behind the second p type island region domain.
Fig. 8 is the cross-sectional view after obtaining gate dielectric layer.
Fig. 9 is the cross-sectional view after obtaining floating gate electrode.
Figure 10 is that autoregistration injection P foreign ion obtains the cross-sectional view after lightly doped region.
Figure 11 is to obtain the cross-sectional view after lateral protection layer.
Figure 12 is that autoregistration injection P foreign ion obtains the cross-sectional view after heavily doped region.
Figure 13 is the cross-sectional view removed behind the 5th barrier layer.
Figure 14~Figure 23 is the specific implementation process cross-sectional view of the embodiment of the present invention 2, in which: Figure 14 is N of the present invention conductive
The cross-sectional view of type of substrate.
Figure 15 is to obtain the cross-sectional view after the areas of dielectric of field.
Figure 16 is to obtain the cross-sectional view after the first n-type region and the second n-type region.
Figure 17 is to obtain the cross-sectional view behind the second p type island region domain.
Figure 18 is the cross-sectional view after obtaining gate dielectric layer.
Figure 19 is the cross-sectional view after obtaining floating gate electrode.
Figure 20 is that autoregistration injection P foreign ion obtains the cross-sectional view after lightly doped region.
Figure 21 is to obtain the cross-sectional view after lateral protection layer.
Figure 22 is that autoregistration injection P foreign ion obtains the cross-sectional view after heavily doped region.
Figure 23 is the cross-sectional view removed behind the 5th barrier layer.
Description of symbols: 200- remembers body cell, 201-P conduction type substrate, the first n-type region of 202-, 203- the
Two n-type regions, 204- third n-type region, the second p type island region 205- domain, the first P-doped zone of 206-, 207- the first p-type heavy doping
Region, the first p-type of 208- lightly doped region, the second P-doped zone of 209-, 210- do not have lightly doped region PMOS transistor,
The second p-type of 212- heavily doped region, 213- do not have the p-type source area of the PMOS transistor 210 of lightly doped region, the field 214- to be situated between
Matter region, 215- gate dielectric layer, 216- floating gate electrode, 216a- gate electrode, 217- lateral protection layer, 219- third p-type heavy doping
Region, 220- control capacitor, 221- do not have the p-type drain region of the PMOS transistor 210 of lightly doped region, the 4th p-type weight of 223-
Doped region, the first interarea of 232-, the second interarea of 233-, the first barrier layer 234-, the second barrier layer 235-, 236- third stop
Layer, the 4th barrier layer 237-, the 5th barrier layer 238-, 239-N conduction type substrate, 243-PMOS selector 230 p-type source electrode
Area, the 5th p-type lightly doped region of 248-, the 5th p-type heavily doped region of 249-, the p-type drain region of 241-PMOS selector, 242-
The 6th p-type heavily doped region of 6th p-type lightly doped region and 243-.
Specific embodiment
Below with reference to specific drawings and examples, the invention will be further described.
Embodiment 1
As shown in Fig. 1 and Figure 13: in order to make non-volatility memory mutually compatible with CMOS logic technique, while energy
Enough that non-volatility memory is enabled to store the longer time, non-volatility memory includes P conduction type substrate 201, and P is led
The material of electric type of substrate 201 is silicon.Top in P conduction type substrate 201 is equipped at least one memory body cell 200, institute
The PMOS transistor 210 that memory body cell 200 includes not lightly doped region is stated, capacitor 220 and PMOS selector crystal are controlled
Pipe 230, deposit is covered with gate dielectric layer 215 on the surface of P conduction type substrate 201, and the gate dielectric layer 215 covers corresponding shape
At the surface of memory body cell 200, P conductive-type is not passed through between the PMOS transistor 210 of lightly doped region and control capacitor 220
Field areas of dielectric 214 in type substrate 201 is mutually isolated, not the PMOS transistor 210 of lightly doped region and PMOS selection
Device transistor 230 is all located in the first n-type region 202, and is concatenated connection, that is, the PMOS selector transistor
230 p-type source area is connected with the p-type drain region of the PMOS transistor 210 of not lightly doped region.On gate dielectric layer 215
It is deposited with floating gate electrode 216, the floating gate electrode 216 is covered on gate dielectric layer 215, and through the no lightly doped region of covering
PMOS transistor 210 and control the corresponding gate dielectric layer 215 of capacitor 220, thus by the PMOS crystal of not lightly doped region
Pipe 210 and control capacitor 220 are connected with each other cooperation.The gate electrode 216a is covered in the gate dielectric layer in the first n-type region 202
On 215.The two sides of the floating gate electrode 216 and gate electrode 216a are covered with lateral protection layer 217, the lateral protection layer 217
Cover the outer wall surface corresponding with gate electrode 216a of floating gate electrode 216.
The PMOS transistor 210 of the not lightly doped region, PMOS selector transistor 230 and control capacitor 220 are logical
Cross the third n-type region 204 in outside and the second n-type region 203 of lower section and the conductivity regions P in P conduction type substrate 201
Domain separation, the P conductive region in P conduction type substrate 201 form the first p type island region domain.Floating gate electrode 216 and gate electrode 216a's
Material includes conductive polycrystalline silicon, and gate dielectric layer 215 is silica, and lateral protection layer 217 is silica or silicon nitride；Field
Areas of dielectric 214 is silica.
The PMOS transistor 210 of the not lightly doped region includes the first n-type region 202, first n-type region
Top in 202 is equipped with symmetrical p-type source area 213 and p-type drain region 221, the p-type source area 213, p-type drain electrode
Area 221 is in contact with the gate dielectric layer 215 of corresponding field areas of dielectric 214 and top.P-type source area 213 includes third p-type
Heavily doped region 219.Wrap the 4th p-type heavily doped region 223 in p-type drain region 221.Third p-type heavily doped region 219 and the 4th P
Type heavily doped region 223 is same manufacture layer.
Controlling capacitor 220 includes the second p type island region domain 205, and the top in second p type island region domain 205 is equipped with the first p-type and mixes
Miscellaneous area 206 and the second P-doped zone 209；First P-doped zone 206 and the second P-doped zone 209 are symmetrically distributed in
In two p type island regions domain 205.First P-doped zone 206, the second P-doped zone 209 and corresponding field areas of dielectric 214 and gate medium
Layer 215 is in contact.First P-doped zone 206 includes the first p-type lightly doped region 208 and the first p-type heavily doped region 207, the
One p-type lightly doped region 208 is in contact by the first p-type heavily doped region 207 with field areas of dielectric 214, and the first p-type is gently mixed
Extended distance of the miscellaneous region 208 in the second p type island region domain 205 is consistent with the thickness of lateral protection layer 217.The doping of second p-type
Area 209 includes the second p-type lightly doped region 211 and the second p-type heavily doped region 212, the second p-type lightly doped region 211
It is in contact by the second p-type heavily doped region 212 with field areas of dielectric 214, the second p-type lightly doped region 211 and the first p-type
The distribution setting of lightly doped region 208 is consistent.The second of 215 lower section of floating gate electrode 216 and gate dielectric layer 215 and gate dielectric layer
Capacitance structure is formed between p type island region domain 205, i.e. control capacitor 220.
The PMOS selector transistor 230 includes the first n-type region 202, the top in first n-type region 202
Equipped with symmetrical p-type source area 243 and p-type drain region 241, the p-type source area 243, p-type drain region 241 with it is corresponding
Field areas of dielectric 214 and the gate dielectric layer 215 of top be in contact.P-type source area 243 includes the 5th p-type lightly doped region
248 and third p-type heavily doped region 249, the doping concentration of the 5th p-type heavily doped region 249 is greater than the 5th p-type and is lightly doped
The doping concentration in region 248.P-type drain region 241 includes the 6th p-type lightly doped region 242 and the 6th p-type heavily doped region 243,
The doping concentration of the 6th p-type heavily doped region 243 is greater than the doping concentration of the 6th p-type lightly doped region 242.5th p-type
Lightly doped region 248 and the 6th p-type lightly doped region 242 are same manufacture layer, the 5th p-type heavily doped region 249 and the 6th p-type
Heavily doped region 243 is same manufacture layer.5th p-type lightly doped region 248 is in contact with the 5th p-type heavily doped region 249, and
It is in contact by the 5th p-type heavily doped region 249 with field areas of dielectric 214；Meanwhile the 6th p-type lightly doped region 242 set
It sets identical as the distribution setting of the 5th p-type lightly doped region 248.The PMOS selector transistor 230 with there is no lightly doped district
It is to be connected in series that the PMOS transistor 210 in domain, which is all located in the first n-type region 202, the p-type source of PMOS selector transistor 230
Polar region 243 and the p-type drain region 221 of the PMOS transistor 210 of not lightly doped region are connected.
By the PMOS transistor 210 of not lightly doped region write-in data can be carried out to memory body cell 200, or
The erasing of the data in body cell 200 will be remembered；It is thin that memory body can be read by the PMOS transistor 210 of not lightly doped region
Storing data state in born of the same parents 200 can be passed to voltage value on floating gate electrode 216 by controlling capacitor 220, realize floating gate electricity
The of the PMOS transistor 210 of lightly doped region with the not no channel of the PMOS transistor 210 of lightly doped region or not of pole 216
One voltage value of n-type region 202 can be realized data write-in, erasing and read operation according to corresponding voltage value.
As shown in Fig. 3~Figure 13: the non-volatility memory of above structure can realize by following processing steps, specifically
Ground:
A, P conduction type substrate 201 is provided, the P conduction type substrate 201 includes the first interarea 232 and the second interarea
233；As shown in Figure 3: the P conduction type substrate 201 requires mutually compatible consistent, P conduction type with stand CMOS preparation
The material of substrate 201 can select common silicon, and the first interarea 232 is corresponding with the second interarea 233；
B, carried out on the first interarea 232 of P conduction type substrate 201 required barrier layer deposition, barrier etch and
Autoregistration ion implanting, with formed in P conduction type substrate 201 the first required n-type region 202, third n-type region 204,
Second p type island region domain 205, third n-type region 204 are located at the outside in the second p type island region domain 205；
As shown in Figure 4 to 7, it is specifically form process are as follows:
B1, the first barrier layer 234 is deposited on the first interarea 232 of P conduction type substrate 201, and selectively sheltered
With etching first barrier layer 234, N-type impurity ion is injected in autoregistration above the first barrier layer 234, in P conductive-type
The second n-type region 203 is obtained in type substrate 201；As shown in figure 4, first barrier layer 234 is silica or silicon nitride；
After depositing the first barrier layer 234 on the first interarea 232, by etching the first barrier layer 234 of central area, when autoregistration is infused
After entering N-type impurity ion, the second n-type region 203 can be obtained in P conduction type substrate 201；The N-type impurity ion is half
Common foreign ion in semiconductor process is capable of forming required the by controlling the dosage and energy of N-type impurity ion implanting
Two n-type regions 203；
B2, growth obtains field areas of dielectric 214 in above-mentioned P conduction type substrate 201, as shown in Figure 5: field medium
Region 214 is silica, can be obtained by conventional thermal oxide growth；
The first barrier layer 234 on b3, corresponding first interarea 232 of the above-mentioned P conduction type substrate 201 of removal, and first
The second barrier layer 235 is deposited on interarea 232；
B4, it selectively shelters and etches the second barrier layer 235, and N-type is injected in autoregistration above the second barrier layer 235
Foreign ion, to form the first n-type region 202 and third n-type region 204, the first n-type region 202 in semiconductor substrate 201
And third n-type region 204 is respectively positioned on the top of the second n-type region 203；It is as shown in Figure 5: selectively to shelter and etch the second resistance
After barrier 235, corresponding second barrier layer 235 of the first n-type region 202 and 204 top of third n-type region will be needed to form and etched
Fall, after injecting N-type impurity ion, the first n-type region 202 and third n-type region 204 can be formed, third n-type region 204 with
The outside of first n-type region 202；
The second barrier layer 235 on b5, corresponding first interarea 232 of the above-mentioned P conduction type substrate 201 of removal, and first
Third barrier layer 236 is deposited on interarea 232；
B6, selectively shelter and etch third barrier layer 236, and the autoregistration injecting p-type above third barrier layer 236
Foreign ion, to form the second p type island region domain 205 above the second n-type region 203；
It is as shown in Figure 7: when etching third barrier layer 236, by the corresponding third barrier layer 236 in 205 top of the second p type island region domain
Removal, after autoregistration injecting p-type foreign ion, can form the second p type island region domain 205；
C, gate dielectric layer 215, the gate medium are deposited on corresponding first interarea 232 of above-mentioned P conduction type substrate 201
Layer 215 covers the first interarea 232 of semiconductor substrate 201；As shown in Figure 8: the gate dielectric layer 215 is silica, and grid are situated between
Matter layer 215 is covered in field areas of dielectric 214 and the corresponding surface of semiconductor substrate 201；
D, floating gate electrode 216 and gate electrode 216a, institute are deposited on the first interarea 232 of above-mentioned P conduction type substrate 201
Floating gate electrode 216 is stated to be covered on gate dielectric layer 215 and correspond to above the second p type island region domain 205 and the first n-type region 202
Gate dielectric layer 215 on, the gate electrode 216a is covered in the corresponding floating gate electrode gate dielectric layer in the top of the first n-type region 202
215；
It is as shown in Figure 9: the corresponding floating gate electrode 216 in the second p type island region domain 205 and 202 top of the first n-type region and grid in figure
Electrode 216a is same manufacture layer, and the corresponding floating gate electrode in the second p type island region domain 205 and 202 top of the first n-type region in figure
216 are connected with each other integrally；Here for that can show structure of the invention, of the invention cut open is obtained using interval section view method
View；Floating gate electrode 216 is in T shape on gate dielectric layer 215；
E, the 4th barrier layer 237 is deposited on above-mentioned gate dielectric layer 215, and selectively shelters and etch the 4th barrier layer
237, it is floating to remove the corresponding covering of corresponding covering floating gate electrode 216 and top above the first n-type region 202 and the second p type island region domain 205
The 4th barrier layer 237 of gate electrode 216a；
F, the autoregistration injecting p-type foreign ion above above-mentioned 4th barrier layer 237, it is upper in the second p type island region domain 205
Portion obtains the first p-type lightly doped region 208 and the second p-type lightly doped region 211, and the top in the first n-type region 202 obtains
5th p-type lightly doped region 248 and the 6th p-type lightly doped region 242；As shown in Figure 10: the 4th barrier layer 237 is silica
Or silicon nitride；After selectively sheltering and etching the 4th barrier layer 237, so that removing the second p type island region domain 205 and the first N-type region
Corresponding region can stop in p type impurity ion implanting P-type conduction type of substrate 201 outside domain 202；Using conventional autoregistration
Injecting p-type foreign ion can obtain required p-type lightly doped region simultaneously；
G, above-mentioned 4th barrier layer 237 is removed, and deposits lateral protection material on the first interarea 232, in floating gate electricity
The two sides of pole 216 form lateral protection layer 217；As shown in figure 11: the material of the lateral protection layer 217 is silica or dioxy
SiClx, by lateral protection layer 217 can formed needed for heavily doped region, while can make corresponding lightly doped region with
Lateral protection layer 217 is corresponding to the same；
H, the 5th barrier layer 238 is deposited on above-mentioned first interarea 232, and selectively shelters and etch the 5th barrier layer
238, to remove the 5th barrier layer 238 of corresponding deposit covering above the second p type island region domain 205 and the first n-type region 202；Deposit
And the 5th barrier layer 238 is selectively sheltered and etches, it mainly avoids avoiding ion implanting P when forming heavily doped region
In type conduction type substrate 201 in other regions；5th barrier layer 238 is silica or silicon nitride；
I, the autoregistration injecting p-type foreign ion again above above-mentioned 5th barrier layer 238, in the second p type island region domain 205
Top obtain the first p-type heavily doped region 207 and the second p-type heavily doped region 212, the top in the first n-type region 202
Obtain third p-type heavily doped region 219, the 4th p-type heavily doped region 223, the 5th p-type heavily doped region 249 and the 6th p-type weight
Doped region 243；As shown in figure 12: the concentration of the autoregistration injecting p-type foreign ion is greater than the ion concentration of step h, by
The blocking of five barrier layer 238 Yu You and lateral protection layer 217 enables to be formed in the position for being correspondingly formed lightly doped region
Heavily doped region, and the lightly doped region retained can be consistent with lateral protection layer 217, to obtain required single polycrystalline frame
Structure；
J, the 5th barrier layer 238 on the first interarea 232 is removed.As shown in figure 13: the 5th barrier layer 238 of removal obtains
Required non-volatility memory.
Embodiment 2
As shown in Fig. 2 and Figure 23: semiconductor substrate is N conduction type substrate 239 in the present embodiment, when using N conductive-type
After type substrate 239, do not have to form the second n-type region 203 and i.e. the second p type island region domain 205 directly in N conduction type substrate 239
Be in contact with N-type conduction type substrate 239, meanwhile, the first n-type region 202 and third n-type region 204 also directly with N conductive-type
Type substrate 239 is in contact.Setting using remaining structure and embodiment 1 after N conduction type substrate 239 is all the same.
As shown in Figure 14~Figure 23: the non-volatility memory of above structure can realize have by following processing steps
Body:
A, N conduction type substrate 239 is provided, the N conduction type substrate 239 includes the first interarea 232 and the second interarea
233；As shown in figure 14, the material of N conduction type substrate 239 can be silicon；
B, required barrier layer deposition, barrier etch and autoregistration are carried out on the first interarea 232 of semiconductor substrate
Ion implanting, to form the first required n-type region 202, third n-type region 204, the second p type island region domain in semiconductor substrate
205, third n-type region 204 is located at the outside in the second p type island region domain 205；
The forming process of step b can be divided into:
S1, growth obtains field areas of dielectric 214 in above-mentioned semiconductor substrate, as shown in figure 15；
S2, the second barrier layer 235 is deposited on the first interarea 232, and selectively shelter and etch the second barrier layer
235；
N-type impurity ion is injected in s3, the top autoregistration on above-mentioned second barrier layer 235, in N conduction type substrate
Top in 239 obtains required the first n-type region 202 and the second n-type region 204, as shown in figure 16；
The second barrier layer 235 on s4, the first interarea 232 of removal, and third barrier layer is deposited on the first interarea 232
236；
S5, selectively shelter and etch third barrier layer 236, and the autoregistration injecting p-type above third barrier layer 236
Foreign ion, to obtain the second p type island region domain 205 in N conduction type substrate 239, as shown in figure 17；
C, gate dielectric layer 215, the gate dielectric layer 215 are deposited on corresponding first interarea 232 of above-mentioned semiconductor substrate
The first interarea 232 of semiconductor substrate 201 is covered, as shown in figure 18；
D, floating gate electrode 216 and gate electrode 216a, the floating gate are deposited on the first interarea 232 of above-mentioned semiconductor substrate
Electrode 216 is covered on gate dielectric layer 215 and through the second p type island region domain 205, the corresponding gate medium in 202 top of the first n-type region
On layer 215, the gate electrode 216a is covered on the corresponding gate dielectric layer 215 in 202 top of the first n-type region as shown in figure 19；
E, the 4th barrier layer 237 is deposited on above-mentioned gate dielectric layer 215, and selectively shelters and etch the 4th barrier layer
237, the first n-type region 202 is removed, the of corresponding covering floating gate electrode 216 and gate electrode 216a above the second p type island region domain 205
Four barrier layers 237；
F, the autoregistration injecting p-type foreign ion above above-mentioned 4th barrier layer 237, it is upper in the second p type island region domain 205
Portion obtains the first p-type lightly doped region 208 and the second p-type lightly doped region 211, and the top in the first n-type region 202 obtains
5th p-type lightly doped region 248 and the 6th p-type lightly doped region 242, as shown in figure 20；
G, above-mentioned 4th barrier layer 237 is removed, and deposits lateral protection material on the first interarea 232, in floating gate electricity
Pole 216 and the two sides of gate electrode 216a form lateral protection layer 217, as shown in figure 21；
H, the 5th barrier layer 238 is deposited on above-mentioned first interarea 232, and selectively shelters and etch the 5th barrier layer
238, to remove the 5th barrier layer 238 of corresponding deposit covering above the second p type island region domain 205 and the first n-type region 202；
I, the autoregistration injecting p-type foreign ion again above above-mentioned 5th barrier layer 238, in the second p type island region domain 205
Top obtain the first p-type heavily doped region 207 and the second p-type heavily doped region 212, the top in the first n-type region 202
Obtain third p-type heavily doped region 219, the 4th p-type heavily doped region 223, the 5th p-type heavily doped region 249 and the 6th p-type weight
Doped region 243, as shown in figure 22；
J, the 5th barrier layer 238 on the first interarea 232 is removed, as shown in figure 23.
As shown in Fig. 1 and Figure 13: for individually remembering for body cell 200, single binary number evidence may be implemented
Write-in is read and is wiped.Below by of the invention non-to illustrate to single memory body cell 200 write-in, reading and erase process
The working mechanism of volatilization memory body.When need be written input according to when, by P conduction type substrate 201 p type island region domain and PMOS select
The gate electrode 216a voltage for selecting device transistor 230 sets 0 current potential, the first n-type region 202, the second n-type region 203 and the 3rd N always
The equal set 5v current potential in type region 204, the second p type island region domain 205 also set 0v current potential control the first P-doped zone of capacitor 220
The 206 and equal set 0V of the second P-doped zone 209；Due to the transmitting effect of control capacitor 220, the voltage value of 0V can be transmitted
Onto floating gate electrode 216, the voltage value for generating 1~2V on floating gate electrode 216 does not have the PMOS transistor 210 of lightly doped region
P-type drain region 241 the set 5v, 5v of the transistor 230 of 213 set 0v, PMOS selector of p-type source area can pass to PMOS selection
The p-type drain region 221 of the PMOS transistor 210 of the p-type source area 243 of the transistor 230 of device or not lightly doped region.This
Sample, not the p-type source area of the PMOS transistor 210 of lightly doped region and the not PMOS transistor 210 of lightly doped region
First n-type region 202 has the reverse bias voltage difference of 5v.By sufficiently high reverse bias voltage difference generate electric field into
The collision of row electron ion is to generate free electronics.Not having the two sides of the channel of the PMOS transistor 210 of lightly doped region does not have
The p-type source of the PMOS transistor 210 of the p-type drain region 221 of the PMOS transistor 210 of lightly doped region and not lightly doped region
The voltage difference of polar region 213 is that the collision of 5v. electron ion collides and generates free electronics in the PMOS crystal of not lightly doped region
The electric field acceleration of the channel of pipe 210 and form thermoelectron.The phenomenon of the thermoelectron injection of PMOS here it is carried out by, thermoelectron is just
It can be reached in floating gate electrode 216 by gate dielectric layer 215, realize the write-in of data.Due to being situated between below floating gate electrode 216 by grid
Matter layer 215 completely cuts off, and side is completely cut off by lateral protection layer 217, therefore electronics can be protected for a long time in floating gate electrode 216
It stays.
When need wipe memory body cell 200 in data when, by P conduction type substrate 201 p type island region domain and PMOS
The gate electrode 216a voltage of selector transistor 230 sets 0 current potential always, not the p-type of the PMOS transistor 210 of lightly doped region
The 241 set 5v of p-type drain region of the transistor 230 of 213 set 5v, PMOS selector of source area, the first n-type region 202, second
The equal set 5V voltage of the voltage of n-type region 203 and third n-type region 204, the voltage set -5V in the second p type island region domain 205, first
Equal set-the 5V of voltage of P-doped zone 206, the second P-doped zone 209 can make floating gate electric in the case where control capacitor 220 acts on
216 generation -4V of pole~-5V voltage, at this time about 215 voltage of gate dielectric layer between floating gate electrode 216 and the first n-quadrant 202
Value is -9~-10V, will reach electric field needed for field emission characteristic is also referred to as FN (Fowler-Nordheim) tunnel-effect, electricity
Son can be entered by gate dielectric layer 215 in the channel of the PMOS transistor 210 of the not lightly doped region of first n-type region 202,
Data in floating gate electrode 216 are wiped to realize.
When need read memory body cell 200 in data when, by P conduction type substrate 201 p type island region domain and PMOS
The gate electrode 216a voltage of selector transistor 230 sets 0 current potential, the first n-type region 202, the second n-type region 203 and always
The equal set 0.5V voltage of the voltage of three n-type regions 204,205 set -1V of the second p type island region domain, the first P-doped zone 206 and second
Equal set-the 1V of P-doped zone 209, not 213 set 0.5V and the PMOS selector of PMOS transistor source area of lightly doped region
241 set 0V of transistor drain area after loading above-mentioned voltage value, when remembering in body cell 200 in the state that data are written, is floated
There are a large amount of electronics in gate electrode 216, under data erased state in memory body cell 200, electronics is out of floating gate electrode 216
Outflow, floating gate electrode 216 is the state of cation；When having electronics in floating gate electrode 216, pass through not lightly doped region
The electric current of PMOS transistor source area 213 is larger, when floating gate electrode 216 is the state of cation, passes through no lightly doped region
PMOS transistor source area 213 electric current it is smaller, thus according to the size of corresponding electric current, be able to know that memory body cell 200
It is that write-in data mode is in data erase status.
Due to the first P-doped zone 206, the second P-doped zone 209, p-type source area 213, p-type drain region 221, in it is right
Answering transportable anion (electronics) in the region P+ is minority, is just not easy volatilization and is lost.It is grasped in this way when the data of sucking
That holds is more long, and storage is more safe and reliable when using.
As shown in Fig. 2 and Figure 23: the single polycrystalline architecture being correspondingly formed using N conduction type substrate 239 it is non-volatile
Memory body, the write-in for needing to carry out, erasing and when reading need corresponding on-load voltage, with realize corresponding write-in, erasing and
Read operation.Specifically, corresponding write-in, erasing and the voltage-drop loading read are correspondingly formed with using P conduction type substrate 201
Single polycrystalline architecture non-volatility memory operation when voltage it is consistent, herein no longer in detail narration.
At least one memory body cell 200 of setting, memory body cell 200 include not mixing gently in semiconductor substrate of the present invention
PMOS transistor 210, control capacitor 220 and the PMOS selector transistor 230 in miscellaneous region；There is no the PMOS of lightly doped region brilliant
Body pipe 210 and control capacitor 220 are mutually isolated by field areas of dielectric 214；On the gate dielectric layer 215 of semiconductor substrate 201
Floating gate electrode 216 is set, and the connection of floating gate electrode 216 is through the not PMOS transistor 210 of lightly doped region and control electricity
Hold 220；The PMOS transistor 210 of the PMOS selector transistor 230 and not lightly doped region is concatenated connection；It is described
P-type drain region of the p-type source area 243 of PMOS selector transistor 230 with the PMOS transistor 210 of not lightly doped region
221 are connected；The gate electrode of the PMOS selector transistor is with the floating gate electricity in the PMOS transistor of not lightly doped region
Pole is independent of each other；When floating gate electrode 216 and voltage difference in the not PMOS transistor 210 of lightly doped region are analog value
When, data can be written into floating gate electrode 216 or wipe the data in floating gate electrode 216, flowed through by detection without light
The electric current of the PMOS transistor 210 of doped region, which can know that, is programmed into state or erase status locating for floating gate electrode 216, whole
The preparation flow of a memory body cell 200 can be mutually compatible with existing CMOS logic technique, compact-sized, can reduce and is processed into
This, improves the adaptability of nonvolatile memory and CMOS logic circuit；By in the PMOS transistor 210 of not lightly doped region
The p-type source area 213 on top and p-type drain region 221, the first P-doped zone 206 and the second p-type that control 220 internal upper part of capacitor
Doped region 209 enables to write-in data to keep more long, improves the safety and reliability of non-volatility memory.
Claims (5)
1.P+ single polycrystalline and the non-volatility memory not being lightly doped, including semiconductor substrate；It is characterized in that: described partly lead
Top in structure base board is equipped with several memory body cells (200) for storage, and the memory body cell (200) includes without light
The PMOS transistor (210) of doped region controls capacitor (220) and PMOS selector transistor (230)；It is described not mix gently
Pass through field areas of dielectric (214) phase in semiconductor substrate between the PMOS transistor (210) in miscellaneous region, control capacitor (220)
Mutually isolation；The PMOS transistor (210) without light doped region, PMOS selector transistor (230) are all to be located at the
One N type region (202), and be to be connected in series between each other；Gate dielectric layer (215), institute are deposited on the surface of semiconductor substrate
Gate dielectric layer (215) are stated equipped with floating gate electrode (216) and gate electrode (216a), the floating gate electrode (216) covers and runs through
There is no corresponding gate dielectric layer (215) above the PMOS transistor (210) of lightly doped region and control capacitor (220), floating gate electricity
The two sides of pole (216) are deposited with lateral protection layer (217), and lateral protection layer (217) covers the side wall of floating gate electrode (216)；Institute
State corresponding gate dielectric layer (215), floating gate electrode above gate electrode (216a) covering PMOS selector transistor (230)
The two sides of (216a) are deposited with lateral protection layer (217), and the side wall of lateral protection layer (217) covering grid electrode (216a) does not have
The PMOS transistor (210) of lightly doped region includes the first N type region (202) and is located in the first N type region (202)
The P type source area (213) on top and P type drain region (221), control capacitor (220) include the 2nd P type region (205) and position
In second p type island region domain (205) internal upper part the first P type doped region (206) and the 2nd P type doped region (209) with
The floating gate electrode (216) of top is corresponding, and connects respectively with corresponding gate dielectric layer (215) and field areas of dielectric (214)
Touching, PMOS selector transistor (230) is including the first N type region (202) and is located in the first N type region (202)
The P type source area (242) in portion and P type drain region (247)；PMOS transistor (210) is no lightly doped region.
2. the P+ single polycrystalline and the non-volatility memory not being lightly doped according to claim 1, it is characterized in that: including
The deep-well structure in the 2nd N type region (203), the PMOS transistor (210) without light doped region, PMOS selector
Transistor (230) and control capacitor (220) pass through the 3rd N type region (204) in outside and the 2nd N type region of lower section
(203) with P conduction type substrate (201) in the conductivity regions P domain separation.
3. the preparation method of P+ single polycrystalline and the non-volatility memory not being lightly doped, it is characterized in that: the preparation method
Include the following steps:
(a), semiconductor substrate is provided, the semiconductor substrate includes the first interarea (232) and the second interarea (233)；
(b), it grows and obtains field areas of dielectric (214) in above-mentioned semiconductor substrate, and in the first interarea of semiconductor substrate
(232) required barrier layer deposition, barrier etch and autoregistration ion implanting are carried out on, to form institute in semiconductor substrate
The first N type region (202), the 3rd N type region (204), the 2nd P type region (205) needed；
(c), gate dielectric layer (215) are deposited on corresponding first interarea (232) of above-mentioned semiconductor substrate, the gate dielectric layer
(215) first interarea (232) of semiconductor substrate (201) is covered；
(d), floating gate electrode (216) and gate electrode (216a) are deposited on the first interarea (232) of above-mentioned semiconductor substrate, it is described
Floating gate electrode (216) is covered on gate dielectric layer (215) and through the 2nd P type region (205) and the first N type region (202)
On the corresponding gate dielectric layer in top (215), the gate electrode (216a) is covered in the gate dielectric layer of PMOS selector (230)
(215) on；
(e), the 4th barrier layer (237) is deposited on above-mentioned gate dielectric layer (215), and selectively shelters and etch the 4th resistance
Barrier (237), the first N type region (202) of removal, the 2nd P type region (205) top correspond to covering floating gate electrode (216)
4th barrier layer (237)；
(f), P type foreign ion is injected in autoregistration above above-mentioned 4th barrier layer (237), in the 2nd P type region (205)
Top obtain the first P type lightly doped region (208) and the 2nd P type lightly doped region (211), in the first N type region
(202) top in obtains the 5th P type lightly doped region (248) and the 6th P type lightly doped region (242)；
(g), above-mentioned 4th barrier layer (237) is removed, and deposits lateral protection material on the first interarea (232), in floating gate
The two sides of electrode (216) form lateral protection layer (217)；
(h), the 5th barrier layer (238) is deposited on above-mentioned first interarea (232), and is selectively sheltered and etched the 5th and stop
Layer (238), to remove the 5th barrier layer in the 2nd P type region (205), the corresponding deposit covering in the first N type region (202) top
(238)；
(i), P type foreign ion is injected in autoregistration again above above-mentioned 5th barrier layer (238), in the 2nd P type region
(205) top in obtains the first P type heavily doped region (207) and the 2nd P type heavily doped region (212), in the first N type
Top in region (202) obtains the 3rd P type heavily doped region (219), the 4th P type heavily doped region (223), the 5th P type
Heavily doped region (249) and the 6th P type heavily doped region (243)；
(j), the 5th barrier layer (238) on the first interarea (232) is removed.
4. the preparation method of P+ single polycrystalline and the non-volatility memory not being lightly doped according to claim 3,
Be characterized in: in the step (a), when semiconductor substrate is P conduction type substrate (201), the step (b) includes
(b1), the first barrier layer (234) are deposited on the first interarea (232) of P conduction type substrate (201), and selectively
First barrier layer (234) is sheltered and etches, N type foreign ion is injected in autoregistration above the first barrier layer (234), with
The 2nd N type region (203) is obtained in semiconductor substrate (201)；
(b2), growth obtains field areas of dielectric (214) in above-mentioned P conduction type substrate (201)；
(b3), the first barrier layer (234) on the above-mentioned P conduction type substrate (201) of removal corresponding first interarea (232), and
The second barrier layer (235) are deposited on first interarea (232)；
(b4), it selectively shelters and etches the second barrier layer (235), and N is injected in autoregistration above the second barrier layer (235)
Type foreign ion, to form the first N type region (202) and the 3rd N type region (204) in the semiconductor substrate (201), first
N type region (202) and the 3rd N type region (204) are respectively positioned on the top in the 2nd N type region (203)；
(b5), the second barrier layer (235) on the above-mentioned P conduction type substrate (201) of removal corresponding first interarea (232), and
Third barrier layer (236) are deposited on first interarea (232)；
(b6), it selectively shelters and etches third barrier layer (236), and P is injected in autoregistration above third barrier layer (236)
Type foreign ion, to form the 2nd P type region (205) above the 2nd N type region (203).
5. the preparation method of P+ single polycrystalline and the non-volatility memory not being lightly doped according to claim 3,
Be characterized in: in the step (a), when semiconductor substrate is N conduction type substrate (239), the step (b) includes
(s1), growth obtains field areas of dielectric (214) in above-mentioned P conduction type substrate (201)；
(s2), it is deposited on the first interarea (232) the second barrier layer (235), and selectively shelters and etch the second barrier layer
(235)；
(s3), N type foreign ion is injected in the top autoregistration of above-mentioned second barrier layer (235), in N conduction type substrate
(239) top in obtains required the first N type region (202) and the 2nd N type region (204)；
(s4), the second barrier layer (235) on the first interarea (232) is removed, and deposits third on the first interarea (232) and stops
Layer (236)；
(s5), it selectively shelters and etches third barrier layer (236), and P is injected in autoregistration above third barrier layer (236)
Type foreign ion, to obtain the 2nd P type region (205) in N conduction type substrate (239).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210579974.0A CN103022043B (en) | 2012-12-28 | 2012-12-28 | P+ single polycrystalline and the non-volatility memory and preparation method thereof not being lightly doped |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210579974.0A CN103022043B (en) | 2012-12-28 | 2012-12-28 | P+ single polycrystalline and the non-volatility memory and preparation method thereof not being lightly doped |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103022043A CN103022043A (en) | 2013-04-03 |
| CN103022043B true CN103022043B (en) | 2019-04-02 |
Family
ID=47970451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210579974.0A Active CN103022043B (en) | 2012-12-28 | 2012-12-28 | P+ single polycrystalline and the non-volatility memory and preparation method thereof not being lightly doped |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103022043B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807393B (en) * | 2017-05-05 | 2020-12-22 | 中芯国际集成电路制造(上海)有限公司 | Memory and forming method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102544122A (en) * | 2012-02-21 | 2012-07-04 | 无锡来燕微电子有限公司 | Non-volatile memory with P+ single polycrystalline architecture and preparation method for non-volatile memory |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7046549B2 (en) * | 2003-12-31 | 2006-05-16 | Solid State System Co., Ltd. | Nonvolatile memory structure |
| US7078761B2 (en) * | 2004-03-05 | 2006-07-18 | Chingis Technology Corporation | Nonvolatile memory solution using single-poly pFlash technology |
| US7903465B2 (en) * | 2007-04-24 | 2011-03-08 | Intersil Americas Inc. | Memory array of floating gate-based non-volatile memory cells |
| US8344440B2 (en) * | 2008-02-25 | 2013-01-01 | Tower Semiconductor Ltd. | Three-terminal single poly NMOS non-volatile memory cell with shorter program/erase times |
-
2012
- 2012-12-28 CN CN201210579974.0A patent/CN103022043B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102544122A (en) * | 2012-02-21 | 2012-07-04 | 无锡来燕微电子有限公司 | Non-volatile memory with P+ single polycrystalline architecture and preparation method for non-volatile memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103022043A (en) | 2013-04-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| USRE49152E1 (en) | Nonvolatile semiconductor memory device and method for driving same | |
| CN100483743C (en) | Semiconductor storage device, its manufacturing method and operating method, and portable electronic apparatus | |
| CN104752435B (en) | Semiconductor device | |
| US10026742B2 (en) | Nonvolatile memory devices having single-layered gates | |
| TW201523838A (en) | Semiconductor device | |
| CN102315174B (en) | SONOS flash memories containing separate gate structures and preparation method thereof, operational approach | |
| CN102544122B (en) | Non-volatile memory with P+ single polycrystalline architecture and preparation method for non-volatile memory | |
| CN102959632A (en) | Memories and their formation | |
| WO2000077855A1 (en) | Ferroelectric field effect transistor, memory utilizing same, and method of operating same | |
| CN103022044B (en) | A kind of embedded non-volatile memory body of P+ single polycrystalline architecture and preparation method thereof with selector transistor | |
| CN1329998C (en) | Memory cell arrangement | |
| CN100530416C (en) | Dibit dielectric memory unit array and method for detecting charge stored in the array | |
| CN103022043B (en) | P+ single polycrystalline and the non-volatility memory and preparation method thereof not being lightly doped | |
| CN103022046B (en) | It is a kind of with P+ single polycrystalline architecture and the non-volatility memory and preparation method thereof mutually compatible with CMOS technology | |
| EP1280209A2 (en) | Semiconductor memory cell | |
| CN100423272C (en) | Semiconductor storage device, operating method thereof, semiconductor device, and portable electronic device | |
| US20030081452A1 (en) | Isolation of memory cells in cross point arrays | |
| CN203118949U (en) | Non-volatile memory with P+ single polycrystalline architecture | |
| CN202434528U (en) | Non-volatile memory with P+ single polycrystalline structure | |
| CN102544074A (en) | Non-volatile memory compatible with complementary metal oxide semiconductor (CMOS) logical process and preparation method for non-volatile memory | |
| TWI400791B (en) | Electrically isolated gate diode non-volatile memory | |
| CN102709295B (en) | Non-volatile memory compatible with CMOS (complementary metal oxide semiconductor) logic process and preparation method of non-volatile memory | |
| CN203260581U (en) | Low-cost non-volatile memory with single polycrystalline architecture | |
| CN202736919U (en) | Non-volatile memory | |
| CN102709294B (en) | Non-volatile memory for improving data storage time and method for producing non-volatile memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230322 Address after: No. 281, Bailian Avenue, Xianhua Street, Pujiang County, Jinhua City, Zhejiang Province, 322299 Patentee after: Zhejiang Feng Hua Chuang Xin Microelectronics Co.,Ltd. Address before: Room 208-3, 208-4, Wuxi National Integrated Circuit Design Institute (Chuangyuan Building), 21-1 Changjiang Road, Wuxi New District, Wuxi City, Jiangsu Province Patentee before: WUXI ADVANCE SUNRISE Co.,Ltd. |
|
| TR01 | Transfer of patent right |