CN103000669A - Source-drain buried graphene transistor device on diamond-like carbon substrate and manufacturing method - Google Patents
Source-drain buried graphene transistor device on diamond-like carbon substrate and manufacturing method Download PDFInfo
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Abstract
A source-drain buried graphene transistor device on a diamond-like carbon substrate suitable for radio frequency communication and a manufacturing method thereof are provided. Firstly, depositing diamond-like carbon with a smooth surface and stable chemical property on a substrate through a magnetic filtering cathode vacuum arc system, etching a source drain region groove on a diamond-like carbon insulating layer and filling electrode metal, after planarization treatment and cleaning the surface of the substrate, transferring graphene grown by a chemical vapor deposition method to a clean substrate, growing a gate insulating medium by an atomic layer deposition method and sputtering gate electrode metal. Reactive ion etching is carried out to form a metal gate, and then a low-K insulating medium is deposited to protect the device. The graphene transistor is high in carrier mobility; the source-drain buried structure can reduce the length of graphene in an area which is not covered by a grid electrode, reduce grid-source grid-drain capacitance and channel resistance, and improve the high-frequency performance and efficiency of the graphene transistor. The invention can be widely applied to small-size high-frequency graphene integrated circuits.
Description
Technical field
The present invention relates to technical field of semiconductors, the source is leaked and is buried type Graphene transistor device and manufacture method on especially a kind of diamond like carbon substrate that is applicable to radio communication.
Background technology
Since the people such as Novoselov in 2004 report about after successfully preparing the one way Graphene and finding field effect in the Graphene, Graphene just paid close attention to widely always and studied (reference: Electric Field Effect in Atomically Thin Carbon Films K.S.Novoselov.et al.Science 22 October 2004:306 (5696), 666-669.).Graphene has obtained semiconductor device engineer's favor especially with its very high mobility and elementary layer thickness.Especially on frequency applications, Graphene has been showed huge potentiality, and each seminar of the world falls over each other to report the high frequency performance of Graphene, and the transistorized cut-off frequency of Graphene has reached 100G～300G.At document: Dual Gate Graphene FETs with fT of 50GHz.Y.-M.Lin.et al, IEEE Electron Device Letters 31, in 68 (2010), the author reduces channel resistance (Access resistance) by regulating back gate voltage, has improved the cut-off frequency of device in certain limit.At document: Boron nitride substrates for high-quality graphene electronics.C.R.Dean.et al.Nature Nanotechnology 5, among the 722-726 (2010), the author makes the Graphene transistor at monocrystalline boron nitride (h-BN) substrate first, descends because of the carrier mobility that the loose look of phonon of substrate silicon dioxide causes to overcome Graphene.Obtain the high almost carrier mobility of an order of magnitude than traditional silicon dioxide substrate.The monocrystalline boron nitride has the smooth surface of atom level, does not almost have dangling bonds and trapped charge, has simultaneously high optical phonon pattern and large energy gap; Therefore be considered to more satisfactory graphene substrate material.At document: High-frequency, scaled graphene transistors on diamond-like carbon.Y.Wu et al., Nature 472, in 74 (2011), the author provides at the diamond like carbon amorphous carbon and has made the transistorized method of Graphene, and studied first the transistorized performance of Graphene under the low temperature, and the Graphene transistor size potentiality of dwindling.
At present the technical difficult points that faces of Graphene transistor has: 1) Graphene is the material of zero band gap, how by mixing or applying outer bias voltage, perhaps introduces the technology such as stress and obtains certain band gap.2) there is more intense phon scattering at Graphene and traditional silicon dioxide insulator interface, serious reduction the carrier mobility of Graphene, the trapped charge of how growing is few, dangling bonds are few, and the weak premium insulation upper and lower interface of phon scattering is to improve the major issue that the Graphene transistor performance faces.3) the Graphene resistance that is not covered by gate electrode between the contact resistance between Graphene and the metal, and source-drain area and the grid, the high frequency performance and the size that are restricting device are dwindled.Shown in Figure 1A and Figure 1B, in the situation of long raceway groove, the electric capacity between gate electrode 0026 and source/drain electrode 0010/0012 is C
Gs, C
GdSmaller, in order to reach higher cut-off frequency
And when reducing gate electrode length Lg, if the distance between grid and the source-drain electrode is Lgd, Lgs is scaled down also, C
Gs, C
GdBut inverse proportion increases, like this can serious restriction cut-off frequency
Raising.If Lgd, Lgs remains unchanged, the series resistance R of Graphene between the grid source grid leak string that is not covered by gate electrode
Gs_s, R
Gd_sThe Graphene resistance R of meeting and grid-control can be compared, even the former is greater than the latter.Therefore the Graphene transistor of prior art can not accomplish that parasitic capacitance and channel resistance reduce simultaneously.
Summary of the invention
For several problems that need solution above-mentioned, the source that the invention discloses on a kind of diamond like carbon substrate is leaked and is buried type Graphene transistor device structures and manufacture method, by the transistorized source-drain electrode of Graphene is buried in the diamond like carbon amorphous carbon substrate, so that even the distance between grid and the source-drain electrode is 0, even less than 0, also can keep the parasitic capacitance between gate electrode and the source/drain electrode constant, thereby fully excavate out the potentiality that the Graphene transistor size dwindles.
The technical scheme that realizes the object of the invention is:
The source is leaked and is buried type Graphene transistor device on a kind of diamond like carbon substrate, comprises at least successively: substrate; Be positioned at the diamond like carbon amorphous carbon film on the substrate; Be buried in the source/drain electrode in the described diamond like carbon amorphous carbon film; At least cover individual layer or the minority layer graphene layer of described source electrode and drain electrode top; Be deposited on the insulating medium layer on the described graphene layer; Be positioned at the metal gate electrode on the described insulating medium layer.
Wherein said gate electrode and described source/drain electrode lay respectively at the up and down both sides of described graphene layer, the distance between described source/drain electrode and the described gate electrode or greater than zero or equal zero or less than zero.
The material of wherein said substrate is smooth, bending or strain is arranged; The material of described substrate is one of following semi-conducting material: silicon, polysilicon, sige alloy, germanium, III-V compounds of group or II-VI compounds of group; Perhaps the material of described substrate is one of following insulating material: plastic film, glass or silicon dioxide; Perhaps the material of described substrate is one of following metal material: iron, aluminium, gold, silver or copper; Also have the silicon dioxide layer as stress-buffer layer between described substrate and the described diamond like carbon amorphous carbon film, described is 5nm～50nm as the stress buffer layer thickness; Described diamond like carbon amorphous carbon film sp3C-C linkage content greater than 50%, sp2C=C linkage content greater than the content of 5%, H atom less than 25%, the content of other impurity elements is less than 20%; Thin film stress is less than 4GPa; Film thickness is 10nm～200nm; Surface roughness is less than 5nm; The metal of described source/drain electrode is selected from one of following material or wherein several combination: comprise palladium, and gold, Ti, Ta, Mo, Al, W, Cu, Ni, Pt, Co is at interior metal; Or comprise TaN, and TiN, TiSiN is at interior metal nitride; Or comprise WSi, and NiSi, CoSi, PtSi is at interior silicide; Or transparent metal oxide electrode IZO, ITO; Or polysilicon; Or multicrystalline silicon compounds; Metal electrode length 5nm～1um that bury in described source region and drain region, width 10nm～10um, thickness 1nm～100nm; The absolute figure of the distance between described source/drain electrode and the described gate electrode is not more than 40nm; The minority layer of described graphene layer is 2～10 layers of carbon atom thickness; Described insulating medium layer be selected from that following material one or a combination set of consists of compound one or more layers: Al2O3, HfO2, comprise HfSiOx, HfSiON, HfAlOx, HfTaOx, HfLaOx, HfAlSiOx, or HfLaSiOx one of at least at interior hafnium base high K dielectric material, comprise ZrO2, La2O3, LaAlO3, TiO2, or Y2O3 is one of at least at interior rare earth based high K dielectric material and comprise silicon dioxide, SiON, or Si3N4 is one of at least at interior dielectric material.
In addition, the present invention also provides a kind of source on the above-mentioned diamond like carbon substrate of making to leak the method for burying type Graphene transistor device, comprises the steps: at least deposit one deck diamond like carbon amorphous carbon film on Semiconductor substrate; Photoetching source region and drain region on described diamond like carbon amorphous carbon film; Then sputtering source drop ply material forms the plane that can expose described source region and drain region by CMP, formation source/drain electrode, and clean the surface on described plane; Individual layer or minority layer graphene are transferred on the described surface after the cleaning; Deposit insulating medium layer on described Graphene; The splash-proofing sputtering metal layer, chemical wet etching forms metal gate electrode.
Preferably, also be formed with layer of silicon dioxide as stress-buffer layer by deposit or thermal oxidation on the described Semiconductor substrate, described diamond like carbon amorphous carbon film is formed on the described stress-buffer layer.
Preferably, the method for deposit diamond like carbon amorphous carbon film is selected from one of following on described silicon dioxide layer: magnetic filters the deposit of (pulse) cathode vacuum arc, plasma enhanced chemical vapor deposition, sputter, pulsed laser deposition, ion beam depositing or quality and selects ion beam depositing; Described source region and drain region adopt the oxygen/argon method for etching plasma to be formed on the described diamond like carbon amorphous carbon film; Described source-drain layer material is to form with grapheme material that good ohmic contacts or the material of Schottky contacts; The step of described transfer Graphene comprises: first Graphene is grown at Copper Foil, PMMA in the spin coating on Graphene, then in FeCl3 solution, described Copper Foil is dissolved, be to be the double-layer structure of Graphene under the PMMA in the formation, then this double-layer structure is transferred on the surface on described plane, with acetone soln PMMA is dissolved, described individual layer or minority layer graphene are just transferred on the surface on described plane again; Described insulating medium layer is deposited on the described Graphene by the atomic layer deposition method.
Preferably, the step that described magnetic filters (pulse) cathode vacuum arc deposition process growth diamond like carbon amorphous carbon film comprises: use magnetic filtered pulse cathodic vacuum arc discharge deposition system, prepare the high purity graphite target as negative electrode, selectivity passes into impure element or contains the gas of H element, produces carbon plasma and electronics, neutral atom and particle by cathodic vacuum arc discharge; Under the guiding of the magnetic filter duct in described magnetic filtered pulse cathodic vacuum arc discharge deposition system, wherein neutral atom and particle are filtered, add back bias voltage by described conducting bracket simultaneously on described substrate/silicon dioxide carbon ion is accelerated, the carbon ion bombardment of ionization also forms the diamond like carbon amorphous carbon film thereon to described substrate/silicon dioxide.
Preferably, the purity of described graphite target is more than 99.9%, and the air pressure of the vacuum chamber of described magnetic filtered pulse cathodic vacuum arc discharge deposition system is controlled at 10-2～10-4Pa; Substrate DC bias 406 is in 20V～200V scope; Underlayer temperature is controlled at less than 150 ℃.
Preferably, form and also comprise 30 minutes behind the described diamond like carbon amorphous carbon film～300 minutes 400 ℃ process annealing.
Preferably, described gate electrode and described source/drain electrode lay respectively at the up and down both sides of described graphene layer, the distance between described source/drain electrode and the described gate electrode or greater than zero or equal zero or less than zero.
The material of wherein said substrate is smooth, bending or strain is arranged; The material of described substrate is one of following semi-conducting material: silicon, polysilicon, sige alloy, germanium, III-V compounds of group or II-VI compounds of group; Perhaps the material of described substrate is one of following insulating material: plastic film, glass or silicon dioxide; Perhaps the material of described substrate is one of following metal material: iron, aluminium, gold, silver or copper; Also have the silicon dioxide layer as stress-buffer layer between described substrate and the described diamond like carbon amorphous carbon film, described is 5nm～50nm as the stress buffer layer thickness; Described diamond like carbon amorphous carbon film sp3C-C linkage content greater than 50%, sp2C=C linkage content greater than the content of 5%, H atom less than 25%, the content of other impurity elements is less than 20%; Thin film stress is less than 4GPa; Film thickness is 10nm～200nm; Surface roughness is less than 5nm; The metal of described source/drain electrode is selected from one of following material or wherein several combination: comprise palladium, and gold, Ti, Ta, Mo, Al, W, Cu, Ni, Pt, Co is at interior metal; Or comprise TaN, and TiN, TiSiN is at interior metal nitride; Or comprise WSi, and NiSi, CoSi, PtSi is at interior silicide; Or transparent metal oxide electrode IZO, ITO; Or polysilicon; Or multicrystalline silicon compounds; Metal electrode length 5nm～1um that bury in described source region and drain region, width 10nm～10um, thickness 1nm～100nm; The absolute figure of the distance between described source/drain electrode and the described gate electrode is not more than 40nm; The minority layer of described graphene layer is 2～10 layers of carbon atom thickness; Described insulating medium layer be selected from that following material one or a combination set of consists of compound one or more layers: Al2O3, HfO2, comprise HfSiOx, HfSiON, HfAlOx, HfTaOx, HfLaOx, HfAlSiOx, or HfLaSiOx one of at least at interior hafnium base high K dielectric material, comprise ZrO2, La2O3, LaAlO3, TiO2, or Y2O3 is one of at least at interior rare earth based high K dielectric material and comprise silicon dioxide, SiON, or Si3N4 is one of at least at interior dielectric material.
Source on the diamond like carbon amorphous carbon substrate of the present invention is leaked and is buried type Graphene transistor, the main advantage of comparing with traditional device architecture: 1) replace traditional SiO with diamond like carbon
2As dielectric substrate, higher as the mobility in the Graphene of conducting channel material on the substrate; 2) gate electrode and source-drain electrode are placed respectively the up and down both sides of graphene conductive raceway groove, can make the level interval between grid and the source-drain electrode little, and then make the parasitic capacitance between gate electrode and the source-drain electrode little, the channel resistance of device is little.
To sum up can significantly improve Graphene transistor high frequency performance and operating efficiency, especially improve cut-off frequency
This device architecture probably is widely used in the high-frequency Graphene transistor of the small size of high-speed radiocommunication and Graphene integrated circuit.
Description of drawings
Figure 1A is the transistorized device architecture schematic diagram of the long raceway groove Graphene of tradition;
Figure 1B is the transistorized device architecture schematic diagram of traditional short channel Graphene;
Fig. 1 C is the transistorized device architecture schematic diagram of Graphene in the one embodiment of the invention;
Fig. 1 D is the transistorized device architecture vertical view of Graphene in the one embodiment of the invention, and wherein the distance L gd ' between grid and the source-drain electrode and Lgs ' are greater than 0;
Fig. 1 E is the transistorized device architecture vertical view of Graphene in the one embodiment of the invention, and wherein grid is aimed at source-drain electrode, and namely Lgd ' and Lgs ' equal 0;
Fig. 1 F is the transistorized device architecture vertical view of Graphene in the one embodiment of the invention, and wherein grid part covers source-drain electrode, and namely Lgd ' and Lgs ' are less than 0;
Fig. 2 A～Fig. 2 G is that type Graphene transistor process flow schematic diagram is buried in the source leakage on the diamond like carbon substrate of the present invention;
Fig. 3 is the device fabrication process flow figure in the one embodiment of the invention;
Fig. 4 is the filtered cathodic vacuum arc deposition system schematic diagram that deposit diamond like carbon amorphous carbon uses.
Embodiment
Below in conjunction with accompanying drawing and take embodiment as example, the present invention is described in detail.But what those skilled in the art should know is to the invention is not restricted to listed embodiment, as long as spirit according to the invention all should be included in protection scope of the present invention.
Basic principle of the present invention is as follows: diamond like carbon amorphous carbon (Diamond-like amorphous Carbon, note by abridging be DLC) film is the amorphous carbon existence form (reference: Michael Moseler.et al.The Ultrasmoothness of Diamond-like Carbon Surfaces.Science3091545 (2005)) of the very smooth rich Sp3 composition in a kind of surface.Diamond like carbon amorphous carbon chemistry stable in properties, surface trap electric charge and dangling bonds are few, and energy and the more weak п key of Graphene interface formation, can obtain mass ratio preferably interface and higher carrier mobility.And the source device architecture that leaks the type of burying can reduce the parasitic capacitance between grid and the source drain greatly, the grid elongate member lower channel length of same size is shorter, especially can be reduced to theoretically zero by the Graphene of gate electrode and the covering of source electrode drain electrode, and then greatly reduced the resistance of raceway groove, thereby improve high frequency performance and the device efficiency of Graphene transistor and integrated circuit.Such as Fig. 1 C, the present invention is buried in the source-drain electrode metal below the Graphene, under the long Lg condition of same grid, can accomplish that parasitic capacitance and channel resistance reduce simultaneously, and integrated level and the high frequency performance of device are improved simultaneously; Fig. 1 D is the transistorized device architecture vertical view of Graphene in the one embodiment of the invention, wherein between grid and the source-drain electrode distance greater than zero, namely apart; Fig. 1 E is the transistorized device architecture vertical view of Graphene in the one embodiment of the invention, and wherein grid and source-drain electrode distance equals zero, and namely aims at; Fig. 1 F is the transistorized device architecture vertical view of Graphene in the one embodiment of the invention, and wherein grid and source-drain electrode distance namely covers less than zero.
Device fabrication process flow schematic diagram below in conjunction with Fig. 3 is further described the present invention.
Step 301 please simultaneously referring to Fig. 2 A, at first provide substrate 000; The range of choice of backing material is very extensive, can be semi-conducting material, optionally comprises: silicon, germanium, polysilicon, amorphous silicon, sige alloy, III-V family, II-VI group iii v compound semiconductor material; Can be insulator also, such as plastic film, glass, silicon dioxide, silicon nitride etc.; Can be metal also, such as iron, aluminium, gold, silver, copper etc.; Backing material can be smooth, crooked, and strain is perhaps arranged.Then deposit stress-buffer layer on substrate 000, in one embodiment, deposit or thermal oxidation silicon dioxide 002, this silicon dioxide thickness scope is 5nm～1um, the stress-buffer layer of the diamond like carbon amorphous carbon 004 that will grow as the back.
Step 302, simultaneously referring to Fig. 2 A, then the high diamond like carbon amorphous carbon film 004 of deposit one deck sp3 content on stress-buffer layer silicon dioxide 002, the method of growth diamond like carbon amorphous carbon film 004 preferentially selects magnetic to filter (pulse) cathodic vacuum arc discharge deposit (FCVA) method, perhaps other optional methods: plasma enhanced chemical vapor deposition (PECVD), sputter (Sputtering), pulsed laser deposition (Pulsed laser deposition), ion beam depositing (Ion beam deposition), quality is selected ion beam depositing (Mass selected ion beam deposition) etc.
The below describes the wherein method of FCVA growth diamond like carbon amorphous carbon 004 in detail.In one embodiment of the invention, growth diamond like carbon amorphous carbon 004 uses magnetic filtered pulse cathodic vacuum arc discharge deposit (FCVA) system 410, as shown in Figure 4; Prepare high purity graphite target 400 as negative electrode, the purity of graphite target is more than 99.9%, selectivity passes into impure element or contains the gas of H element, such as silane (SiH4), ammonia (NH3), acetylene (C2H2) etc. produce carbon plasma and electronics, neutral atom and particle by cathodic vacuum arc discharge.Under the guiding of magnetic filter duct 402, neutral atom and particle are filtered, adding back bias voltage by conducting bracket 404 simultaneously on substrate 000/ silicon dioxide 002 accelerates carbon ion, almost the carbon ion bombardment of 100% ionization is to substrate 000/ silicon dioxide 002, thereby forms diamond like carbon amorphous carbon film 004 at substrate 000/ silicon dioxide 002.Wherein the carbon ion energy is regulated by add certain back bias voltage 406 at substrate.The air pressure of vacuum chamber 408 is controlled at 10-2～10-5Pa; Substrate DC bias 406 is in 20V～300V scope; Substrate 404 temperature are controlled at less than 150 ℃.
Because the diamond like carbon amorphous carbon with the FCVA growth all has the compression that magnitude range is 2～8GPa usually, therefore optionally through 30 minutes～300 minutes 400 ℃ process annealing, to discharge partly or completely compression, but still the high-insulativity of maintenance diamond like carbon, the character such as smooth surface do not change.
The sp3C-C linkage content is greater than 50% in the diamond like carbon amorphous carbon film 004 of preparation gained, less than 20%, the content of doped chemical is less than 20% greater than the content of 5%, H atom for the sp2C=C linkage content, optional doped chemical comprises the combination of one or more elements in the following element: B, N, O, F, Si, P, Cl, and metallic element; Film thickness is at 10nm～500nm; Surface roughness (RMS) is less than 5nm, and more preferably, RMS is less than 1nm.
Because the Graphene of subsequent technique is two-dimensional material, if the smooth not or surperficial inadequate cleaning of diamond like carbon amorphous carbon 004 film surface will pollute Graphene, fold is introduced local stress, even seriously reduces the mobility of the charge carrier of Graphene.Therefore to guarantee the smooth of diamond like carbon amorphous carbon film 004 surface and cleaning.
Step 303 please be simultaneously referring to Fig. 2 B, photoetching and etching source region 006 and drain region 008 on diamond like carbon amorphous carbon film 004; In a specific embodiment, etching source region 006 and drain region 008 are to adopt the oxygen/argon method for etching plasma.
Step 304, please be simultaneously referring to Fig. 2 C, then sputter multiple layer metal, the source is leaked metal and can be selected from and anyly can form with grapheme material that good ohmic contacts or the material of Schottky contacts, easily preferred and Graphene forms the metal species of good ohmic contact, in a specific embodiment, adopts palladium (palladium) and gold (aurum) to leak metal electrode as the source, the palladium of the at first gold of sputter 20nm, and then sputter 50nm; In other embodiments, the source is leaked metal and can also be selected one of following material or wherein several combination: metal: Ti, Ta, Mo, Al, W, Cu, Ni, Pt, Co; Metal nitride: TaN, TiN, TiSiN; Silicide: WSi, NiSi, CoSi, PtSi; Transparent metal oxide electrode IZO, ITO; Polysilicon, multicrystalline silicon compounds etc.
With reference to figure 1D, the metal electrode that bury in source region 012 and drain region 010 optional 1nm～100nm of (z axle) thickness on perpendicular to in-plane, be parallel to the optional 5nm～1um of conducting channel direction (x axle) length, be parallel to the plane perpendicular to conducting channel direction (y axle) width optionally at 10nm～10um.
Then carry out chemical-mechanical planarization (CMP) and obtain being buried in source region 012 and drain region 010 in the diamond like carbon amorphous carbon film 004, and form a surface 016, expose the metal in source region 012 and drain region 010 so that the grapheme material that forms with subsequent technique forms good ohmic contact or Schottky contacts, shown in Fig. 2 D.
Step 305 must clean surface 016 after the CMP, because the quality on surface 016 directly affects the carrier mobility of Graphene and the size of contact resistance.In a specific embodiment, use acetone ethanol solution ultrasonic cleaning 10～30 minutes.
Please be simultaneously referring to Fig. 2 E, then will transfer on the surface 016 after the cleaning as the Graphene 018 of conducting channel material, Graphene can be individual layer as the conducting channel material, perhaps minority layer (general 2～10 layers); Grapheme material is optionally introduced band gap by chemical doping or by applying mechanical stress, or without the grapheme material of the zero band gap of any change.
Graphene can be the method acquisition with mechanical stripping, but this method efficient is low, is not suitable for industrial applications.The perhaps individual layer that obtains of SiC material heating or the grapheme material of multilayer; Graphene also can be to utilize the method growth gained of chemical vapour deposition (CVD) (to please refer to: Li, X.S.et al.Large-area synthesis of high-quality and uniform graphene films on copper foils.Science 324,1312-1314 (2009)).
In a preferred embodiment of the invention, adopt chemical gaseous phase depositing process on the individual layer or the surface 016 of minority layer (generally being 2～10 layers of carbon atom thickness) after Graphene 018 is transferred to cleaning that Copper Foil is grown, to ask simultaneously referring to Fig. 2 E.Graphene 018 is after the Copper Foil growth is good, PMMA (polymethyl methacrylate in the spin coating on Graphene 018 at first, polymethylmethacrylate), then in FeCl3 solution, Copper Foil is dissolved, formed as being the double-layer structure 020 of Graphene under the PMMA, then (PMMA/ Graphene) 020 transferred on the surface 016, with acetone soln PMMA is dissolved, individual layer or minority layer graphene 018 just are adsorbed on the surface 016 by surperficial hydrogen bond and have stayed on diamond like carbon amorphous carbon 004 substrate again.Individual layer or minority layer graphene 018 and drain region, source region metal 010/012 just can form on good ohmic contact and the smooth surface that is adsorbed on diamond like carbon amorphous carbon 004 016 like this.
Referring to Fig. 2 F, Graphene covers the conducting channel area 0 28 between source region 012 and drain region 010 and the source-drain area at least.
Step 306 is referring to Fig. 2 F, in one embodiment, at Graphene 018 usefulness atomic layer deposition (Atomic Layer Deposition, ALD) the high K insulating medium layer 022 of method deposit HfO2/Al2O3, the Al of deposit 2nm at first, the HfO of deposit 15nm again behind the Al autoxidation
2The gate insulation medium optionally has hafnium base high K dielectric material: HfO
2, HfSiO
x, HfSiON, HfAlO
x, HfTaO
x, HfLaO
x, HfAlSiO
x, HfLaSiO
xDeng; Rare earth based high K dielectric material: ZrO
2, La
2O
3, LaAlO
3, TiO
2, Y
2O
3Tradition dielectric material SiO
2, SiON
x, Si
3N
4, Al
2O
3Deng; The dielectric material can be selected the composite multi-layer structure of one or more dielectric materials of above-mentioned material.
The quality of diamond like carbon amorphous carbon and dielectric is extremely important, because they directly contact with Graphene, comprises defective, evenness, trapped charge, foreign atom, dangling bonds, the loose look of phonon etc. directly affect the mobility of charge carrier in the Graphene in the quality of interior contact interface.
Step 307, then the splash-proofing sputtering metal layer 024, photoetching and etching metal gate electrode 026, gate electrode is transferred to the figure of gate electrode on the metal level 024 above dielectric 022 between two electrodes of source leakage, obtains metal gate electrode 026; Gate electrode is regulated and control charge transport in the conducting channel across above-mentioned gate insulation medium by electric field.The optional material of gate electrode metal is very extensive, and almost any grid metal that is applicable to modern integrated circuits can be controlled by applying voltage the charge transport process of the charge carrier in the Graphene; The distance L gd ' of source-drain electrode and gate electrode and Lgs ', namely at a distance of (Fig. 1 D) or equal zero optionally greater than zero, i.e. autoregistration (Fig. 1 E), or less than zero, namely cover (Fig. 1 F); At a distance of being not more than 40nm with the absolute figure that covers.
Step 308, step 309 and 310 is used at last with the method for CMOS process compatible and is done protective layer, and metal throuth hole is interconnected, and the backend process such as packaging and testing (BEOL) are because being technology well known in the art, so repeat no more.
So just finished present embodiment (Fig. 2 G), a kind of source on diamond like carbon amorphous carbon substrate is leaked and is buried type Graphene transistor.In conjunction with Fig. 2 G and Fig. 1 D, 1E, 1F as seen, source transistor drain electrode 010/012 of the present invention is distributed in the downside of graphene conductive raceway groove 018, gate electrode is positioned at the upside of graphene conductive raceway groove 018, the distance L gd ' of source-drain electrode and gate electrode and Lgs ' can be greater than zero namely at a distance of (Fig. 1 D), or to equal zero be autoregistration (Fig. 1 E), or namely cover (Fig. 1 F) less than zero; At a distance of being not more than 40nm with the absolute figure that covers.
Compare the main advantage of this device with traditional device architecture: 1) replace traditional SiO with diamond like carbon
2As dielectric substrate, higher as the mobility in the Graphene of conducting channel material on the substrate; 2) gate electrode and source-drain electrode are placed respectively the up and down both sides of graphene conductive raceway groove, can make the level interval between grid and the source-drain electrode little, and then make the parasitic capacitance between gate electrode and the source-drain electrode little, the channel resistance of device is little.
Two above-mentioned main advantages can significantly improve Graphene transistor high frequency performance and operating efficiency, especially improve cut-off frequency
This device architecture application prospect in high-frequency Graphene transistor and Graphene integrated circuit towards the small size of high-speed radiocommunication is extensive.
Device architecture of the present disclosure and process are not only applicable to the grapheme material transistor, and are applicable to transistor such as the carbon nanometer transistor of other material with carbon elements, and amorphous silicon, polysilicon, the thin-film transistors such as oxide.
It should be noted that above-described embodiment is example and unrestricted the present invention, those skilled in the art can design a lot of alternate embodiments and not break away from the scope of attached claims.
Claims (11)
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