CN102969244B - SJ-insulated gate bipolar transistor (SJ-IGBT) device structure and manufacturing method thereof - Google Patents
SJ-insulated gate bipolar transistor (SJ-IGBT) device structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN102969244B CN102969244B CN201210533291.1A CN201210533291A CN102969244B CN 102969244 B CN102969244 B CN 102969244B CN 201210533291 A CN201210533291 A CN 201210533291A CN 102969244 B CN102969244 B CN 102969244B
- Authority
- CN
- China
- Prior art keywords
- drift region
- region
- source
- drain terminal
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides an SJ-insulated gate bipolar transistor (SJ-IGBT) device structure and a manufacturing method thereof. The SJ-IGBT device structure comprises the following steps of: providing a substrate; forming a drift region on the substrate and presetting a source end and a drain end in the drift region; providing a first mask provided with a plurality of first windows, wherein the widths of the first windows are sequentially increased in a direction from the source end to the drain end; performing N-type ion implantation into the drift region from the first windows; annealing, and forming an N-type drift region of which the ion concentration is linearly increased in the drift region; providing a second mask provided with a plurality of second windows; performing P-type ion implantation into the N-type drift region from the second windows, wherein a certain distance is formed from a P-type column region to a drain region, and forming a P column and an N column at intervals after annealing; and finally, forming a channel region, a source region, a drain region and a gate region. The concentration of the N column is gradually increased from the source end to the drain end, and residual charges in the drift region are eliminated; and moreover, because a certain distance is formed from the P column to the drain, the influence of the charge imbalance in the drift region on the device performance is reduced, and the reliability is improved.
Description
Technical field
Invention describes a kind of SJ-IGBT device architecture, belong to microelectronics and solid electronics technical field.
Background technology
Power integrated circuit also claims high voltage integrated circuit sometimes, it is the important branch of modern electronics, can be the new-type circuit that various power conversion and energy processing unit provide high speed, high integration, low-power consumption and Flouride-resistani acid phesphatase, be widely used in electric control system, automotive electronics, display device drive, current consumption field and many key areas such as national defence, space flight such as communication and illumination.The rapid expansion of its range of application, it is also proposed higher requirement to the high tension apparatus of its core.
For power device MOSFET, under the prerequisite ensureing puncture voltage, the conducting resistance of device must be reduced as much as possible to improve device performance.But there is a kind of approximate quadratic relationship between puncture voltage and conducting resistance, formed so-called " silicon limit ".In order to solve this contradiction, forefathers propose drift region based on three-dimensional RESURF technology by the alternate super-junction structure (SJ) formed of P, N post for optimizing the drift region Electric Field Distribution of high tension apparatus.This structure, under the prerequisite keeping conducting resistance constant, improves puncture voltage, the limit of the power MOS (Metal Oxide Semiconductor) device theory that breaks traditions.The theoretical foundation of this technology is that charge compensation is theoretical, and when drift region applying voltage reaches certain value, drift region reaches and exhausts completely, and Electric Field Distribution is more even, improves the breakdown characteristics of device.Ensureing, under the prerequisite that puncture voltage is constant, significantly to improve the doping content of drift region, reduce conducting resistance." the silicon limit " of conventional power MOSFET element has been broken in the proposition of super-junction structure.
SJ structure is formed in the drift layer of device, and this drift layer comprises N conductivity type columns (column) (N post) and P conductivity type columns (column) (P post).N post and P post form the unit as a pair SJ structure, thus multipair N post and P post provide SJ structure.SJ structure is applied to vertical VDMOS device at first, expands to horizontal LDMOS device afterwards.Transversary is more conducive to the high-density power Integrated predict model of a new generation, is the focus of contemporary power device research.But super-junction structure is used for transversal device also brings new problem.The first, desirable p, n post district technique that can exhaust completely is difficult to formed.Second, substrate participates in exhausting of superjunction post district and causes substrate-assisted depletion effect, and the width of depletion layer device drain terminal to source direction diverse location not etc., this just brings the problem of drift region Electric Field Distribution inequality, needs to be optimized device making technics and structure.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of preparation method of SJ-IGBT device architecture, for solving the problem of Electric Field Distribution inequality in drift region in prior art.
For achieving the above object and other relevant objects, the invention provides a kind of preparation method of SJ-IGBT device architecture, the method comprises the following steps:
One substrate is provided;
Form drift region over the substrate and preset source and drain terminal in this drift region;
There is provided the first mask plate that is provided with some first windows, the width of described first window increases along source successively to drain terminal direction;
Be positioned over by this mask plate on described drift region, mask plate is concordant with on the left of this drift region,
N-type ion implantation is carried out to described drift region from above-mentioned first window;
Annealing, forms the N-type drift region linearly increased to drain terminal direction N-type carrier concentration along source in this drift region;
The second mask plate that one is provided with some Second Windows is provided; The left side of described Second Window is from the position adjacent with source, namely concordant initial with on the left of first occlusion part of the first mask plate, ends near described drain terminal, but has certain distance from drain terminal
Carry out P type ion implantation from this Second Window to the mode that described N-type drift region adopts three energy and dosage to reduce successively, form P post and the N post at interval; And P post discord drain terminal is connected;
Finally form raceway groove, source region, drain region and gate region.
Preferably, described annealing time is 600 ~ 1000 minutes.Described annealing temperature is 1000 ~ 1400 degree.
Preferably, three dosage summations of described P type ion implantation are 1.5-2.5 times of N-type ion implantation, preferably 2 times.
Preferably, described substrate is silicon or SOI.
Preferably, described drain region is heavy doping P.
The present invention also provides a kind of SJ-IGBT device architecture, and this structure comprises substrate; Be positioned at the drift region on this substrate; Gate region above this drift region, source at these two ends, drift region, drain terminal and spaced some P posts and N post between this source and drain terminal; And P post discord drain terminal is connected; Described P post and N post longitudinally and source, drain region longitudinally are vertical; Described N post linearly increases along source to drain terminal direction ion concentration.
Preferably, described substrate is silicon or SOI.Described gate region comprises gate dielectric layer and is positioned at the grid on gate dielectric layer.
P and the N post district alternately existed in tradition superjunction devices drift region, withstand voltage in order to improve, require that N post district and P post region reach charge balance, device reverse withstand voltage time drift region realize fully-depleted, but owing to there is substrate-assisted depletion effect, cause P Xing Zhu district to occur residual charge, the present invention adopts the N post district in linear drift district to replace traditional equally distributed N-type drift region.Effectively can eliminate substrate-assisted depletion effect, improve the puncture voltage of device.
The present invention makes the concentration of N post increase gradually from source to drain terminal, eliminates drift region residual charge.Simultaneously, by changing drain electrode N+ district into P+ district, during devices function, heavy doping P district is to drift region injected hole, increase drift region current capacity, better reduce device on resistance, because there is certain distance in P Xing Zhu district from drain electrode, because this reducing the impact of charge unbalance on device performance, improve device reliability.
Accompanying drawing explanation
Fig. 1 a is shown as the structural representation of N-type ion implantation of the present invention.
Fig. 1 b is shown as the vertical view of Fig. 1.
Fig. 2 is shown as through the LINEAR N type drift region structure schematic diagram distributing and formed of annealing.
Fig. 3 a is shown as and forms P post region structural representation.
Fig. 3 b is shown as the vertical view of Fig. 3 a.
Fig. 4 is shown as P trap and injects the structural representation forming raceway groove.
Fig. 5 is shown as the structural representation that grid is formed.
Fig. 6 is shown as the structural representation forming heavy doping N district.
Fig. 7 is shown as the structural representation forming heavy doping P district.
Fig. 8 is shown as the super junction device structure schematic diagram of body silicon.
Element numbers explanation
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to shown in Fig. 1 a to Fig. 8.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
A preparation method for SJ-IGBT device architecture, the method comprises the following steps: provide a substrate; Form drift region over the substrate and preset source and drain terminal in this drift region; There is provided the first mask plate that is provided with some first windows, the width of described first window increases along source successively to drain terminal direction; N-type ion implantation is carried out to described drift region from above-mentioned first window; Annealing, forms the N-type drift region linearly increased to drain terminal direction N-type carrier concentration along source in this drift region; The second mask plate that one is provided with some Second Windows is provided; Carry out P type ion implantation from this Second Window to the mode that described N-type drift region adopts three energy and dosage to reduce successively, form P post and the N post at interval; And P post discord drain terminal is connected; Finally form raceway groove, source region, drain region and gate region.
Described annealing time is 600 ~ 1000 minutes.Described annealing temperature is 1000 ~ 1400 degree.The dosage of described P type ion implantation is 1.5-2.5 times of N-type ion implantation, preferably 2 times.Described substrate is silicon or SOI.Described drain region is heavy doping P.
Refer to shown in Fig. 1 a ~ Fig. 8, the invention provides a kind of preparation method of SJ-IGBT device architecture, the method at least comprises the following steps:
First implementation step 1), provide semi-conductive substrate 1, in the present embodiment, this substrate is silicon or SOI substrate.Described Semiconductor substrate 1 forms drift region 2.
It should be noted that, before the described drift region of formation, can also be included in described Semiconductor substrate 1 and form resilient coating (not shown), described Semiconductor substrate 1 is arrived to prevent the depletion layer when blocking voltage, and described resilient coating is for controlling the ability of Semiconductor substrate to buffering area injected minority carrier, namely controls the injection efficiency of described Semiconductor substrate 1.
Refer to shown in Fig. 1 a, source and drain terminal (not shown) are preset in this drift region 2.Then provide one end from the first mask plate 3 of the POS INT adjacent with source, (namely this mask plate is positioned on described drift region, and mask plate is concordant with on the left of this drift region).
This first mask plate is provided with some first windows, refers to shown in Fig. 1 b, and it is the vertical view that the first mask plate 3 is positioned over above the Semiconductor substrate 1 being provided with drift region 2.In the present embodiment, described first window is the consistent rectangles of several length l, and these several first windows width d in source to the direction of drain terminal increases gradually.In other words, the width of the first mask plate occlusion part reduces to the direction of drain terminal gradually from source.Namely, in arranging along source to drain terminal direction, the width of second window 32 is larger than the width of first window 31; The width of the 3rd window 33 is larger than the width of second window 32, by that analogy.In other words, along source to drain terminal direction in arrangement, the width of first occlusion part is greater than the width of second occlusion part, and the width of second occlusion part is greater than the width of the 3rd occlusion part, by that analogy.As long as the width linearity of described window increases gradually can realize the present invention.
Concrete, in the present embodiment, the width of first window is roughly 0.6um, the width of second window is roughly 0.9um, the width of the 3rd window is roughly 1.8um, the width of the 4th window is roughly 2.3um, the width of the 5th window is roughly 3.2um, the width of the 6th window (not shown) is roughly 4.5um, the width of the 7th window (not shown) is roughly 6.2um, the width of the 8th window (not shown) is roughly 9.5um, and the width of the 9th window (not shown) is roughly 15.8um.By that analogy.
The width of first occlusion part is roughly 14.7 um, the width of second occlusion part is roughly 10.6um, the width of the 3rd occlusion part is roughly 7.5um, the width of the 4th occlusion part is roughly 5.2um, the width of the 5th occlusion part is roughly 3.1um, the width of the 6th occlusion part (not shown) is roughly 1.9um, and the width of the 7th occlusion part (not shown) is roughly 1.1um, and the width of the 8th occlusion part (not shown) is roughly 0.6um.By that analogy.
This first mask plate is placed on described drift region 2, mask plate is concordant with on the left of this drift region, N-type implantation annealing is carried out to this drift region from above-mentioned window, in arranging to drain terminal direction from source, distance between first window, 31 to the second window 32 is greater than the distance of the 3rd window 33 to the second window 32, so N-type ion diffuse after annealing, diffusion region ion concentration between first window and second window is less than the diffusion region ion concentration between the 3rd window and second window, by that analogy, the N-type drift region that ion concentration linearly distributes in source to drain terminal direction is formed in whole drift region.As shown in Figure 2.
In the present embodiment, the time of carrying out N-type implantation annealing is 600 ~ 900 minutes.Preferably 900 minutes.Annealing temperature is 1000 ~ 1200 degree.Preferably 1200 degree.
Then provide one second mask plate (not shown), this second mask plate is laterally provided with some windows 4 uniformly, and in the present embodiment, the window longitudinally on described second mask plate is the direction from source to drain terminal.The left side of wherein said window 41 is namely concordant initial with first occlusion part (from source to drain terminal number first occlusion part the widest) left side of the first mask plate from the position adjacent with source, ends near described drain terminal, but has certain distance from drain terminal.Please refer to shown in Fig. 3 b.
The mode adopting three energy and dosage to reduce successively from the window of described second mask plate carries out P type ion implantation, please refer to shown in Fig. 3 a.Concrete, the energy of P type ion implantation is 3E12-5E12, preferably 4E12 for the first time, and dosage is 300-500kev, preferably 400 kev; The energy of second time P type ion implantation is 2E12-4E12, preferably 3E12; Dosage is 200-300kev, preferably 250kev; Third time, the energy of P type ion implantation was 0.5E12-2 E12, preferably 1E12, and dosage is 50-100kev, preferably 80kev.
The dosage summation that this P type ion injects for three times is 1.5-2.5 times of this N-type ion implantation dosage, the preferably dosage of 2 times.Material is thus formed P post N post, P post N intercolumniation every the region of appearance.The not through drift region of window on described second mask plate, namely the window of this second mask plate has certain distance from drain terminal, thus P post discord drain terminal is connected.Because there is certain distance in P Xing Zhu district from drain terminal, because this reducing the impact of charge unbalance on device performance, improve device reliability.
Next through the high annealing of 10-30 minute (preferably about 20 minutes), the drift region of superjunction is formed.The drift region of high annealing formation superjunction belongs to the common practise of this area, does not repeat them here.
Then please refer to shown in Fig. 4, preparation P trap.Substrate in the present embodiment is chosen as SOI substrate, and it comprises end silicon 11, the buried regions oxide layer 12 be positioned on low level, and is positioned at the top layer silicon in buried regions oxide layer 12, for as drift region.Carry out P ion implantation in the source preset, form P trap.
Then above P trap, P post and the nearly source of N post, prepare gate region, this gate region comprises gate dielectric layer 51 and is positioned at the grid 52 on gate dielectric layer 51.In the present embodiment, the material of gate dielectric layer is that material is commonly used in this area such as silicon dioxide, silicon nitride.Please refer to shown in Fig. 5.
Then carry out heavily doped N-type injection in source near the position of gate region, form N
+region.Please refer to shown in Fig. 6.
Finally, please refer to shown in Fig. 7, on P trap, N
+the side (side away from gate region) in region and drain terminal carry out heavily doped P-type ion implantation, form P respectively separately
+region.Form raceway groove, source region, drain region.Described drain region is heavy doping P.This part belongs to the common practise of this area, does not repeat them here.
Due to P and the N post district alternately existed in traditional superjunction devices drift region, withstand voltage in order to improve, require that N post district and P post region reach charge balance, device reverse withstand voltage time drift region realize fully-depleted, but owing to there is substrate-assisted depletion effect, P Xing Zhu district is caused to occur residual charge, the present invention adopts the N post in linear drift district to replace traditional equally distributed N-type drift region, the concentration in NXing Zhu district increases from source to thread cast-off, eliminate substrate-assisted depletion effect, device is made to reach charge balance, improve device withstand voltage, this structure also can be applicable to bulk silicon technology.As shown in Figure 8.
The present invention by adopt the window of mask plate from source to drain terminal direction width increase successively, shield portions width reduces successively, ion implantation for the formation of LINEAR N post district is carried out to whole drift region, regulate ion implantation energy and dosage, then carry out a long high annealing, make N post district form a linear drift district.After linear drift district is formed, divided by P type mask plate again and carry out P type ion implantation for three times, the metering of P type ion implantation is close to 2 times of N post district, then after of short duration 20 minutes high annealings, form the drift region of superjunction, and then carry out conventional raceway groove, source region, drain region, the making of grid.
Owing to there is substrate-assisted depletion effect in horizontal SOI superjunction devices, cause from device source to drain terminal, the residual charge in P Xing Zhu district increases gradually, and the existence of P type residual charge, reduces device withstand voltage.According to existing result of study, the residual charge of p type island region distributes from source to leakage approximately linear, therefore, in the present invention, the N-type region of horizontal SOI super junction power device adopts linear distribution, the concentration in N post district is increased gradually from source to leakage, eliminates drift region residual charge, and the discord drain electrode of P Xing Zhu district is connected.Meanwhile, by changing the drain electrode N+ district of traditional superjunction devices into P+ district, be incorporated in superjunction devices design by IGBT, devices function is when ON state, and P+ district, to drift region injected hole, increases drift region current capacity, better can reduce device on resistance.Because there is certain distance in P Xing Zhu district from drain electrode, because this reducing the impact of charge unbalance on device performance, improve device reliability.Meanwhile, by changing drain electrode N+ district into P+ district, during devices function, heavy doping P district, to drift region injected hole, increases drift region current capacity, better reduces device on resistance.
In sum, the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (6)
1. a preparation method for SJ-IGBT device architecture, is characterized in that, the method comprises the following steps:
One substrate is provided;
Form drift region over the substrate and preset source and drain terminal in these both sides, drift region;
There is provided the first mask plate that is provided with some first windows, the width of described first window increases along source successively to drain terminal direction;
Be positioned over by this mask plate on described drift region, mask plate is concordant with on the left of this drift region,
N-type ion implantation is carried out to described drift region from above-mentioned first window;
Annealing, forms the N-type drift region linearly increased to drain terminal direction N-type carrier concentration along source in this drift region;
There is provided one to be positioned on drift region and be provided with the second mask plate of some Second Windows; Wherein, the left side of described Second Window is namely concordant initial with on the left of first occlusion part of the first mask plate from the position adjacent with source, ends near described drain terminal, but has certain distance from drain terminal;
Carry out P type ion implantation from this Second Window to the mode that described N-type drift region adopts three energy and dosage to reduce successively, form P post and the N post at interval; And P post discord drain terminal is connected;
Finally form raceway groove, source region, drain region and gate region.
2. the preparation method of SJ-IGBT device architecture according to claim 1, is characterized in that, described annealing time is 600 ~ 1000 minutes.
3. the preparation method of SJ-IGBT device architecture according to claim 1, is characterized in that, described annealing temperature is 1000 ~ 1400 degree.
4. the preparation method of SJ-IGBT device architecture according to claim 1, is characterized in that, three dosage summations of described P type ion implantation are 1.5-2.5 times of N-type ion implantation.
5. the preparation method of SJ-IGBT device architecture according to claim 1, is characterized in that, described substrate is silicon or SOI.
6. the preparation method of SJ-IGBT device architecture according to claim 1, is characterized in that, described drain region is heavy doping P.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210533291.1A CN102969244B (en) | 2012-12-11 | 2012-12-11 | SJ-insulated gate bipolar transistor (SJ-IGBT) device structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210533291.1A CN102969244B (en) | 2012-12-11 | 2012-12-11 | SJ-insulated gate bipolar transistor (SJ-IGBT) device structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102969244A CN102969244A (en) | 2013-03-13 |
| CN102969244B true CN102969244B (en) | 2015-03-25 |
Family
ID=47799303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210533291.1A Active CN102969244B (en) | 2012-12-11 | 2012-12-11 | SJ-insulated gate bipolar transistor (SJ-IGBT) device structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102969244B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916730A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing silicon on insulator (SOI) super-junction laterally diffused metal oxide semiconductor (LDMOS) with linear buffer layer |
| CN201887047U (en) * | 2010-12-22 | 2011-06-29 | 东南大学 | N-type super-junction laterally double-diffused metal-oxide transistor |
| CN102460652A (en) * | 2009-05-12 | 2012-05-16 | 克里公司 | Diffused junction termination structures for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same |
| CN102593007A (en) * | 2012-03-21 | 2012-07-18 | 中国科学院上海微系统与信息技术研究所 | Super junction device with multiple embedded P islands and N channels and preparation method thereof |
| CN102623345A (en) * | 2012-03-21 | 2012-08-01 | 中国科学院上海微系统与信息技术研究所 | Embedded multi-N-island P-channel hyperconjugation device and preparation method thereof |
| CN102646701A (en) * | 2012-05-04 | 2012-08-22 | 上海先进半导体制造股份有限公司 | Junction field-effect transistor (JFET) and producing method thereof |
| CN202434526U (en) * | 2011-12-21 | 2012-09-12 | 成都成电硅海科技股份有限公司 | High-voltage transverse diffusion metal-oxide semiconductor structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007027193A (en) * | 2005-07-12 | 2007-02-01 | Renesas Technology Corp | Semiconductor device, its manufacturing method and non-insulated dc/dc converter |
-
2012
- 2012-12-11 CN CN201210533291.1A patent/CN102969244B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102460652A (en) * | 2009-05-12 | 2012-05-16 | 克里公司 | Diffused junction termination structures for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same |
| CN101916730A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing silicon on insulator (SOI) super-junction laterally diffused metal oxide semiconductor (LDMOS) with linear buffer layer |
| CN201887047U (en) * | 2010-12-22 | 2011-06-29 | 东南大学 | N-type super-junction laterally double-diffused metal-oxide transistor |
| CN202434526U (en) * | 2011-12-21 | 2012-09-12 | 成都成电硅海科技股份有限公司 | High-voltage transverse diffusion metal-oxide semiconductor structure |
| CN102593007A (en) * | 2012-03-21 | 2012-07-18 | 中国科学院上海微系统与信息技术研究所 | Super junction device with multiple embedded P islands and N channels and preparation method thereof |
| CN102623345A (en) * | 2012-03-21 | 2012-08-01 | 中国科学院上海微系统与信息技术研究所 | Embedded multi-N-island P-channel hyperconjugation device and preparation method thereof |
| CN102646701A (en) * | 2012-05-04 | 2012-08-22 | 上海先进半导体制造股份有限公司 | Junction field-effect transistor (JFET) and producing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102969244A (en) | 2013-03-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103021864B (en) | Silicon On Insulator (SOI) Reduced Surface Field (RESURF) superjunction device structure and production method thereof | |
| CN107482061B (en) | Super junction device and manufacturing method thereof | |
| CN102800701A (en) | Semiconductor device having a super junction structure and method of manufacturing the same | |
| CN102194818B (en) | P-type epitaxial layer-based binary coded decimal (BCD) integrated device and manufacturing method thereof | |
| CN102097484B (en) | Multichannel LDMOS (laterally diffused metal oxide semiconductor) and preparation method thereof | |
| CN103579353B (en) | Half hyperconjugation VDMOS of buried regions assisted by a kind of P of having type | |
| CN202839620U (en) | Super junction metal oxide semiconductor field effect transistor (MOSFET) component | |
| CN101552291A (en) | Semiconductor tube of hyperconjugation longitudinal double diffusion metal oxide with N channels | |
| CN105097914A (en) | lateral dispersion metallic oxide semiconductor device and manufacturing method thereof | |
| CN102376762A (en) | Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof | |
| CN102623345B (en) | Embedded multi-N-island P-channel hyperconjugation device and preparation method thereof | |
| CN102263125B (en) | Power MOS (metal oxide semiconductor) component for transversely diffusing metallic oxides | |
| CN102593007B (en) | Super junction device with multiple embedded P islands and N channels and preparation method thereof | |
| CN108598151B (en) | Semiconductor device terminal structure capable of improving voltage endurance capability and manufacturing method thereof | |
| CN105047693A (en) | Junction termination structure of transverse high-voltage power device | |
| CN102646712A (en) | Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof | |
| CN102637744B (en) | Signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device | |
| CN103035525A (en) | Manufacturing method of high voltage isolating N type laterally diffused metal oxide semiconductor (LDMOS) component | |
| CN101777584B (en) | P-channel laterally double diffused metal oxide semiconductor device | |
| CN102969244B (en) | SJ-insulated gate bipolar transistor (SJ-IGBT) device structure and manufacturing method thereof | |
| CN103560148B (en) | A kind of junction termination structures of superjunction devices and manufacture method thereof | |
| CN100370625C (en) | Integrated high-voltage P-type LDMOS transistor structure and production thereof | |
| CN105990139A (en) | Method of manufacturing lateral diffusion metal oxide semiconductor field effect transistor | |
| CN106206677B (en) | The junction termination structures of lateral high voltage power device | |
| CN105140269A (en) | Junction termination structure of lateral high-voltage power device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |