CN102969244B - SJ-insulated gate bipolar transistor (SJ-IGBT) device structure and manufacturing method thereof - Google Patents

Abstract

The present invention provides a SJ-IGBT device structure and its manufacturing method, comprising the following steps: providing a substrate; forming a drift region on the substrate and preset source and drain ends in the drift region; providing a device with several The first mask plate of the first window, the width of the first window increases sequentially along the direction from the source end to the drain end; N-type ion implantation is performed from the first window to the drift region; annealing, in the drift region Forming an N-type drift region in which the ion concentration increases linearly; providing a second mask with a plurality of second windows; performing P-type ion implantation from the second windows to the N-type drift region, and the P-type column region is separated from There is a certain distance between the drain region, and after annealing, a spaced P column and an N column are formed; finally, a channel, a source region, a drain region and a gate region are formed. The invention gradually increases the concentration of the N column from the source end to the drain end, eliminates the residual charge in the drift region, and because the P column has a certain distance from the drain, it reduces the influence of the charge imbalance in the drift area on the performance of the device, and improves reliability . <!--1-->

Description

A kind of SJ-IGBT device structure and manufacturing method thereof

technical field

The invention introduces a SJ-IGBT device structure, which belongs to the technical field of microelectronics and solid electronics.

Background technique

Power integrated circuits are sometimes called high-voltage integrated circuits, which are an important branch of modern electronics. They can provide new circuits with high speed, high integration, low power consumption and radiation resistance for various power conversion and energy processing devices, and are widely used in electric power Daily consumption fields such as control systems, automotive electronics, display device drivers, communications and lighting, as well as many important fields such as national defense and aerospace. The rapid expansion of its application scope has also put forward higher requirements for the high-voltage devices in its core part.

For the power device MOSFET, under the premise of ensuring the breakdown voltage, the on-resistance of the device must be reduced as much as possible to improve the performance of the device. But there is an approximate quadratic relationship between breakdown voltage and on-resistance, forming the so-called "silicon limit". In order to solve this contradiction, the predecessors proposed a superjunction structure (SJ) in which the drift region is composed of P and N columns based on the three-dimensional RESURF technology to optimize the electric field distribution in the drift region of high-voltage devices. Under the premise of keeping the on-resistance constant, this structure increases the breakdown voltage and breaks the theoretical limit of traditional power MOS devices. The theoretical basis of this technology is the charge compensation theory. When the voltage applied to the drift region reaches a certain value, the drift region is completely exhausted, and the electric field distribution is more uniform, which improves the breakdown resistance of the device. Under the premise of keeping the breakdown voltage unchanged, the doping concentration of the drift region can be greatly increased to reduce the on-resistance. The proposal of the super junction structure breaks the "silicon limit" of traditional power MOSFET devices.

The SJ structure is formed in a drift layer of the device, which includes N conductivity type columns (N columns) and P conductivity type columns (P columns). N-pillars and P-pillars constitute a unit as a pair of SJ structures, so that multiple pairs of N-pillars and P-pillars provide an SJ structure. The SJ structure was initially applied to vertical VDMOS devices and later extended to lateral LDMOS devices. The lateral structure is more conducive to the new generation of high-density power integration applications, and is a hot spot in the research of contemporary power devices. However, the use of superjunction structures in lateral devices also brings new problems. First, it is difficult to form ideal p and n column regions that can be completely depleted. Second, the depletion of the substrate participating in the superjunction column region leads to the substrate-assisted depletion effect, and the width of the depletion layer varies in different positions from the drain to the source of the device, which brings the electric field in the drift region The problem of uneven distribution requires optimization of the device manufacturing process and structure.

Contents of the invention

In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for fabricating an SJ-IGBT device structure, which is used to solve the problem of uneven electric field distribution in the drift region in the prior art.

In order to achieve the above purpose and other related purposes, the present invention provides a method for preparing a SJ-IGBT device structure, the method comprising the following steps:

providing a substrate;

forming a drift region on the substrate and presetting a source terminal and a drain terminal in the drift region;

providing a first mask plate provided with several first windows, the width of the first windows increases sequentially along the direction from the source end to the drain end;

The mask plate is placed on the drift area, the mask plate is flush with the left side of the drift area,

performing N-type ion implantation from the first window to the drift region;

Annealing, forming an N-type drift region in which the concentration of N-type carriers increases linearly from the source end to the drain end in the drift region;

Provide a second reticle with several second windows; the left side of the second window is from the position adjacent to the source end, that is, flush with the left side of the first shielding part of the first reticle start and end near the drain end, but there is a certain distance from the drain end

Performing P-type ion implantation from the second window to the N-type drift region in a manner of decreasing energy and dose successively three times to form spaced P columns and N columns; and the P columns are not connected to the drain end;

Finally, channel, source, drain and gate regions are formed.

Preferably, the annealing time is 600-1000 minutes. The annealing temperature is 1000-1400 degrees.

Preferably, the sum of the three doses of the P-type ion implantation is 1.5-2.5 times, preferably 2 times, that of the N-type ion implantation.

Preferably, the substrate is silicon or SOI.

Preferably, the drain region is heavily doped with P.

The present invention also provides an SJ-IGBT device structure, which comprises a substrate; a drift region located on the substrate; a gate region located above the drift region, a source terminal and a drain terminal located at both ends of the drift region; A plurality of P columns and N columns arranged at intervals between the source terminal and the drain terminal; and the P column is not connected to the drain terminal; the longitudinal direction of the P column and the N column is perpendicular to the longitudinal direction of the source and drain regions; the N column The ion concentration increases linearly from source to drain.

Preferably, the substrate is silicon or SOI. The gate region includes a gate dielectric layer and a gate located on the gate dielectric layer.

P and N column regions alternately exist in the drift region of traditional superjunction devices. In order to improve the withstand voltage, the N column region and the P column region are required to achieve charge balance. Substrate-assisted depletion effect causes residual charges to appear in the P-type column region. The present invention uses the N-column region in the linear drift region to replace the traditional uniformly distributed N-type drift region. It can effectively eliminate the substrate-assisted depletion effect and improve the breakdown voltage of the device.

The invention gradually increases the concentration of the N column from the source end to the drain end, and eliminates the residual charge in the drift region. At the same time, by replacing the N+ region of the drain with a P+ region, when the device is working, the heavily doped P region injects holes into the drift region, increasing the current capability of the drift region, and better reducing the on-state resistance of the device. There is a certain distance between the drains, thus reducing the impact of charge imbalance on device performance and improving device reliability.

Description of drawings

Fig. 1a shows a schematic diagram of the structure of N-type ion implantation in the present invention.

Figure 1b shows a top view of Figure 1 .

FIG. 2 is a schematic diagram showing the structure of a linear N-type drift region formed by annealing and redistribution.

Figure 3a shows a schematic diagram of the structure for forming the P-pillar region.

Figure 3b shows a top view of Figure 3a.

FIG. 4 shows a schematic diagram of the structure of a channel formed by P-well implantation.

FIG. 5 shows a schematic diagram of the structure formed for the gate.

FIG. 6 shows a schematic diagram of the structure for forming a heavily doped N region.

FIG. 7 shows a schematic structural diagram for forming a heavily doped P region.

FIG. 8 shows a schematic diagram of a superjunction device structure of bulk silicon.

Component designation description

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figure 1a to Figure 8. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

A method for preparing a SJ-IGBT device structure, the method comprising the following steps: providing a substrate; forming a drift region on the substrate and presetting source and drain terminals in the drift region; providing a device with a plurality of first The first mask plate of the window, the width of the first window increases sequentially along the direction from the source end to the drain end; N-type ion implantation is performed from the first window to the drift region; annealing forms an edge along the drift region An N-type drift region in which the concentration of N-type carriers increases linearly from the source end to the drain end; a second mask with a plurality of second windows is provided; three times are used from the second window to the N-type drift region P-type ion implantation is carried out in a manner of decreasing energy and dose in order to form spaced P columns and N columns; and the P columns are not connected to the drain end; finally, the channel, source region, drain region and gate region are formed.

The annealing time is 600-1000 minutes. The annealing temperature is 1000-1400 degrees. The dose of the P-type ion implantation is 1.5-2.5 times, preferably 2 times, that of the N-type ion implantation. The substrate is silicon or SOI. The drain region is heavily doped with P.

Please refer to Figures 1a to 8, the present invention provides a method for preparing a SJ-IGBT device structure, the method at least includes the following steps:

First, step 1) is implemented, and a semiconductor substrate 1 is provided. In this embodiment, the substrate is a silicon or SOI substrate. A drift region 2 is formed on the semiconductor substrate 1 .

It should be noted that, before forming the drift region, a buffer layer (not shown) may also be formed on the semiconductor substrate 1 to prevent the depletion layer from reaching the semiconductor substrate 1 when the voltage is blocked. , and the buffer layer is used to control the ability of the semiconductor substrate to inject minority carriers into the buffer, that is, to control the injection efficiency of the semiconductor substrate 1 .

Referring to FIG. 1 a , a source terminal and a drain terminal (not shown) are preset on the drift region 2 . Then provide a first mask 3 whose end starts from a position adjacent to the source end (that is, the mask is placed on the drift region, and the mask is flush with the left side of the drift region).

Several first windows are provided on the first mask, as shown in FIG. 1 b , which is a top view of the first mask 3 placed above the semiconductor substrate 1 provided with the drift region 2 . In this embodiment, the first windows are several rectangles with the same length l, and the width d of the several first windows gradually increases from the source terminal to the drain terminal. In other words, the width of the shielding portion of the first mask gradually decreases from the source end to the drain end. That is, in the arrangement along the direction from the source end to the drain end, the width of the second window 32 is larger than the width of the first window 31; the width of the third window 33 is larger than the width of the second window 32, and so on. In other words, in the arrangement along the direction from the source terminal to the drain terminal, the width of the first shielding portion is greater than the width of the second shielding portion, the width of the second shielding portion is greater than the width of the third shielding portion, and so on. The present invention can be implemented as long as the width of the window increases linearly.

Specifically, in this embodiment, the width of the first window is approximately 0.6um, the width of the second window is approximately 0.9um, the width of the third window is approximately 1.8um, and the width of the fourth window is approximately 2.3um. um, the width of the fifth window is approximately 3.2um, the width of the sixth window (not shown) is approximately 4.5um, the width of the seventh window (not shown) is approximately 6.2um, and the width of the eighth window ( Not shown) has a width of approximately 9.5um, and the ninth window (not shown) has a width of approximately 15.8um. And so on.

The width of the first shading part is about 14.7um, the width of the second shading part is about 10.6um, the width of the third shading part is about 7.5um, the width of the fourth shading part is about 5.2um, and the width of the fifth The width of the first shielding part is approximately 3.1um, the width of the sixth shielding part (not shown) is approximately 1.9um, the width of the seventh shielding part (not shown) is approximately 1.1um, and the eighth shielding part ( Not shown) has a width of approximately 0.6um. and so on.

The first mask plate is placed on the drift region 2, the mask plate is flush with the left side of the drift region, and annealing is performed after N-type ion implantation from the above-mentioned window to the drift region. In the end direction arrangement, the distance between the first window 31 and the second window 32 is greater than the distance between the third window 33 and the second window 32, so after annealing, N-type ions diffuse, and the first window and the second window The ion concentration in the diffusion region between the two windows is less than the ion concentration in the diffusion region between the third window and the second window, and so on, forming a linear distribution of ion concentration in the direction from the source end to the drain end in the entire drift region. N-type drift region. as shown in picture 2.

In this embodiment, the annealing time after the N-type ion implantation is 600-900 minutes. Preferably 900 minutes. The annealing temperature is 1000-1200 degrees. Preferably 1200 degrees.

Then provide a second mask plate (not shown), the second mask plate is uniformly provided with a number of windows 4 in the horizontal direction, in this embodiment, the longitudinal direction of the window on the second mask plate is from direction from source to drain. Wherein the left side of the window 41 is flush with the left side of the first shielding part (the first and widest shielding part counting from the source end to the drain end) of the first mask from the position adjacent to the source end It starts and ends near the drain end, but there is a certain distance from the drain end. Please refer to Figure 3b.

The P-type ion implantation is performed from the window of the second mask using three times of sequentially decreasing energy and dose, as shown in FIG. 3 a . Specifically, the energy of the first P-type ion implantation is 3E12-5E12, preferably 4E12, and the dose is 300-500kev, preferably 400kev; the energy of the second P-type ion implantation is 2E12-4E12, preferably It is 3E12; the dose is 200-300kev, preferably 250kev; the energy of the third P-type ion implantation is 0.5E12-2 E12, preferably 1E12, and the dose is 50-100kev, preferably 80kev.

The sum of the three implanted doses of the P-type ions is 1.5-2.5 times, preferably twice, the dose of the N-type ion implanted. In this way, the area where the P-pillar, N-column, and P-pillar-N-column intervals appear is formed. The window on the second mask plate does not penetrate the drift region, that is, the window of the second mask plate has a certain distance from the drain end, so that the P column is not connected to the drain end. Since there is a certain distance between the P-type column region and the drain end, the influence of the charge imbalance on the performance of the device is reduced, and the reliability of the device is improved.

Next, after a high temperature annealing for 10-30 minutes (preferably about 20 minutes), the drift region of the super junction is formed. The formation of the drift region of the superjunction by high temperature annealing belongs to the common knowledge in the field, and will not be repeated here.

Next, please refer to FIG. 4 to prepare a P well. The substrate in this embodiment is selected to be an SOI substrate, which includes bottom silicon 11 , buried oxide layer 12 on the lower position, and top silicon on the buried oxide layer 12 for use as a drift region. Perform P ion implantation at the preset source to form a P well.

Then prepare a gate area above the P well, P column and N column near the source end, the gate area includes a gate dielectric layer 51 and a gate 52 on the gate dielectric layer 51 . In this embodiment, the material of the gate dielectric layer is silicon dioxide, silicon nitride and other commonly used materials in the field. Please refer to Figure 5.

Next, a heavily doped N-type implant is performed at a position close to the gate region at the source end to form an N ⁺ region. Please refer to Figure 6.

Finally, please refer to FIG. 7, perform heavily doped P-type ion implantation on the P well, the side of the N ⁺ region (the side away from the gate region), and the drain end to form a P ⁺ region respectively. Channel, source and drain regions are formed. The drain region is heavily doped with P. This part belongs to the common knowledge in this field, and will not be repeated here.

Due to the alternate existence of P and N column regions in the drift region of traditional superjunction devices, in order to improve the withstand voltage, the N column region and the P column region are required to achieve charge balance, and the drift region is fully depleted when the device reverses the withstand voltage, but Due to the existence of the substrate-assisted depletion effect, residual charges appear in the P-type column region. The present invention uses the N-type column in the linear drift region to replace the traditional uniformly distributed N-type drift region, and the concentration of the N-type column region increases linearly from the source to the drain. , eliminates the substrate-assisted depletion effect, enables the device to achieve charge balance, and improves the withstand voltage of the device. This structure can also be applied to bulk silicon technology. As shown in Figure 8.

In the present invention, the width of the window of the mask plate increases sequentially from the source end to the drain end, and the width of the shielding part decreases sequentially, and ion implantation is performed on the entire drift area to form a linear N-column area, and the ion implantation energy and dose are adjusted. , and then perform a long-time high-temperature annealing to make the N-column region form a linear drift region. After the linear drift region is formed, P-type ion implantation is performed three times through the P-type mask. The metering of P-type ion implantation is close to twice that of the N-column region, and then a short 20-minute high-temperature annealing is performed to form a superjunction The drift region, and then the conventional channel, source region, drain region, and gate are fabricated.

Due to the substrate-assisted depletion effect of lateral SOI superjunction devices, the residual charge in the P-type column region gradually increases from the source end to the drain end of the device. The existence of P-type residual charge reduces the withstand voltage of the device. According to the existing research results, the residual charge in the P-type region is approximately linearly distributed from source to drain. Therefore, the N-type region of the lateral SOI superjunction power device in the present invention adopts a linear distribution, so that the concentration of the N column region is from source to drain. Gradually increase to eliminate the residual charge in the drift region, while the P-type column region is not connected to the drain. At the same time, by replacing the drain N+ region of the traditional super-junction device with a P+ region, the IGBT is introduced into the design of the super-junction device. When the device is in the on state, the P+ region injects holes into the drift region to increase the current capability of the drift region. , can better reduce the on-state resistance of the device. Since there is a certain distance between the P-type column region and the drain, the influence of the charge imbalance on the device performance is reduced, and the reliability of the device is improved. At the same time, by replacing the drain N+ region with a P+ region, when the device is working, the heavily doped P region injects holes into the drift region, increasing the current capability of the drift region, and better reducing the on-state resistance of the device.

To sum up, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (6)

1. a preparation method of SJ-IGBT device structure, is characterized in that, the method comprises the following steps: providing a substrate; forming a drift region on the substrate and presetting source and drain terminals on both sides of the drift region; providing a first mask plate provided with several first windows, the width of the first windows increases sequentially along the direction from the source end to the drain end; The mask plate is placed on the drift area, the mask plate is flush with the left side of the drift area, performing N-type ion implantation from the first window to the drift region; Annealing, forming an N-type drift region in which the concentration of N-type carriers increases linearly from the source end to the drain end in the drift region; Provide a second reticle placed on the drift region and provided with a plurality of second windows; wherein, the left side of the second window is from the position adjacent to the source end, that is, the first reticle of the first reticle. The left side of each shielding part starts flush with the left side and ends near the drain end, but there is a certain distance from the drain end; Performing P-type ion implantation from the second window to the N-type drift region in a manner of decreasing energy and dose successively three times to form spaced P columns and N columns; and the P columns are not connected to the drain end; Finally, channel, source, drain and gate regions are formed. 2. The method for preparing the SJ-IGBT device structure according to claim 1, characterized in that the annealing time is 600-1000 minutes. 3. The method for preparing the SJ-IGBT device structure according to claim 1, characterized in that the annealing temperature is 1000-1400 degrees. 4. The manufacturing method of the SJ-IGBT device structure according to claim 1, characterized in that the sum of the three doses of the P-type ion implantation is 1.5-2.5 times that of the N-type ion implantation. 5. The method for preparing the SJ-IGBT device structure according to claim 1, wherein the substrate is silicon or SOI. 6 . The method for preparing the SJ-IGBT device structure according to claim 1 , wherein the drain region is heavily doped with P. 7 .