CN102945291A - High-speed image acquisition memory card based on PCI-E (Peripheral Component Interconnect-Express) - Google Patents

Abstract

The invention discloses a high-speed image acquisition memory card based on PCI-E (Peripheral Component Interconnect-Express), which comprises an optical fiber transmission module, an A/D conversion module, an FPGA (Field-Programmable Gate Array) logic module, an EPCS (Electronic Propulsion Control System) logic program memory module, a JTAG (Joint Test Action Group) program download interface, an SATA (Serial Advanced Technology Attachment) hard disk data memory module, an SDRAM (Synchronous Dynamic Random Access Memory) module, a bridge chip and a PCI-E interface, wherein the optical fiber transmission module is connected with the A/D conversion module; the PCI-E interface is connected with the bridge chip; the A/D conversion module, the EPCS logic program memory module, the JTAG program download interface, the SATA hard disk data memory module, the SDRAM module and the bridge chip are connected with the FPGA logic module respectively. Therefore, high-speed image acquisition can be realized fast.

Description

High-speed image sampling storage card based on PCI-E

Technical field

The invention belongs to the high-speed image sampling field, particularly a kind of high-speed image sampling storage card based on PCI-E.

Background technology

Image and people's productive life is closely bound up, is that the mankind obtain the main source with exchange message, and human according to statistics have the information more than 80% to come from image.Exhibition along with computing machine and video technique and hardware technology, image acquisition is widely used at electronic communication and field of information processing, for example digital radio TV, the network media, supervisory system etc., the visual plant that the video image acquisition storage card is used as computer video, bearing simulating signal to the task of digital signal conversion, in the modern media system in occupation of important position.Design a kind of flexible function, easy to use, the video signal collective circuit of being convenient to be embedded in the system has important Practical significance.

Image capturing system comprises image acquisition, image transmitting, image storage, image processing and graphical analysis etc.Traditional image capturing system is a kind of system based on personal computer (PC).The image acquisition storage card partly be responsible for obtaining, gathering and controlling of picture signal and with high speed data transfer and the corresponding control of intercomputer, PC is partly finished the functions such as the storage, demonstration of picture signal.The image acquisition storage card occupy core status in image capturing system undoubtedly.

Relatively several PC video interfaces of main flow are VGA interface, DVI interface and HDMI interface at present.Comparatively speaking, the VGA interface is relatively backward, but because it remains the substandard that at present maximum manufacturers support, so its range of application is the most widely.Because VGA interface outputting analog signal, in the situation that resolution improves, the shown image of VGA signal has obvious distortion.

The DVI interface is a kind of digital visual interface, the video resolution that its support is higher.The DVI interface is particularly suitable for the vision signal input as liquid crystal display, can bring into play to greatest extent the little advantage of liquid crystal display sharpness hi-vision distortion.But the DVI interface is larger, has affected usability.

The HDMI interface is present very novel a video interface, and it is the upgrade version of DVI interface.Except output digit signals, support that beyond the high-resolution, it is output audio signal simultaneously.And the HDMI interface is very small and exquisite, and is easy to use.But present, HDMI interface price is partially expensive.

Release along with pci bus, present image acquisition storage card is by the characteristics of the linear burst transfer of pci bus, can adopt the image acquisition mode of computer-oriented storer, be after analog image passes through A/D converter, be stored in first (the general capacity that only need several K) in the impact damper of pci bus product self, behind buffer full directly the physical storage of image data transmission to computing machine.Therefore circuit design is comparatively simplified, cost is low, picking rate is fast, data transmission is smooth, substantially satisfies the image acquisition request of 24 frames/s.And along with the proposition of PCI-E bus, the speed with data transmission rises to a new step again.

As third generation high-performance IO bus, its bus structure have been taked the change of essence: parallel bus becomes universal serial bus, and number of pins reduces widely; The interconnection of point-to-point.These changes have not only improved the speed of data transmission, and have reduced widely the cost of circuit design.This bus is applied in the video frequency collection card, not only can alleviates the unmatched contradiction of data throughput rate, can also simplify the design of circuit.

Summary of the invention

The object of the present invention is to provide a kind of image acquisition storage card based on the PCI-E bus, thereby realize fast the method for the collection of high speed image.

The technical solution that realizes the object of the invention is: a kind of high-speed image sampling storage card based on PCI-E, comprise optical fiber transmission module, the A/D modular converter, the fpga logic module, EPCS logical program memory module, JTAG program download interface, SATA hard disc data memory module, the SDRAM module, bridge chip and PCI-E interface, optical fiber transmission module is connected with the A/D modular converter, the PCI-E interface is connected with bridge chip, the A/D modular converter, EPCS logical program memory module, JTAG program download interface, SATA hard disc data memory module, the SDRAM module is connected with bridge chip with the fpga logic module and is connected, the PCI-E interface is identified by PC by the WDM driver, optical fiber transmission module advances the A/D modular converter with the image transmission that gathers, the A/D modular converter is converted into the digital signal serial input to the fpga logic module with simulating signal, in this fpga logic module, the data recombination of image will be finished, the combination of pci data structure, the generation of control signal with cooperate; EPCS logical program memory module is carried out the FPGA application configuration after integrated circuit board powers on, and finishes the initialization of fpga logic module; JTAG program download interface is FPGA program transmission channel, by this interface, can be with program Solidification to EPCS logical program memory module, SATA hard disc data memory module is finished the fpga logic module to the permanent storage of image deal with data, finish the combination of SATA data structure and control signal by this module, the SDRAM module realizes string and conversion and the storage of image data, for follow-up PCI-E data structure is prepared the transmission of data; Bridge chip will be finished pci signal that the fpga logic module transmits out to the conversion of PCI-E.

The present invention compared with prior art, its remarkable advantage: (1) PCI-E is the I/O bus structure of a new generation, different from the conventional bus structure is that it has adopted point-to-point mode connected in series, each equipment has the special use of oneself to connect, do not need as conventional bus, to share bandwidth, therefore can reach the high bandwidth that the parallel buss such as PCI, AGP can not provide.(2) specification of PCI-E bus does not wait to 32 passages from 1 passage, its 1 passage one-way transmission bandwidth can reach 250MBytes/s, 8 passage one-way transmission bandwidth can reach 2GBytes/s, and the one-way transmission bandwidth of 32 passages can reach 8GBytes/s, can satisfy the different system equipment demand different to data transfer bandwidth.(3) PCI-E adopts serial mode to transmit data, has reduced the pin number of interface, has reduced volume and the cost of PCI-E equipment.(4) based on the image capturing system of PCI-E bus, the message transmission rate of energy Effective Raise system is the effective solution of the Real-time Image Collecting System of high frame frequency, big data quantity.(5) simultaneously in the inner PCI principal and subordinate module that realizes of FPGA, realized configuration space and IO space register from module, primary module is realized dma controller.During data transmission, virtual realization primary module in fact by hardware interface, realizes that primary module is to the DMA burst transfer of PC to the data transmission from module.(6) use bridge chip to carry out the conversion of PCI-PCIE, solve the high problem of FPGA stone cost.Design the SATA interface module, realized the large data disk array stores of processing, made things convenient for backup and the inquiry of data.

Below in conjunction with accompanying drawing the present invention is described in further detail.

Description of drawings

Fig. 1 is entire block diagram of the present invention.

Fig. 2 is fpga logic inside modules block diagram.

Fig. 3 is the AD interface module interface definition of fpga chip.

Fig. 4 is AD interface module programming flowchart.

Fig. 5 is the definition of SDRAM memory read/write module input and output pin.

Fig. 6 is simulation pci bus data transmission principle figure.

Fig. 7 is PCISlave module interface schematic diagram.

Fig. 8 is pc access input/output space basic flow sheet.

Fig. 9 is PCIMaster module interface schematic diagram.

Figure 10 is PCIMaster module status state transition diagram.

Figure 11 is WDM driver workflow diagram.

Figure 12 is the overall flow of driver and application program operation.

Embodiment

In conjunction with Fig. 1, the present invention is based on the high-speed image sampling storage card of PCI-E, comprise optical fiber transmission module, the A/D modular converter, the fpga logic module, EPCS logical program memory module, JTAG program download interface, SATA hard disc data memory module, the SDRAM module, bridge chip and PCI-E interface, optical fiber transmission module is connected with the A/D modular converter, the PCI-E interface is connected with bridge chip, the A/D modular converter, EPCS logical program memory module, JTAG program download interface, SATA hard disc data memory module, the SDRAM module is connected with bridge chip with the fpga logic module and is connected, the PCI-E interface is identified by PC by the WDM driver, optical fiber transmission module advances the A/D modular converter with the image transmission that gathers, the A/D modular converter is converted into the digital signal serial input to the fpga logic module with simulating signal, in this fpga logic module, the data recombination of image will be finished, the combination of pci data structure, the generation of control signal with cooperate; EPCS logical program memory module is carried out the FPGA application configuration after integrated circuit board powers on, and finishes the initialization of fpga logic module; JTAG program download interface is FPGA program transmission channel, by this interface, can be with program Solidification to EPCS logical program memory module, SATA hard disc data memory module is finished the fpga logic module to the permanent storage of image deal with data, finish the combination of SATA data structure and control signal by this module, the SDRAM module realizes string and conversion and the storage of image data, for follow-up PCI-E data structure is prepared the transmission of data; Bridge chip will be finished pci signal that the fpga logic module transmits out to the conversion of PCI-E.

In conjunction with Fig. 2, the fpga logic module that the present invention is based on the high-speed image sampling storage card of PCI-E comprises the Arbiter arbitration modules, SDRAM memory read/write module, fpga chip, the PCIMaster module, the PCISlave module, the Arbiter arbitration modules, SDRAM memory read/write module, the signal of PCIMaster module and PCISlave module links to each other with the pin of fpga chip respectively, for guaranteeing data integrity and sequential relationship, to the AD data of gather the storage of rattling respectively, produce A and two passages of B, buffer memory advances configurable two AD_FIFO of fpga chip respectively, by the Arbiter arbitration modules data that gather is read and write control operation; SDRAM memory read/write module is data buffer storage, recombination module, it is responsible for that the AD interface module table tennis from fpga chip is write two viewdata signals the AD_FIFO and reads, deposit in the outside SDRAM module, after one frame data have stored, it takes out the view data in the SDRAM module more successively, put among the configurable PCI_FIFO of fpga chip, wait for calling of PCIMaster module; The virtual PCI of PCISlave module produces control signal from equipment by PCIMaster, cooperates PCI_FIFO, data virtual is sent to the PCISlave module, and be transferred to bridge chip by the PCISlave module; The PCIMaster module is read sampled data for function and the sequential of simulation PCI main equipment from PCI_FIFO, then initiate the DMA write operation, the data communication device that gathers is crossed Virtual PC I pass to PC from equipment through bridge chip.

In conjunction with Fig. 3 and Fig. 4, the AD interface module of fpga chip comprises the signal sum counter, signal be dataclk,, RGB_A, hsync, vsync, cmd_pc, data_AD, call_AD_rdreq, AD_fifo_ack, ckinv, wherein dataclk is the input dot frequency, RGB_A is for changing the rear video sampled signal through AD, hsync is the line frequency signal, vsync is the field frequency signal, cmd_pc is the control signal of PC input, resolution and the refreshing frequency of the current collection image of notice AD interface module; Data_AD is the video sampling signal of output, call_AD_rdreq is zone bit, when delegation's signal data has stored set when complete in AD_FIFO, AD_fifo_ack has run through the time set of data line in SDRAM memory read/write module from AD_FIFO; Ckinv is the clock energizing signal, and concrete signal flows to and is:

(1) after PC is initiated image acquisition, the AD interface module receives the control signal Cmd_pc that transmits from PC, therefrom obtains the resolution of current collection image, refreshing frequency;

(2) wait for that the field frequency signal is effective, after the field frequency signal is effective, enter waiting status, wait for beginning to gather after the line frequency signal effectively; (general field frequency signal, line frequency signal put 1 for effective)

(3) when the line frequency signal effectively after, open counter, to AD_FIFO storage carrier chrominance signal, count down to given resolution after, delegation's image data acquiring is complete, and all sends into AD_FIFO, stops storage, counter O reset;

(4) then notice SDRAM memory read/write module reading out data repeats top operation, until the data storage is complete.

In conjunction with Fig. 5, the SDRAM memory read/write module that the present invention is based on the high-speed image sampling storage card of PCI-E comprises clock clk100, AD_data, data_RGB, call_AD_rdreq, AD_fifo_ack, cmd_pc, pci_rd_ack, pci_rd_en, ram_data, cmd, cmdack, dm, clock clk100 is 100MHz, AD_data is that the AD interface module writes the view data among the AD_FIFO, the view data of data_RGB for from the SDRAM module, reading in, call_AD_rdreq has stored complete rear set, AD_fifo_ack set the SDRAM module runs through data line from AD_FIFO after at delegation's signal data in AD_FIFO; Cmd_pc is the control signal of importing into from PC, includes current acquisition resolution, refreshing frequency; Pci_rd_ack is the PCIMaster module has run through data line from PCI_FIFO sign, pci_rd_en is for depositing data line in the sign among the PCI_FIFO, ram_data is the data of input SDRAM module, ram_addr is the SDRAM module stores address of choosing, and cmd, cmdack, dm are the control signal of SDRAM module; Concrete signal flows to:

(1) reads in the cmd_pc command signal from the PCIMaster module, determine counting of the line number that needs in the SDRAM module and every row;

(2) initialization SDRAM module configures the SDRAM module after waiting for, write the inside of SDRAM module by address wire ram_addr and deposit, and then the configuration read-write mode waits for several time-delays; After configuration is finished, the operation of reading and writing the SDRAM module.

In conjunction with Fig. 7 and Fig. 8, the interface definition of PCISlave module that the present invention is based on the high-speed image sampling storage card of PCI-E is: clk is the frequency of operation 55Mhz of PCI, rst is reset signal, frame, irdy, cbe[3..0], trdy, devsel, stop, paren1, ad[31..0], intb, intc, intd, reqb, serr, perr, ext_add[21..0] be respectively the PCISlave module by signal, data_rd_out is PC read operation sign, data_wr is host computer write operation sign, iosel is the IO operation flag, memsel is the storage operation sign, dmasel is the dma operation sign, ext_add[21..0] be the PCIMaster register address; The PCISlave module realizes preparation input/output space register, with control DMA data transmission procedure, and the basic function of access input/output space register, the flow direction of concrete signal is:

(1) PC issues configuration signal, PCISlave module receive data order cbe[3..0], judgement order validity and order character;

(2) PCISlave inside modules state machine according to the order redirect, and read in ad[31..0] address information;

(3) PCISlave module output ext_add[21..0] low eight to the IO space address to PCISlave module mask register;

(4) the PCISlave module enables the data_rd_out signal, allows PCIMaster module accesses ad[31..0] address space;

(5) whether decision signal irdy is 0, is 0, then allows the PCIMaster module to read configuration data, writes register, and registration finishes.

In conjunction with Fig. 9 and Figure 10, the interface definition of PCIMaster module that the present invention is based on the high-speed image sampling storage card of PCI-E is: clk is PCI frequency of operation 55MHz, rst is reset signal, cmd_pc[31..0] be the resolution command interface of PC transmission, pci_rd_ack is the PCIMaster module has run through data line from PCI_FIFO sign, pci_rd_en is that the SDRAM module has deposited data line in the sign among the PCI_FIFO, the state transitions process of PCIMaster module is: at first by PC simulation PCI main equipment register is configured, such as interrupt register int_reg, DMA transmits first address register head_reg, DMA transmits sized registers count_reg, command dma register master_reg, command register cmd_pc; Then wait for the SDRAM module deposit data line in PCI_FIFO and make pci_rd_en effectively after, initiate the DMA write operation, data reading among the PCI_FIFO is passed to PC from equipment through bridge chip by simulation PCI, after from PCI_FIFO, running through data line, make pci_rd_ack effective, request SDRAM memory read/write module is read the next line data and is deposited PCI_FIFO in from the SDRAM module, so move in circles, until transmit frame data complete.

The below further describes the high-speed image sampling storage card that the present invention is based on PCI-E from the angle of design.

In conjunction with Fig. 1, the present invention is based on the high-speed image sampling storage card of PCI-E, the specific implementation step is as follows:

The first step, select the EP1C12F324 FPGA of altera corp as the digital signal processing core chip, because it has 1.2 ten thousand logical blocks (LE), 249 I/O mouths with various modes, core voltage is 1.5V, and low-power consumption can directly connect peripheral various interface device, such as AD converter, SDRAM storage chip etc.The A/D of image input end or decoder module are selected the AD9888 of ADI company, because this chip can be supported the image acquisition under the 1600x1280 resolution, and binary channels output, the highest sample frequency can reach 205MHz, meets the requirement of design.SDRAM selects the HY57V28820HCT-K of Modern Corporation, and it is that a capacity is 128M bytes, and the highest support of clock frequency 133MHz has 8 bit memories of 4 Bank, can store the image under the above 1600x1280 resolution of 2 frames, meets design requirement.Owing to existing and a large amount of data communication of computing machine, we have selected * 1 PCI-E bus structure.Its theoretical velocity can reach 250MB/s, and computer control is convenient.In order to reduce design difficulty, selected a PCI to the PEX8111 of the bridging chip PLX company of PCI-E, can easily realize the PCI-E bus to the conversion of pci bus by it, wherein the PCI-E interface links to each other with PC, pci interface links to each other with hardware, and the pci bus sequential is realized by the FPGA internal processes.

Second step, among the present invention, the FPGA program has realized the control to image acquisition and data transmission procedure.Difference according to each function, roughly can be divided into eight modules, they are respectively optic module, AD9888 data acquisition module, SDRAM memory read/write module, PCIMaster module, PCISlave module, I2C bus configuration module and Arbiter arbitration modules and SATA interface module.In addition also used some free IP core that Altera carries, such as asynchronous twoport FIFO, PLL frequency multiplier and SDRAM Controller module etc., system chart is as shown in Figure 1, 2.

The 3rd step, as shown in Figure 3, wherein, dataclk is the input dot frequency, and RGB_A is for changing the rear video sampled signal through AD, hsync is the line frequency signal, vsync is the field frequency signal, and cmd_pc is the control signal of computer input, and he mainly notifies resolution and the refreshing frequency of the current collection image of AD9888 data acquisition module, data_AD is the video sampling signal of output

Call_AD_rdreq is zone bit, when delegation's signal data has stored set when complete in AD_FIFO, AD_fifo_ack has run through the time set of data line in SDRAM memory read/write module from AD_FIFO, ckinv is the clock energizing signal, other be FIFO control signal and test signal.The specific works flow process is:

(1) after PC initiates image acquisition, the AD9888 data acquisition module receives the control signal Cmd_pc that transmits from PC, therefrom obtains the resolution of current collection image, the information such as refreshing frequency.

(2) wait for that field frequency signal (vsync) is effective, after the field frequency signal is effective, enter waiting status, wait for beginning to gather after line frequency signal (hsync) effectively.

(3) after the line frequency signal is effective, open counter, (for example resolution is in the 800x600 situation, counter is 800) to FIFO storage carrier chrominance signal (data_AD), count down to 800 points after, delegation's image data acquiring is complete, and all send into FIFO, stop storage, counter O reset.

(4) then notice SDRAM memory read/write module reading out data repeats top operation, until the data storage is complete.FPGA internal processes process flow diagram such as Fig. 4 of AD9888 interface module.

The 4th step, SDRAM memory read/write module, as shown in Figure 5, clock clk100 is 100MHz, AD_data is that AD9888 writes the view data among the AD_FIFO, the view data of data_RGB for reading in from the SDRAM module, call_AD_rdreq has stored complete rear set, AD_fifo_ack set the SDRAM module runs through data line from AD_FIFO after at delegation's signal data in AD_FIFO.Cmd_pc is the control signal of importing into from host computer, includes current acquisition resolution, the information such as refreshing frequency.Pci_rd_ack is the PCIMaster module has run through data line from PCI_FIFO sign, pci_rd_en is for depositing data line in the sign among the PCI_FIFO, ram_data is the data of input SDRAM module, ram_addr is the SDRAM module stores address of choosing, cmd, cmdack, dm are the control signal of SDRAM module, and other signal is the control signal of AD_FIFO and PCI_FIFO.

The workflow of this module is:

(1) reads in the cmd_pc command signal from the PCIMaster module, determine counting of the line number that needs in the SDRAM module and every row.

(2) initialization SDRAM module needs 200us ability steady operation after hardware powers on, configure the SDRAM module after waiting for.Mainly be to deposit (mode_register) by the inside that address wire ram_addr writes the SDRAM module, the configuration read-write mode.Native system adopts the burst read-write, and the output data are take page or leaf as unit.Then wait for several time-delays.After configuration is finished, the operation of reading and writing the SDRAM module.

The 5th the step, as shown in Figure 6, PCIMster module, PCISlave module simulated respectively in the pci bus data transmission main equipment and from equipment.Mutual by the control signal wire between these two modules, simulated a virtual data channel, data are sent into from equipment from main equipment.But real data do not send into the PCISlave module simulation from equipment.But by the conversion of PEX8111 bridge chip, sent into the PCI-E bus, finally sent into the internal memory of PC.The Main Function of PCISlave module is function and the sequential of simulation PCI " target device ", realizes the formulation space of PCI equipment, finishes initial configuration to it by host computer by the PEX8111 bridging chip.Receive the control information that host computer is sent, by signal the PCIMaster module is controlled.Realize the access of input/output space register.The interface definition of PCISlave module as shown in Figure 7,

Wherein, clk is the frequency of operation 55Mhz of PCI, rst is reset signal, frame, irdy, cbe[3..0], trdy, devsel, stop, paren1, ad[31..0], intb, intc, intd, reqb, serr, perr be respectively PCI local bus signal, data_rd_out is host computer read operation sign, data_wr is host computer write operation sign, iosel is the IO operation flag, memsel is the storage operation sign, dmasel is the dma operation sign, ext_add[21..0] be PCI " main equipment " register address.

A main task of this module realizes preparing the input/output space register exactly, with control DMA data transmission procedure.Access the basic procedure of input/output space register as shown in Figure 8:

The 6th step, the PCIMaster modular design as shown in Figure 9, wherein, clk is PCI frequency of operation 55MHz, rst is reset signal, cmd_pc[31..0] be the resolution command interface of host computer transmission, pci_rd_ack is the PCIMaster module has run through data line from PCI_FIFO sign, pci_rd_en is that SDRAM memory read/write module has deposited data line in the sign among the PCI_FIFO, and all the other are PCI local bus signal and PCI_FIFO control signal.

This module status transition diagram is as shown in figure 10: at first by host computer simulation PCIMaster module register is configured, transmits first address register head_reg, DMA such as interrupt register int_reg, DMA and transmit sized registers count_reg, command dma register master_reg, command register cmd_pc.Then wait for SDRAM memory read/write module deposit data line in PCI_FIFO and make pci_rd_en effectively after, initiate the DMA write operation, the data reading among the PCI_FIFO is passed to host computer by simulation PCI local bus through PEX8111.Make pci_rd_ack effective when run through data line from PCI_FIFO after, request SDRAM module is read the next line data and is deposited PCI_FIFO in from the SDRAM module, so moves in circles, until transmit frame data complete.

In the 7th step, the WDM driver is to serve for the PCI Express high-speed image sampling storage card of image acquisition.Because bridging chip has been simplified operation, make design only need the operation pci bus, and pci bus is supported plug and play, so adopt the WDM model to come driver will make driver more reasonable, supports more operating system, and convenient in installation and maintenance.Device driver is in fact to provide the many modules that can independently call for operating system, in case the user has the read-write requests of pair peripheral hardware, the I/O manager will these modules of Automatically invoked, gone with operating system by these modules more mutual, thereby finally reach user's read-write purpose.

Concrete steps are as follows:

(1) establishment equipment, most WDM device object all creates when the PnP manager calls the AddDevice entrance.This routine is called when the INF file indicates this driver to be the driver that will move with installing at the insertion new equipment.After this, a series of PnP IRP is sent to driver, and when indicating equipment should start and inquire about its function.At last, a sweep equipment PnP IRP indicating equipment is deleted, thus driver sweep equipment object, as shown in figure 11.

Behind establishment equipment, in order to make Win32 as seen, we are necessary for each equipment Create Symbol link.Can adopt two kinds of method Create Symbol links: first method is to adopt " hard coded " symbolic link name that shows, user program must similarly be encoded to implementor name in the source code.Another method is to use equipment interface, and each equipment interface is by a unique identifier sign of the overall situation.Be facility registration that a specific equipment interface has just created Symbolic Links.Subscriber equipment can be obtained the equipment that has this GUID.This driver adopts second method.The equipment interface that defines in the pcitio.INF file is: ClassGUID={ff646f80-8def-11d2-9449-00105a075f6b}.

(2) hardware resource distributes

The driver of low layer need to be known for which hardware resource they distributed.Modal hardware resource is I/O port, storage address, interruption and DMA line.The WDM driver of processing PnP IRP is apprised of the resource of equipment when receiving the PnP IRP of " starting outfit ".I/O port, storage address and interrupt resources in this driver WDM5920, have been distributed.

The 8th step, the function realization of device driver, the I/O address space of X 86 processor only has 64KB, and the address of a chip is shone upon I/O in the scope in I/O address space, and the equipment in the I/O address space can only visit by the I/O instruction.The KIoRange class realizes the access to I/O mapping chip.The accessing step of realizing port in the image acquisition Storage Card Drivers program is as follows:

(1) KIoRange class object of definition in equipment class file pcitio.h.KIoRange?m_IoPortRange0;

(2) in the device start routine of pcitioDevice.cpp file, this routine of initialization.

(3) after initially changing into merit, just can call the member function inb(of class KIoRange), outb(), inw(), outw(), ind() and outd(), realize the access to the I/O address register., among the driver pcitioDevice.cpp, to member function ind() call as follows:

PULONG?pOutBuffer=（PULONG）Mem.MapToSystemSpace（）;

PULONG?pInBuffer=（PULONG）I.IoctlBuffer（）;

m_MemoryRangeForBass0.ind（ByteOffset,pOutBuffer,count）;

In addition, can also use class KIoRange realization to the access of I/O address register, the same KIoRange of call method.

The 9th step, the overall flow that driver and application program are moved as shown in figure 12,

(1) behind system boot automatically the DriverEntry routine of load driver program be used for data structure and the resource of initialization driver scope.After the driver initialization, computer system is called driving journey AddDevice routine and is come initialisation image to gather memory card device.For it distributes hardware interrupts, map image gathers the storage card configuration space to calculator memory, and obtains the skew base address.

(2) driver enters waiting status, sends the hardware system configuration information by application program by DeviceControl.After driver obtains configuration information, by interface function out the image acquisition storage card is configured.

(3) application program creates an event, gives driver with its handle.In driver interruption delay function DpcFor_Irq (), add the statement of wake events.

(4) application program is sent data transfer instruction by DeviceControl, after driver is received, writes the DMA data transfer register of image acquisition storage card configuration space by the out function, initiates data transmission.Behind a frame data end of transmission, the image acquisition storage card produces hardware interrupts and automatically begins the next frame data transmission.Driver is had no progeny in receiving, at first determines whether the capture card hardware interrupts, then wakes application event up by the statement among the interruption delay function DpcFor_Irq (), by application program finish data read behaviour do.

(5) after data acquisition finished, application program sent halt instruction, and driver receives that rear control image acquisition storage card stops the DMA data transmission.

The tenth step, the view data that PC is processed, through the PCIE interface, SATA control module, SATA interface among the FPGA import disk array into and preserve.

Claims (6)

1. high-speed image sampling storage card based on PCI-E, it is characterized in that comprising optical fiber transmission module, the A/D modular converter, the fpga logic module, EPCS logical program memory module, JTAG program download interface, SATA hard disc data memory module, the SDRAM module, bridge chip and PCI-E interface, optical fiber transmission module is connected with the A/D modular converter, the PCI-E interface is connected with bridge chip, the A/D modular converter, EPCS logical program memory module, JTAG program download interface, SATA hard disc data memory module, the SDRAM module is connected with bridge chip with the fpga logic module and is connected, the PCI-E interface is identified by PC by the WDM driver, optical fiber transmission module advances the A/D modular converter with the image transmission that gathers, the A/D modular converter is converted into the digital signal serial input to the fpga logic module with simulating signal, in this fpga logic module, the data recombination of image will be finished, the combination of pci data structure, the generation of control signal with cooperate; EPCS logical program memory module is carried out the FPGA application configuration after integrated circuit board powers on, and finishes the initialization of fpga logic module; JTAG program download interface is FPGA program transmission channel, by this interface, can be with program Solidification to EPCS logical program memory module, SATA hard disc data memory module is finished the fpga logic module to the permanent storage of image deal with data, finish the combination of SATA data structure and control signal by this module, the SDRAM module realizes string and conversion and the storage of image data, for follow-up PCI-E data structure is prepared the transmission of data; Bridge chip will be finished pci signal that the fpga logic module transmits out to the conversion of PCI-E.

2. the high-speed image sampling storage card based on PCI-E according to claim 1, it is characterized in that the fpga logic module comprises the Arbiter arbitration modules, SDRAM memory read/write module, fpga chip, the PCIMaster module, the PCISlave module, the Arbiter arbitration modules, SDRAM memory read/write module, the signal of PCIMaster module and PCISlave module links to each other with the pin of fpga chip respectively, for guaranteeing data integrity and sequential relationship, to the AD data of gather the storage of rattling respectively, produce A and two passages of B, buffer memory advances configurable two AD_FIFO of fpga chip respectively, by the Arbiter arbitration modules data that gather is read and write control operation; SDRAM memory read/write module is data buffer storage, recombination module, it is responsible for that the AD interface module table tennis from fpga chip is write two viewdata signals the AD_FIFO and reads, deposit in the outside SDRAM module, after one frame data have stored, it takes out the view data in the SDRAM module more successively, put among the configurable PCI_FIFO of fpga chip, wait for calling of PCIMaster module; The virtual PCI of PCISlave module produces control signal from equipment by PCIMaster, cooperates PCI_FIFO, data virtual is sent to the PCISlave module, and be transferred to bridge chip by the PCISlave module; The PCIMaster module is read sampled data for function and the sequential of simulation PCI main equipment from PCI_FIFO, then initiate the DMA write operation, the data communication device that gathers is crossed Virtual PC I pass to PC from equipment through bridge chip.

3. the high-speed image sampling storage card based on PCI-E according to claim 2, the AD interface module that it is characterized in that fpga chip comprises the signal sum counter, signal is dataclk, RGB_A, hsync, vsync, cmd_pc, data_AD, call_AD_rdreq, AD_fifo_ack, ckinv, wherein dataclk is the input dot frequency, RGB_A is for changing the rear video sampled signal through AD, hsync is the line frequency signal, vsync is the field frequency signal, cmd_pc is the control signal of PC input, resolution and the refreshing frequency of the current collection image of notice AD interface module; Data_AD is the video sampling signal of output, call_AD_rdreq is zone bit, when delegation's signal data has stored set when complete in AD_FIFO, AD_fifo_ack has run through the time set of data line in SDRAM memory read/write module from AD_FIFO; Ckinv is the clock energizing signal, and concrete signal flows to and is:

(1) after PC is initiated image acquisition, the AD interface module receives the control signal Cmd_pc that transmits from PC, therefrom obtains the resolution of current collection image, refreshing frequency;

(2) wait for that the field frequency signal is effective, after the field frequency signal is effective, enter waiting status, wait for beginning to gather after the line frequency signal effectively;

(3) when the line frequency signal effectively after, open counter, to AD_FIFO storage carrier chrominance signal, count down to given resolution after, delegation's image data acquiring is complete, and all sends into AD_FIFO, stops storage, counter O reset;

(4) then notice SDRAM memory read/write module reading out data repeats top operation, until the data storage is complete.

4. the high-speed image sampling storage card based on PCI-E according to claim 2, it is characterized in that SDRAM memory read/write module comprises clock clk100, AD_data, data_RGB, call_AD_rdreq, AD_fifo_ack, cmd_pc, pci_rd_ack, pci_rd_en, ram_data, cmd, cmdack, dm, clock clk100 is 100MHz, AD_data is that the AD interface module writes the view data among the AD_FIFO, the view data of data_RGB for from the SDRAM module, reading in, call_AD_rdreq has stored complete rear set, AD_fifo_ack set the SDRAM module runs through data line from AD_FIFO after at delegation's signal data in AD_FIFO; Cmd_pc is the control signal of importing into from PC, includes current acquisition resolution, refreshing frequency; Pci_rd_ack is the PCIMaster module has run through data line from PCI_FIFO sign, pci_rd_en is for depositing data line in the sign among the PCI_FIFO, ram_data is the data of input SDRAM module, ram_addr is the SDRAM module stores address of choosing, and cmd, cmdack, dm are the control signal of SDRAM module; Concrete signal flows to:

(1) reads in the cmd_pc command signal from the PCIMaster module, determine counting of the line number that needs in the SDRAM module and every row;

(2) initialization SDRAM module configures the SDRAM module after waiting for, write the inside of SDRAM module by address wire ram_addr and deposit, and then the configuration read-write mode waits for several time-delays; After configuration is finished, the operation of reading and writing the SDRAM module.

5. the high-speed image sampling storage card based on PCI-E according to claim 2, the interface definition that it is characterized in that the PCISlave module is: clk is the frequency of operation 55Mhz of PCI, rst is reset signal, frame, irdy, cbe[3..0], trdy, devsel, stop, paren1, ad[31..0], intb, intc, intd, reqb, serr, perr, ext_add[21..0] be respectively the PCISlave module by signal, data_rd_out is PC read operation sign, data_wr is host computer write operation sign, iosel is the IO operation flag, memsel is the storage operation sign, dmasel is the dma operation sign, ext_add[21..0] be the PCIMaster register address; The PCISlave module realizes preparation input/output space register, with control DMA data transmission procedure, and the basic function of access input/output space register, the flow direction of concrete signal is:

(1) PC issues configuration signal, PCISlave module receive data order cbe[3..0], judgement order validity and order character;

(2) PCISlave inside modules state machine according to the order redirect, and read in ad[31..0] address information;

(3) PCISlave module output ext_add[21..0] low eight to the IO space address to PCISlave module mask register;

(4) the PCISlave module enables the data_rd_out signal, allows PCIMaster module accesses ad[31..0] address space;

(5) whether decision signal irdy is 0, is 0, then allows the PCIMaster module to read configuration data, writes register, and registration finishes.

6. the high-speed image sampling storage card based on PCI-E according to claim 2, the interface definition that it is characterized in that the PCIMaster module is: clk is PCI frequency of operation 55MHz, rst is reset signal, cmd_pc[31..0] be the resolution command interface of PC transmission, pci_rd_ack is the PCIMaster module has run through data line from PCI_FIFO sign, pci_rd_en is that the SDRAM module has deposited data line in the sign among the PCI_FIFO, the state transitions process of PCIMaster module is: at first by PC simulation PCI main equipment register is configured, such as interrupt register int_reg, DMA transmits first address register head_reg, DMA transmits sized registers count_reg, command dma register master_reg, command register cmd_pc; Then wait for the SDRAM module deposit data line in PCI_FIFO and make pci_rd_en effectively after, initiate the DMA write operation, data reading among the PCI_FIFO is passed to PC from equipment through bridge chip by simulation PCI, after from PCI_FIFO, running through data line, make pci_rd_ack effective, request SDRAM memory read/write module is read the next line data and is deposited PCI_FIFO in from the SDRAM module, so move in circles, until transmit frame data complete.

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