CN102931195A - Semiconductor element and manufacturing method thereof - Google Patents
Semiconductor element and manufacturing method thereof Download PDFInfo
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- CN102931195A CN102931195A CN2011102349653A CN201110234965A CN102931195A CN 102931195 A CN102931195 A CN 102931195A CN 2011102349653 A CN2011102349653 A CN 2011102349653A CN 201110234965 A CN201110234965 A CN 201110234965A CN 102931195 A CN102931195 A CN 102931195A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 230000002262 irrigation Effects 0.000 claims description 56
- 238000003973 irrigation Methods 0.000 claims description 56
- 239000003989 dielectric material Substances 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 32
- 238000005530 etching Methods 0.000 claims description 29
- 239000004020 conductor Substances 0.000 claims description 27
- 230000004888 barrier function Effects 0.000 claims description 20
- 238000000059 patterning Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- 239000007789 gas Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229910021332 silicide Inorganic materials 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- 239000010936 titanium Substances 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
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- 239000011574 phosphorus Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
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- 238000009434 installation Methods 0.000 description 1
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Abstract
The invention discloses a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a plurality of embedded-type bit lines, a plurality of bit-line contact windows, a plurality of dielectric layers and a plurality of embedded-type word lines. The embedded-type bit lines are arranged in substrates, are arranged in parallel and extend along the first direction. The bit-line contact windows are respectively arranged in the substrate on one side of the bit lines, and the embedded-type bit lines are respectively electrically connected with the substrate through the bit-line contact windows. The dielectric layers are respectively arranged on the embedded-type bit lines. The embedded-type word lines are arranged in the substrates and are positioned on the dielectric layers, are arranged in parallel and extend along the second direction different from the first direction, and a plurality of projections are arranged at the lower parts of the embedded-type word lines and are respectively positioned between two adjacent dielectric layers. By adopting the semiconductor element and the manufacturing method thereof, the on-state current can be improved, and the element efficiency can be further improved.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, and be particularly related to a kind of vertical channel transistor array and manufacture method thereof.
Background technology
Dynamic random access memory (dynamic random access memory, DRAM) belongs to a kind of volatile memory, and it is to be made of a plurality of memory cells.Each memory cell is made of capacitor of being controlled by transistor of a transistor AND gate, and each memory cell is electrically connected to each other by character line (word line, WL) and bit line (bit line, BL).
For the integration that improves dynamic random access memory (DRAM) to accelerate the service speed of element, and meeting the consumer for the demand of miniaturization electronic installation, the transistor channel section length in the dynamic random access memory (DRAM) has the trend that continues shortening.But, can make thus transistor suffer serious short-channel effect (short channel effect), and the lower degradation problem of On current (on current).
Therefore, in order to overcome the problems referred to above, industry proposes the transistor arrangement of horizontal direction is changed into the transistor arrangement of vertical direction in recent years, for instance, vertical transistor structure is formed in the deep trenches of substrate.Thus, service speed and the integration of integrated circuit can be promoted, and the problems such as short-channel effect can be avoided.Yet at present general vertical type bipolar transistor still has very large improvement space, for this reason target of field institute active research in structural design and raceway groove control.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of semiconductor element and manufacture method thereof, can promote On current, and further improve element efficiency.
The present invention proposes a kind of semiconductor element, and it comprises many embedded bit line, many contact window of bit lines, many dielectric layers and many flush type character lines.Embedded bit line is arranged in the substrate, is arranged in parallel and extends along first direction.Contact window of bit line is arranged at respectively in the substrate of a side of embedded bit line, and embedded bit line is electrically connected substrate via contact window of bit line respectively.Dielectric layer is arranged on the embedded bit line respectively.Flush type character line is arranged in the substrate and is positioned on the dielectric layer, flush type character line parallel is arranged and is extended along the second direction that is different from first direction, wherein the bottom of each flush type character line has a plurality of protuberances, and each protuberance is respectively between adjacent two dielectric layers.
The present invention proposes a kind of manufacture method of semiconductor element in addition, and it comprises the following steps.Form a plurality of the first irrigation canals and ditches in substrate, the first irrigation canals and ditches are arranged in parallel and extend along first direction.Form many embedded bit line in the bottom of the first irrigation canals and ditches.Form many contact window of bit lines in the sidewall of the first irrigation canals and ditches, contact window of bit line lays respectively at a side of embedded bit line to be electrically connected substrate.Form dielectric layer in substrate, dielectric layer covers embedded bit line and fills up the first irrigation canals and ditches.Remove part substrate and dielectric layer, to form a plurality of the second irrigation canals and ditches, the second irrigation canals and ditches are arranged in parallel and extend along the second direction that is different from first direction, and the upper surface of substrate that wherein is arranged in the second irrigation canals and ditches is lower than the dielectric layer upper surface that is arranged in the second irrigation canals and ditches.Form many flush type character lines in the second irrigation canals and ditches, the bottom of each flush type character line has a plurality of protuberances, and protuberance is formed in the substrate.
Beneficial effect of the present invention is, based on above-mentioned, semiconductor element of the present invention and manufacture method utilization thereof be formed with a plurality of protuberances in the bottom of flush type character line and so that grid groove can be more close or or even touch contact window of bit line, therefore can improve the element conductive electric current, and then improve element efficiency.In addition, the manufacturing approach craft of semiconductor element of the present invention is simple, and can be integrated in existing general technology.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate accompanying drawing to be described in detail below.
Description of drawings
Figure 1A to Fig. 1 D is the semiconductor element part perspective diagram from different perspectives according to one embodiment of the invention.
Fig. 2 A is the generalized section of A-A ' line segment in Figure 1B.
Fig. 2 B is the generalized section of B-B ' line segment in Figure 1B.
Fig. 2 C is the generalized section of C-C ' line segment in Figure 1B.
Fig. 2 D is the generalized section of D-D ' line segment in Figure 1B.
Fig. 3 A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A and Fig. 8 A illustrate into according among Figure 1B along the manufacturing process generalized section of A-A ' line segment.
Fig. 3 B, Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B and Fig. 8 B illustrate into according among Figure 1B along the manufacturing process generalized section of B-B ' line segment.
Fig. 3 C, Fig. 4 C, Fig. 5 C, Fig. 6 C, Fig. 7 C and Fig. 8 C illustrate into according among Figure 1B along the manufacturing process generalized section of C-C ' line segment.
Fig. 3 D, Fig. 4 D, Fig. 5 D, Fig. 6 D, Fig. 7 D and Fig. 8 D illustrate into according among Figure 1B along the manufacturing process generalized section of D-D ' line segment.
Fig. 9 A and Fig. 9 B illustrate the part perspective diagram of different angles after forming the second irrigation canals and ditches.
Wherein, description of reference numerals is as follows:
100,300: substrate
100a, 300a: semiconductor column
102,306: embedded bit line
102a, 108a, 306a, 320a: conductor layer
102b, 108b, 306b, 320b: barrier layer
104,308: contact window of bit line
104a, 308a: metal silicide layer
104b, 308b: doped polysilicon layer
104c, 308c: doped region
106,110,310,312: dielectric layer
107,314: lining
108,320: flush type character line
112,322: protuberance
114a, 324a: the first wire
114b, 324b: the second wire
114c, 324c: connecting portion
302,316: patterned mask layer
304: the first irrigation canals and ditches
312a: the first dielectric material
312b: the second dielectric material
312c: the 3rd dielectric material
318: the second irrigation canals and ditches
318a: groove
D1: first direction
D2: second direction
Embodiment
Semiconductor element proposed by the invention for example is a kind of transistor array with vertical-channel, and can be used for dynamic random access memory.Hereinafter will describe embodiments of the invention in detail in the arrange in pairs or groups mode of profile of perspective view.
Figure 1A to Fig. 1 D is the semiconductor element part perspective diagram from different perspectives according to one embodiment of the invention.Fig. 2 A is the generalized section of A-A ' line segment in Figure 1B.Fig. 2 B is the generalized section of B-B ' line segment in Figure 1B.Fig. 2 C is the generalized section of C-C ' line segment in Figure 1B.Fig. 2 D is the generalized section of D-D ' line segment in Figure 1B.It is noted that, for simplifying accompanying drawing, only show the main members such as embedded bit line, contact window of bit line, flush type character line, part dielectric layer among Figure 1A to Fig. 1 D.
Please refer to Figure 1A to Fig. 1 D and Fig. 2 A to Fig. 2 D, the semiconductor element that is arranged in the substrate 100 comprises many embedded bit line 102, many contact window of bit lines 104, many dielectric layers 106 and many flush type character lines 108.Substrate 100 for example is silicon base or other semiconductor bases.In one embodiment, the top of substrate 100 can have a plurality of semiconductor column 100a, and wherein semiconductor column 100a for example is separated from one another and is arranged in array, with the active region as vertical-channel transistors.
Embedded bit line 102 is arranged in the substrate 100, and embedded bit line 102 is arranged in parallel and extend along first direction D1.In one embodiment, also comprise one dielectric layer 110 between embedded bit line 102 and the substrate 100, with isolated part embedded bit line 102 and substrate 100.Particularly, embedded bit line 102 comprises conductor layer 102a and barrier layer 102b, and wherein barrier layer 102b is arranged between conductor layer 102a and the dielectric layer 110.The material of conductor layer 102a comprises metal material, such as tungsten, copper, aluminium, albronze etc.The material of barrier layer 102b for example is titanium nitride (TiN) or titanium (Ti).The material of dielectric layer 110 for example is silica.
Contact window of bit line 104 is arranged at respectively in the substrate 100 of a side of embedded bit line 102.In one embodiment, contact window of bit line 104 comprises metal silicide layer 104a, doped polysilicon layer 104b and doped region 104c, wherein metal silicide layer 104a is disposed between doped polysilicon layer 104b and the barrier layer 102b, and doped polysilicon layer 104b is disposed between metal silicide layer 104a and the doped region 104c.Metal silicide layer 104a directly contacts with barrier layer 102b, thereby so that embedded bit line 102 can be electrically connected substrate 100 via contact window of bit line 104 respectively.The material of metal silicide layer 104a for example is titanium silicide.Doped polysilicon layer 104b and doped region 104c are such as being to be doped with the admixtures such as arsenic (As) or phosphorus (P).
Flush type character line 108 is arranged in the substrate 100 and is positioned on the dielectric layer 106.Flush type character line 108 is arranged in parallel and extends along the second direction D2 that is different from first direction D1.Flush type character line 108 for example is to be made of conductor layer 108a and barrier layer 108b.The material of conductor layer 108a comprises metal material, such as tungsten, copper, aluminium or albronze etc., and the material of barrier layer 108b for example is titanium nitride (TiN) or titanium (Ti).
The bottom of each flush type character line 108 has a plurality of protuberances 112, and each protuberance 112 lays respectively between adjacent two dielectric layers 106.In one embodiment, flush type character line 108 and contact window of bit line 104 are the closer to better, and wherein the protuberance 112 of flush type character line 108 for example is the doped region 104c that directly touches contact window of bit line 104.For example, the bottom profile of flush type character line 108 can have difference of height.Be positioned at flush type character line 108 and embedded bit line 102 staggered places, can be provided with dielectric layer 106 between flush type character line 108 and the embedded bit line 102 and both are isolated mutually, so flush type character line 108 is higher in herein bottom profile.On the other hand, above between the adjacent embedded bit line 102, locate, the protuberance 112 of flush type character line 108 for example is directly to contact with the contact window of bit line 104 that is positioned at embedded bit line 102 1 sides, so flush type character line 108 is lower in herein bottom profile.
In addition, every flush type character line 108 is made of first a wire 114a, second a wire 114b and a plurality of connecting portion 114c.The first wire 114a and the second wire 114b extend along second direction D2 respectively, and connecting portion 114c lays respectively on the dielectric layer 106 and connects the first adjacent wire 114a and the second wire 114b.Particularly, adjacent the first wire 114a and the second wire 114b that are connected by connecting portion 114c can connect same row's semiconductor column 100a at second direction D2, and adhere to the adjacent first wire 114a of two different flush type character lines 108 separately and second wire 114b is separated from one another does not contact mutually.In each flush type character line 108, the first wire 114a connects the side of the upper same row's of second direction D2 semiconductor column 100a, and the corresponding relative another side that connects the upper same row's of second direction D2 semiconductor column 100a of the second wire 114b.Hold above-mentionedly, each flush type character line 108 has a plurality of protuberances 112 between adjacent two dielectric layers 106, and so protuberance 112 for example is to be positioned at accordingly respectively the bottom of the first wire 114a and the bottom of the second wire 114b.
In this explanation be, the both sides of adopting the first wire 114a and the second wire 114b to be coated on the upper same row's of second direction D2 semiconductor column 100a owing to every flush type character line 108 form double gate (double gate) structure of fin-shaped (fin), thereby so that all can respond to the electric field that grid causes as the two side of same row's semiconductor column 100a of active region, and the On current of the element that is increased (on current), and reduce the problem of leakage current in the raceway groove.In addition, be provided with a plurality of protuberances 112 and form similar H shape grid (shown in Fig. 2 A) at cross section view by the bottom at flush type character line 108, therefore so that grid groove can be more close or or even touch the doped region 104c of contact window of bit line 104, can help more to improve the element conductive electric current, and then effectively improve element efficiency in isolation embedded bit line 102 and the flush type character line 108.
Next will utilize the generalized section of A-A ', B-B ' along Figure 1B, C-C ', D-D ' line segment to be illustrated the manufacturing process that forms the semiconductor element shown in above-mentioned Figure 1A to Fig. 1 D, Fig. 2 A to Fig. 2 D.It is noted that, the manufacturing process of the semiconductor element of the following stated mainly is the formation method that the flush type character line with protuberance is described, so that those skilled in the art can implement according to this, but be not to limit scope of the present invention, generation type and order as for other members such as embedded bit line, contact window of bit line, dielectric layer, lining etc., all can be according to the fabrication techniques known to the technical staff in the technical field, and it is described to be not limited to following embodiment.
Fig. 3 A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A and Fig. 8 A illustrate into according among Figure 1B along the manufacturing process generalized section of A-A ' line segment.Fig. 3 B, Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B and Fig. 8 B illustrate into according among Figure 1B along the manufacturing process generalized section of B-B ' line segment.Fig. 3 C, Fig. 4 C, Fig. 5 C, Fig. 6 C, Fig. 7 C and Fig. 8 C illustrate into according among Figure 1B along the manufacturing process generalized section of C-C ' line segment.Fig. 3 D, Fig. 4 D, Fig. 5 D, Fig. 6 D, Fig. 7 D and Fig. 8 D illustrate into according among Figure 1B along the manufacturing process generalized section of D-D ' line segment.
Please refer to Fig. 3 A to Fig. 3 D, substrate 300 is provided, it for example is silicon base or other semiconductor bases.Then, in substrate 300, form patterned mask layer 302.The material of patterned mask layer 302 for example is silicon nitride, and its formation method for example is chemical vapour deposition technique.Then, remove part substrate 300 take patterned mask layer 302 as mask, to form a plurality of the first irrigation canals and ditches 304 in substrate 300, wherein a plurality of the first irrigation canals and ditches 304 are arranged in parallel and extend along first direction D1.
Please refer to Fig. 4 A to Fig. 4 D, form many embedded bit line 306 in the bottom of the first irrigation canals and ditches 304, and form many contact window of bit lines 308 in the sidewall of the first irrigation canals and ditches 304, contact window of bit line 308 lays respectively at a side of embedded bit line 306 to be electrically connected substrate 300.Embedded bit line 306 comprises conductor layer 306a and barrier layer 306b, and wherein barrier layer 306b is arranged between conductor layer 306a and the dielectric layer 310.In one embodiment, contact window of bit line 308 comprises metal silicide layer 308a, doped polysilicon layer 308b and doped region 308c, and wherein doped polysilicon layer 308b is disposed between metal silicide layer 308a and the doped region 308c.
Particularly, contact window of bit line 308 and embedded bit line 306 can be utilized following step and form, but the present invention is not limited to this.At first, on the lower sides of the first irrigation canals and ditches 304 and bottom, form one dielectric layer 310.The material of dielectric layer 310 for example is silica, and its formation method for example is thermal oxidation method.Then, on the sidewall of wherein one side of the first irrigation canals and ditches 304 bottoms that dielectric layer 310 exposes, form the doped polysilicon layer 308b that is doped with arsenic (As) or phosphorus (P), utilize thereupon thermal process make arsenic (As) among the doped polysilicon layer 308b or phosphorus (P) dopant diffusion to substrate 100 that doped polysilicon layer 308b contact in, thereby in the wherein doped region 308c of formation contact window of bit line 308 in the sidewall on one side of the first irrigation canals and ditches 304 bottoms.Afterwards, compliance ground forms barrier layer 306b on dielectric layer 310, and barrier layer 306b covers on the doped polysilicon layer 308b.Barrier layer 306b for example is titanium nitride (TiN) or titanium (Ti), and wherein the titanium (Ti) among the barrier layer 306b can produce reaction and form metal silicide 308a with doped polysilicon layer 308b.Then, insert conductor layer 306a in the bottom of the first irrigation canals and ditches 304, wherein conductor layer 306a covers barrier layer 306b, thereby finishes the structure of contact window of bit line 308 and embedded bit line 306.The material of conductor layer 306a comprises metal material, such as tungsten, copper, aluminium or albronze etc.
Please refer to Fig. 5 A to Fig. 5 D, form dielectric layer 312 in substrate 300, dielectric layer 312 covers embedded bit line 306 and fills up the first irrigation canals and ditches 304.In one embodiment, dielectric layer 312 for example is multilayer dielectric layer, it comprises the first dielectric material 312a and the second dielectric material 312b with different etching selectivities at least, and the first dielectric material 312a is arranged between embedded bit line 306 and the second dielectric material 312b.The first dielectric material 312a utilizes the formed silica of high-density plasma (HDP oxide), and the second dielectric material 312b utilizes the formed silica of spin-coating method (SOD oxide).In addition, dielectric layer 312 also can comprise the 3rd dielectric material 312c that has different etching selectivities from the second dielectric material 312b.The 3rd dielectric material 312c covers on the second dielectric material 312b and the patterned mask layer 302, so that the second dielectric material 312b is sandwiched between the first dielectric material 312a and the 3rd dielectric material 312c.The 3rd dielectric material 312c that has different etching selectivities from the second dielectric material 312b can be the material that is same as the first dielectric material 312a, as utilizes the formed silica of high-density plasma (HDP oxide).
In one embodiment, before forming dielectric layer 312, can also be optionally in embedded bit line 306 tops and the sidewall of the first irrigation canals and ditches 304 form lining 314, lining 314 for example be compliance be formed between dielectric layer 312 and the substrate 300 and be formed between dielectric layer 312 and the embedded bit line 306.The material of lining 314 for example is silicon nitride, and its formation method for example is chemical vapour deposition technique.
Please refer to Fig. 6 A to Fig. 6 D, in substrate 300, form another layer pattern mask layer 316.The material of patterned mask layer 316 for example is carborundum, and its formation method for example is chemical vapour deposition technique.Then, remove part substrate 300, dielectric layer 312, lining 314 and patterned mask layer 302 take patterned mask layer 316 as mask, to form a plurality of the second irrigation canals and ditches 318.A plurality of the second irrigation canals and ditches 318 are parallel in the substrate 300, and extend along the second direction D2 that is different from first direction D1.The second irrigation canals and ditches 318 for example are the tops that is positioned at embedded bit line 306, and with embedded bit line 306 at a distance of a distance.In one embodiment, the second irrigation canals and ditches 318 and the first irrigation canals and ditches 304 are divided into the top of substrate 300 the semiconductor column 300a of a plurality of separation and arrayed jointly.
What specify is that Fig. 9 A and Fig. 9 B illustrate the part perspective diagram of different angles after forming the second irrigation canals and ditches, and for simplifying accompanying drawing to clearly demonstrate, have omitted patterned mask layer 316 among Fig. 9 A and Fig. 9 B.Shown in Fig. 9 A and Fig. 9 B, in the second irrigation canals and ditches 318, the upper surface of the substrate 300 that is exposed out can be lower than the upper surface of dielectric layer 312, thereby forms a plurality of groove 318a in the bottom of each the second irrigation canals and ditches 318.Particularly, a plurality of the second irrigation canals and ditches 318 for example are take patterned mask layer 316 as mask and the dry etch process of carrying out multi-step forms.
In one embodiment, after forming patterned mask layer 316, carry out the first etching step to remove partially patterned mask layer 302, dielectric layer 312 and lining 314 and expose part substrate 300, then carry out the second etching step and remove the part substrate 300 that exposes until the required degree of depth, carry out afterwards the 3rd etching step and remove the part dielectric layer 312 that exposes, and finish the making of the second irrigation canals and ditches 318.Because substrate 300 has different etching selectivities from dielectric layer 312, therefore the second etching step only can remove a small amount of dielectric layer 312, and the 3rd etching step only can remove a small amount of substrate 300.Thus, can by the process conditions of control the second etching step and the 3rd etching step, have different upper level so that be positioned at substrate 300 and the dielectric layer 312 of the second irrigation canals and ditches 318.
On the practice, above-mentioned second etching step that carries out removes the part substrate 300 that exposes and can use CHF
3, HBr, Cl
2And SF
6As reacting gas, CHF wherein
3Gas flow for example be 90sccm to 120sccm, the gas flow of HBr for example is 20sccm to 45sccm, Cl
2Gas flow for example be 20sccm to 45sccm, SF
6Gas flow for example be 8sccm to 13sccm.Carrying out the second etching step, to remove the part substrate 300 that exposes for example be to carry out under the pressure of about 10mTorr to 30mTorr, and for example be to apply approximately 1000W to 1500W and apply approximately 60W to 90W of rf bias at electric pole plate in order to radio frequency (radio frequency, the RF) power that produces plasma in the etching step.Carrying out the time that the second etching step removes the part substrate 300 that exposes for example is 20 seconds to 30 seconds.
On the other hand, above-mentioned the 3rd etching step that carries out removes the part dielectric layer 312 that exposes and can use CHF
3As reacting gas, CHF wherein
3Gas flow for example be 300sccm to 500sccm.It for example is to carry out under the pressure of about 10mTorr to 30mTorr that the 3rd etching step removes the part dielectric layer 312 that exposes, and for example is to apply approximately 200W to 500W and apply approximately 550W to 800W of rf bias at electric pole plate in order to the radio-frequency power supply power that produces plasma in the etching step.Carrying out the time that the 3rd etching step removes the part dielectric layer 312 that exposes for example is 35 seconds to 45 seconds.In addition, in the second etching step and the 3rd etching step, also can further add such as the usefulness of the inert gases such as argon gas (Ar) or helium (He) as diluent gas and carrier gas when passing into reacting gas.
It is worth mentioning that, although be in the above-described embodiments carry out first the second etching step remove part substrate 300 carry out again the 3rd etching step remove part dielectric layer 312 make the bottom have a plurality of groove 318a the second irrigation canals and ditches 318 for example describes, the present invention is not limited to this.In another embodiment, carrying out the first etching step to remove partially patterned mask layer 302, dielectric layer 312 and lining 314 after exposing part substrate 300, also can be to carry out first the 3rd etching step to remove the part dielectric layer 312 that exposes until the required degree of depth, just carry out afterwards the second etching step and remove the part substrate 300 that exposes to form the second irrigation canals and ditches 318, in these those skilled in the art when knowing its variation according to previous embodiment, therefore repeat no more in this.
Please refer to Fig. 7 A to Fig. 7 D, remove the second dielectric material 312b, thereby between the first dielectric material 312a and the 3rd dielectric material 312c, form opening, so that can be interconnected between the second adjacent irrigation canals and ditches 318.The method that removes the second dielectric material 312b for example is to carry out wet etching, and the hydrofluoric acid (dilute hydrofluoric acid, DHF) that can utilize dilution is as etching solution.Afterwards, in substrate, form conductor layer 320a, conductor layer 320a insert in the second irrigation canals and ditches 318 and be formed at the first dielectric material 312a and the 3rd dielectric material 312c between opening (former the second dielectric material 312b place) in.Because the bottom of the second irrigation canals and ditches 318 has a plurality of groove 318a, so conductor layer 320a can insert in the groove 318a, and forms a plurality of protuberances 322 in the bottom of conductor layer 320a.Protuberance 322 for example be with contact window of bit line 308 the closer to better, so protuberance 322 is preferably the doped region 308c that directly touches contact window of bit line 308.Before forming conductor layer 320a, also optionally in formation barrier layer 320b between conductor layer 320a and the substrate 300, between conductor layer 320a and the dielectric material.Thus, conductor layer 320a and barrier layer 320b can be used as the material of the predetermined character line that forms of subsequent step.
Please refer to Fig. 8 A to Fig. 8 D, patterning conductor layer 320a and barrier layer 320b, to form respectively first a wire 324a and second wire 324b who extends along second direction D2 in each second irrigation canals and ditches 318, wherein conductor layer 320a and the barrier layer 320b in the opening between the first dielectric material 312a and the 3rd dielectric material 312c (former the second dielectric material 312b place) then forms a plurality of connecting portion 324c.A plurality of connecting portion 324c connect the first wire 324a and the second wire 324b that lays respectively in adjacent two second irrigation canals and ditches 318, thereby consist of a flush type character line 320, and finish the structure of the semiconductor element shown in Figure 1A to Fig. 1 D.Comprise in formation after the semiconductor element of the members such as embedded bit line 306, contact window of bit line 308, flush type character line 320, the making that also can continue to form capacitor above it and finish memory, know those skilled in the art as can be known its application and variation, therefore repeat no more in this.
Hold above-mentioned, adjacent the first wire 324a that is connected by a plurality of connecting portion 324c and the second wire 324b can connect same row's semiconductor column 300a at second direction D2, and adhere to the adjacent first wire 324a of two different flush type character lines 320 separately and second wire 324b is separated from one another does not contact mutually.The first wire 324a in every flush type character line 320 and the second wire 324b can be coated on the upper same row of second direction D2 semiconductor column 300a relative both sides and form the double gate structure of fin-shaped, can help to make the two side of same row's semiconductor column 300a all can sense electric field, and increase the On current of element and reduce the problem of leakage current in the raceway groove.Moreover, because the protuberance 322 of conductor layer 320a can be inserted in the groove 318a of the second irrigation canals and ditches 318 bottoms, therefore the first wire 324a in every flush type character line 320 and the second wire 324b are can be by protuberance 322 more close or even touch the doped region 308c of contact window of bit line 308, therefore can improve the element conductive electric current, and then improve element efficiency.
In sum, semiconductor element of the present invention and manufacture method thereof have following advantages at least:
1. the flush type character line of the semiconductor element of above-described embodiment has protuberance, can help to make grid groove can more close even directly touch the doped region of contact window of bit line, therefore can increase the On current of element, and then effectively improve element efficiency in isolation embedded bit line and the flush type character line.
2. the manufacture method of the semiconductor element of above-described embodiment utilizes substrate and dielectric layer to have different etching selectivities, and the change that only need see through etch process conditions can form in the bottom of flush type character line protuberance, so technique is simple and can be integrated in existing technique, and can significantly promote the element efficiency of follow-up formation.
Although the present invention discloses as above with embodiment; so it is not to limit the present invention; any the technical staff in the technical field; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (10)
1. semiconductor element comprises:
Many embedded bit line are arranged in the substrate, and described many embedded bit line are arranged in parallel and extend along a first direction;
Many contact window of bit lines are arranged at respectively in this substrate of a side of described many embedded bit line, and described many embedded bit line are electrically connected this substrate via described many contact window of bit lines respectively;
Many dielectric layers are arranged at respectively on described many embedded bit line; And
Many flush type character lines, be arranged in this substrate and be positioned on this dielectric layer, described many flush type character line parallels are arranged and are extended along a second direction that is different from this first direction, wherein the bottom of each described many flush type character line has a plurality of protuberances, and each described a plurality of protuberance is respectively between adjacent two dielectric layers.
2. semiconductor element as claimed in claim 1 is characterized in that, described many flush type character lines directly contact described many contact window of bit lines.
3. semiconductor element as claimed in claim 1 is characterized in that, each described flush type character line comprises:
One first wire and one second wire extend along this second direction respectively; And
A plurality of connecting portions are positioned on described many dielectric layers and connect this adjacent first wire and this second wire.
4. semiconductor element as claimed in claim 1 is characterized in that, each described flush type character line comprises a barrier layer and a conductor layer.
5. semiconductor element as claimed in claim 1 is characterized in that, described contact window of bit line comprises doped region.
6. the manufacture method of a semiconductor element comprises:
Form a plurality of the first irrigation canals and ditches in a substrate, described a plurality of the first irrigation canals and ditches are arranged in parallel and extend along a first direction;
Form many embedded bit line in the bottom of described a plurality of the first irrigation canals and ditches;
Form many contact window of bit lines in the sidewall of described a plurality of the first irrigation canals and ditches, described many contact window of bit lines lay respectively at a side of described many embedded bit line to be electrically connected this substrate;
Form a dielectric layer in this substrate, this dielectric layer covers described many embedded bit line and fills up described a plurality of the first irrigation canals and ditches;
Remove this substrate of part and this dielectric layer, to form a plurality of the second irrigation canals and ditches, described a plurality of the second irrigation canals and ditches are arranged in parallel and extend along a second direction that is different from this first direction, and this upper surface of substrate that wherein is arranged in described a plurality of the second irrigation canals and ditches is lower than this dielectric layer upper surface that is arranged in described a plurality of the second irrigation canals and ditches; And
Form many flush type character lines in described a plurality of the second irrigation canals and ditches, the bottom of each described many flush type character line has a plurality of protuberances, and described a plurality of protuberances are formed in this substrate.
7. the manufacture method of semiconductor element as claimed in claim 6 is characterized in that, described many flush type character lines directly contact described many contact window of bit lines.
8. the manufacture method of semiconductor element as claimed in claim 6, it is characterized in that, this dielectric layer between adjacent described a plurality of the second irrigation canals and ditches is multilayer dielectric layer, it comprises one first dielectric material and one second dielectric material with different etching selectivities, and this first dielectric material is arranged between described many embedded bit line and this second dielectric material.
9. the manufacture method of semiconductor element as claimed in claim 8 is characterized in that, the manufacture method of described many flush type character lines comprises:
Remove this second dielectric material;
Form a conductor layer in this substrate, this conductor layer is inserted in described a plurality of the second irrigation canals and ditches and is formed on this first dielectric material; And
This conductor layer of patterning, in each described a plurality of second irrigation canals and ditches, to form respectively one first wire and one second wire that extends along this second direction, this conductor layer that wherein is positioned on this first dielectric material forms a plurality of connecting portions, lays respectively at this first wire and this second wire in adjacent two second irrigation canals and ditches with connection.
10. the manufacture method of semiconductor element as claimed in claim 6 is characterized in that, described contact window of bit line comprises doped region.
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| CN110299324A (en) * | 2018-03-22 | 2019-10-01 | 长鑫存储技术有限公司 | The transistor arrangement and its manufacturing method of semiconductor memory |
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| CN1819205A (en) * | 2004-11-30 | 2006-08-16 | 因芬尼昂技术股份公司 | Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array |
| US20080246067A1 (en) * | 2005-03-05 | 2008-10-09 | Hong-Sik Yoon | Dram device and method of manufacturing the same |
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| CN1819205A (en) * | 2004-11-30 | 2006-08-16 | 因芬尼昂技术股份公司 | Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array |
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