CN102931127A - Method for forming isolation structure of anti-radiation hardening shallow groove - Google Patents
Method for forming isolation structure of anti-radiation hardening shallow groove Download PDFInfo
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- CN102931127A CN102931127A CN2012103819063A CN201210381906A CN102931127A CN 102931127 A CN102931127 A CN 102931127A CN 2012103819063 A CN2012103819063 A CN 2012103819063A CN 201210381906 A CN201210381906 A CN 201210381906A CN 102931127 A CN102931127 A CN 102931127A
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Abstract
The invention aims to provide a method for forming an isolation structure of an anti-radiation hardening shallow groove. The method comprises the following steps of: forming a groove on a semiconductor substrate by etching; depositing a sacrifice layer with certain thickness in the groove; etching to remove the sacrifice layer at the bottom of the groove; depositing and filling silica in the groove; selectively removing the sacrifice layer by wet etching; and forming an air gap layer. The invention provides the method for forming the isolation structure of the anti-radiation hardening shallow groove, which reduces the manufacturing cost, improves the reliability of devices and circuits and solves the problem of increased leakage current caused by radiation.
Description
Technical field
The present invention relates to a kind of formation method of shallow groove isolation structure, particularly relate to a kind of radiation hardening shallow groove isolation structure formation method with air gap.
Background technology
Along with the progress of semi-conductor industry, integrated circuit is towards more microsize and faster arithmetic speed development.When the size of integrated circuit increasingly when the microminiaturization, how effectively to carry out the isolation of element, be the important key of integrated circuit development.Component isolation structure generally is to prevent that movably charge carrier flow to peripheral element from a semiconductor element via substrate.General component isolation structure is to utilize regional oxidation (LOCOS) technology of silicon to form the thick silicon oxide layer that one deck extends at semiconductor base, to obtain low-cost and high stability component isolation structure.Yet the isolation structure that forms in the LOCOS mode can cause many problems, comprises issuable internal stress, causes beak erosion etc. around field oxide.Particularly, when element dwindles, the beak erosion areas will relatively become greatly so that the LOCOS structure generation bottleneck on the size.
Therefore the insulation system between the shallow-trench isolation fabrication techniques active area is generally adopted gradually at present.Traditional shallow-trench isolation (Shallow Trench Isolation:STI) structure forms normally first deposit one deck silicon nitride layer on semiconductor base, and then this silicon nitride layer of patterning forms hard mask.Then etching substrate forms groove between adjacent element.At last, in groove, insert oxide forming element isolation structure.The shallow-trench isolation technology has solved the variety of issue that the LOCOS technology occurs, and has better played buffer action.
But for current shallow groove isolation structure, still there are many problems in the design of its groove side wall and adjacent area joint.When the shallow-trench isolation technology was applied to active picture element image sensor, because the height of light-sensitive device is integrated now, the size of photodiode was also constantly reducing in the cmos image sensor, so that the distance of photodiode and groove side wall furthers.This will produce series of problems, as crosstalks, dark current etc.And, adopt shallow-trench isolation, when being subject to radiation, not only can in the groove inner oxide layer, produce the oxide trap positive charge, but also can be at the Si/SiO of groove side wall
2The surface produces a large amount of interface trapped charges, and can be along Si/SiO
2The surface forms the delivering path of a leakage current, so that Leakage Current increases, the Leakage Current of this part equally also is the main source of the whole Leakage Current of device.In addition, adopt shallow-trench isolation, equally can be because the radiation induced charge causes parasitic channel to be produced, so that the leakage current of MOSFET device increases.Above these problems all can reduce the isolation characteristic of STI, thereby can reduce the reliability of device and circuit.
Patent (US20110186918A1) discloses a kind of shallow groove isolation structure with air gap, and the shallow groove isolation structure of carrying is to be applied to cmos image sensor.It is that shallow-trench isolation side wall by etching and photodiode joint one side forms air gap layer, can suppress crosstalking and dark current between the cmos image sensor pixel.But in the forming process of air gap structure, when forming one-sided air gap by etching shallow slot side wall, need the accurate etching of aiming at, this is difficult to realize in actual process so that technology difficulty is larger.When forming the bilateral air gap layer if make better isolation between pixel, difficulty is higher.And in the process that forms air gap layer, owing to wanting the deposit multilayer dielectricity so that technique is loaded down with trivial details, technique controlling difficulty is large.In addition, because a structure of carrying has very large application limitation for cmos image sensor.
Summary of the invention
The object of the present invention is to provide a kind of reduction manufacturing cost, improve device and circuit reliability, solved because Leakage Current that radiation causes increases a kind of radiation hardening shallow groove isolation structure formation method of problem.
The object of the present invention is achieved like this:
Radiation hardening shallow groove isolation structure formation method may further comprise the steps:
Step 3, sti trench groove 2 with sacrifice layer 4 and the surface of Semiconductor substrate 1 are carried out photoengraving, remove the sacrifice layer 4 on sti trench groove 2 bottoms and Semiconductor substrate 1 surface, expose bottom Semiconductor substrate 1;
Step 4, carry out the shallow trench oxidation layer and fill deposit, method deposit silicon dioxide in sti trench groove 2 by low-pressure chemical vapor phase deposition makes its covering groove, forms shallow trench oxidation layer packed layer 6, remove unnecessary silicon dioxide with chemico-mechanical polishing again, obtain smooth surface;
Described Semiconductor substrate (1) material is silicon, germanium, III ~ V group iii v compound semiconductor material, II ~ VI group iii v compound semiconductor material or monocrystal material.
Described monocrystal material can make it become N-shaped substrate or p-type substrate by doping.
The invention has the advantages that:
This shallow groove isolation structure with air gap of the present invention, not only has good buffer action, can effectively suppress dark current and crosstalk, and when being subject to radiation, because the air gap that forms on the Si/SiO2 surface of groove side wall not only can suppress the generation of Si/SiO2 surface interface trapped charge, and can cut off the delivering path of leakage current, solved because the problem that leakage current that radiation causes increases, improve the reliability of device and circuit, realized good radiation resistance.Technique for shallow groove isolation structure Air gap portion forms, and the present invention is by the certain thickness sacrifice layer of deposit in groove, and obtains air gap layer by wet etching removal groove side wall sacrifice layer.Do not form air gap layer by dry etching, because because air gap layer is very thin, need to aim at very accurately when dry etching, technology difficulty is larger, is not easy to realize.And adopt the method for wet etching to form air gap layer, and reduced technology difficulty, more easily realize, and the use of in processing step is implemented, having omitted mask plate, also so that work simplification.Improve simultaneously rate of finished products, reduced manufacturing cost.In the process that forms air gap layer, too much do not use protective layer, so that technique is simply controlled, more easily realize, and the scope of application of the present invention is larger, can be widely used in the CMOS technology.
Description of drawings
Fig. 1 is the schematic diagram of bottom Si substrate before the etching;
Fig. 2 is formed sti trench groove schematic diagram after Fig. 1 structure etching;
Fig. 3 is the schematic diagram behind the structure deposit sacrifice layer shown in Figure 2;
Fig. 4 is that structure shown in Figure 3 is through removing the schematic diagram of channel bottom and substrate surface sacrifice layer behind the photoengraving;
Fig. 5 is that specific embodiment one carries out shallow trench oxidation layer filling deposit SiO in structure shown in Figure 4
2After schematic diagram;
The schematic diagram of Fig. 6 to be specific embodiment one form after removing groove side wall sacrifice layer by corrosive agent on the structure shown in Figure 5 air gap;
Fig. 7 is the schematic diagram of specific embodiment two after structure shown in Figure 4 is carried out deep layer P type Implantation;
Fig. 8 is that specific embodiment two carries out shallow trench oxidation layer filling deposit SiO in structure shown in Figure 7
2After schematic diagram;
The schematic diagram of Fig. 9 to be specific embodiment two form after removing groove side wall sacrifice layer by corrosive agent on the structure shown in Figure 8 air gap.
Embodiment
Below in conjunction with accompanying drawing the present invention is done more detailed description:
Specific embodiment one:
In conjunction with Fig. 1.Be bottom Semiconductor substrate 1, its material can freely be selected, such as: silicon, germanium, III ~ V group iii v compound semiconductor material, II ~ VI group iii v compound semiconductor material or other compound semiconductor materials etc., also can adopt monocrystal material, also can make it become N-shaped substrate or p-type substrate by doping for monocrystal material.For this Semiconductor substrate 1, material is elected silicon materials as.
In conjunction with Fig. 2.Bottom Semiconductor substrate (1) is carried out etching, and the formation degree of depth is 300 ~ 450nm, and width is the sti trench groove 2 of 150nm.
In conjunction with Fig. 3.For structure shown in Figure 2, method growth thickness on the first horizontal substrate surface a, the second horizontal substrate surperficial b, sti trench groove 2 bottom level substrate surface c and sti trench groove 2 side wall surfaces 3 by low-pressure chemical vapor phase deposition (CVD) is the sacrifice layer 4 of 15 ~ 20nm, material can be elected sacrificial layer material commonly used as, such as SiGe, polyimides etc.
In conjunction with Fig. 4.For structure shown in Figure 3, utilize the method for photoengraving that sacrifice layer 4 is carried out etching, remove the sacrifice layer 4 on the first horizontal substrate surface a, the second horizontal substrate surface b and the sti trench groove 2 bottom level substrate surface c, forming width is the sti trench groove 2 side wall sacrifice layers 5 of 15 ~ 20nm.
In conjunction with Fig. 5.Structure shown in Figure 4 is carried out the shallow trench oxidation layer fill deposit, by method deposit silicon dioxide (SiO in sti trench groove 2 of low-pressure chemical vapor phase deposition (CVD)
2), make it cover whole sti trench groove 2, form shallow trench oxidation layer packed layer 6, use again chemico-mechanical polishing (CMP) to remove unnecessary silicon dioxide, thereby obtain smooth surface.
In conjunction with Fig. 6.Utilize corrosive agent that sti trench groove 2 side wall sacrifice layers 5 are carried out wet etching, remove sti trench groove 2 both sides side wall sacrifice layers 5, forming thickness is the air gap layer 7 of 15 ~ 20nm.
Specific embodiment two:
In conjunction with Fig. 1.Be bottom Semiconductor substrate 1, its material can freely be selected, such as: silicon, germanium, III ~ V group iii v compound semiconductor material, II ~ VI group iii v compound semiconductor material or other compound semiconductor materials etc., also can adopt monocrystal material, also can make it become N-shaped substrate or p-type substrate by doping for monocrystal material.For this Semiconductor substrate 1, material is elected silicon materials as.
In conjunction with Fig. 2.Bottom Semiconductor substrate 1 is carried out etching, and the formation degree of depth is 300 ~ 450nm, and width is the sti trench groove 2 of 150nm.
In conjunction with Fig. 3.For structure shown in Figure 2, method growth thickness on the first horizontal substrate surface a, the second horizontal substrate surperficial b, sti trench groove 2 bottom level substrate surface c and sti trench groove 2 side wall surfaces 3 by low-pressure chemical vapor phase deposition (CVD) is the sacrifice layer 4 of 15 ~ 20nm, its material can be elected sacrificial layer material commonly used as, such as SiGe, polyimides etc.
In conjunction with Fig. 4.For structure shown in Figure 3, utilize the method for photoengraving that sacrifice layer 4 is carried out etching, remove sacrifice layer, the sacrifice layer on the b of the second horizontal substrate surface and the sacrifice layer 4 on the sti trench groove 2 bottom level substrate surface c on a of the first horizontal substrate surface, forming width is the sti trench groove 2 side wall sacrifice layers 5 of 15 ~ 20nm.
In conjunction with Fig. 7.For structure shown in Figure 4, resist coating on a of the first horizontal substrate surface, and on the b of the second horizontal substrate surface resist coating; form photoresist protective layer 8; then sti trench groove 2 bottom level substrate surface c are carried out deep layer P type Implantation, form ion implanted layer 9, doping content is 3 * 10
17/ cm
3After it evenly spreads, need under 600 ~ 950 degrees centigrade temperature, carry out high annealing, to eliminate irradiation damage.
In conjunction with Fig. 8.For structure shown in Figure 7, remove the photoresist on a of the first horizontal substrate surface, and remove the photoresist on the b of the second horizontal substrate surface.Then carry out the shallow trench oxidation layer and fill deposit, by method deposit silicon dioxide (SiO in sti trench groove 2 of low-pressure chemical vapor phase deposition (CVD)
2), make it cover whole sti trench groove 2, form shallow trench oxidation layer packed layer 6, use again chemico-mechanical polishing (CMP) to remove unnecessary CVD silica, thereby obtain smooth surface.
In conjunction with Fig. 9.To structure shown in Figure 8, utilize corrosive agent that sti trench groove 2 side wall sacrifice layers 5 are carried out wet etching, remove the sacrifice layer 4 of sti trench groove 2 both sides side walls, forming thickness is the air gap layer 7 of 15 ~ 20nm.
Specific embodiment two is on the basis of specific embodiment one channel bottom to be carried out the deep layer Implantation, and the method for specific embodiment one has been had good expansion, can realize better radioresistance and buffer action.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; what it should be noted that is; the above only is specific embodiments of the invention; do not limit the present invention; within the spirit and principles in the present invention all, the modulation of doing and optimization all should be included within protection scope of the present invention.
Claims (3)
1. radiation hardening shallow groove isolation structure formation method is characterized in that may further comprise the steps:
Step 1, provide semi-conductive substrate (1), on this Semiconductor substrate, form sti trench groove (2) downwards by etching;
Step 2, in sti trench groove (2) and the surface deposition sacrifice layer (4) of this Semiconductor substrate (1);
Step 3, sti trench groove (2) with sacrifice layer (4) and the surface of Semiconductor substrate (1) are carried out photoengraving, remove sti trench groove (2) bottom and the surperficial sacrifice layer (4) of Semiconductor substrate (1), expose bottom Semiconductor substrate (1);
Step 4, carry out the shallow trench oxidation layer and fill deposit, method deposit silicon dioxide in sti trench groove (2) by low-pressure chemical vapor phase deposition, make it cover sti trench groove (2), form shallow trench oxidation layer packed layer (6), remove unnecessary silicon dioxide with chemico-mechanical polishing again, obtain smooth surface;
Step 5, utilize corrosive agent that sacrifice layer (4) is carried out wet etching, remove sti trench groove (2) side wall sacrifice layer (5), form the air gap layer (7) with thickness.
2. radiation hardening shallow groove isolation structure formation method according to claim 1 is characterized in that, described Semiconductor substrate (1) material is silicon, germanium, III ~ V group iii v compound semiconductor material, II ~ VI group iii v compound semiconductor material or monocrystal material.
3. radiation hardening shallow groove isolation structure formation method according to claim 2 is characterized in that, described monocrystal material can make it become N-shaped substrate or p-type substrate by doping.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113889537A (en) * | 2021-12-07 | 2022-01-04 | 北京芯可鉴科技有限公司 | Semiconductor device and method for manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060030128A1 (en) * | 2004-08-03 | 2006-02-09 | Xiaomei Bu | Structure and method of liner air gap formation |
| CN1943023A (en) * | 2004-04-21 | 2007-04-04 | 国际商业机器公司 | Wiring structure for integrated circuit with reduced intralevel capacitance |
| CN102138210A (en) * | 2008-08-27 | 2011-07-27 | 科洛司科技有限公司 | Shallow trench isolating structure having an air gap, a cmos image sensor employing the same, and a production method therefor |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1943023A (en) * | 2004-04-21 | 2007-04-04 | 国际商业机器公司 | Wiring structure for integrated circuit with reduced intralevel capacitance |
| US20060030128A1 (en) * | 2004-08-03 | 2006-02-09 | Xiaomei Bu | Structure and method of liner air gap formation |
| CN102138210A (en) * | 2008-08-27 | 2011-07-27 | 科洛司科技有限公司 | Shallow trench isolating structure having an air gap, a cmos image sensor employing the same, and a production method therefor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113889537A (en) * | 2021-12-07 | 2022-01-04 | 北京芯可鉴科技有限公司 | Semiconductor device and method for manufacturing the same |
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Application publication date: 20130213 |