CN102890653A

CN102890653A - Instruction executing method, memory controller and memory storage device

Info

Publication number: CN102890653A
Application number: CN2011102003890A
Authority: CN
Inventors: 叶志刚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2011-07-18
Filing date: 2011-07-18
Publication date: 2013-01-23
Anticipated expiration: 2031-07-18
Also published as: CN102890653B

Abstract

The invention proposes an instruction executing method, a memory controller and a memory storage device. The method comprises the following steps: receiving a writing instruction and written data corresponding to the writing instruction from a host computer system during the period of executing data merging operation; temporarily storing the written data into a buffer memory, and transmitting response information to the host computer system at a delay time point, wherein the delay time point is set by a time point of finishing temporary storage of the written data in the buffer memory and virtual delay time. Therefore, the method can effectively correspond to the response time of a writing instruction executed during the period of executing the data merging operation at average, thereby shortening the maximal access time.

Description

Instruction executing method, Memory Controller and memorizer memory devices

Technical field

The present invention relates to a kind of instruction executing method, relate in particular to a kind of a plurality of Memory Controller and memorizer memory devices that write the instruction executing method of instruction and use the method that come from host computer system of in memorizer memory devices, carrying out.

Background technology

Digital camera, mobile phone and MP3 are very rapid in growth over the years, so that the consumer is to the also rapidly increase of demand of Storage Media.Because the characteristics such as duplicative nonvolatile memory (rewritable non-volatile memory) has that data are non-volatile, power saving, volume are little, machinery-free structure, read or write speed are fast, be suitable for most portable electronic product, for example notebook computer.Solid state hard disc is exactly a kind of with the storage device of flash memory module as Storage Media.Therefore, the flash memory industry becomes a ring quite popular in the electronic industry in recent years.

The duplicative nonvolatile memory has a plurality of physical blocks (physical block), and each physical blocks has a plurality of physical page (physical page), wherein must be according to the order of physical page data writing in order during data writing in physical blocks.In addition, after must being erased first, the physical page that has been written into data could again be used for data writing.Particularly, physical blocks is the least unit of erasing, and physical page is the programming minimum unit of (also claiming to write).Therefore, in general, in the management of duplicative nonvolatile memory module, physical blocks is divided into data field (data area) and idle district (free area) to I haven't seen you for ages.

The physical blocks of data field (also being called the data entity block) is to store the stored data of host computer system.Specifically, memory management circuitry can be converted to the logic access address of host computer system institute access the logical page (LPAGE) of logical blocks and the logical page (LPAGE) of logical blocks be mapped to the physical page of the physical blocks of data field.That is to say that in the management of flash memory module, the physical blocks of data field is the physical blocks (for example, having stored the data that host computer system writes) that is regarded as being used.For example, memory management circuitry can be put down in writing mapping relations between the physical blocks of logical blocks and data field with logical blocks-physical blocks mapping table, and wherein the logical page (LPAGE) in the logical blocks is the physical page of the physical blocks of shining upon of correspondence sequentially.

The physical blocks (also being called idle physical blocks) in idle district is the physical blocks in the data field of rotating.Specifically, as mentioned above, the physical blocks of written data must be erased just can be used for data writing again afterwards, and the idle physical blocks of distinguishing is to be designed to write more new data to replace the physical blocks of original mapping logic block.Base this, the physical blocks in idle district be sky or spendable physical blocks, i.e. no record data or be labeled as invalid data useless.

That is to say that the data field is the logical page (LPAGE) that the mode of rotating is come the mapping logic block with the physical page of the physical blocks in idle district, to store the data that host computer system was write.

For example, when host computer system wants to write the logic access address of upgrading page data when being a certain logical page (LPAGE) of a certain logical blocks of corresponding storage device, the memory management circuitry of storage device can be extracted a physical blocks from idle district, and with this more new data write in the physical page of the physical blocks of extracting.Afterwards, when the physical blocks in idle district exhausted soon, memory management circuitry can merge (Merge) operation to this logical blocks executing data.For example, in the data union operation, memory management circuitry can be extracted a physical blocks as the new data physical blocks from idle district, all up-to-date page datas that will belong to this logical blocks write so far in the new data physical blocks and with this logical blocks so far physical blocks that remaps.

In order effectively to promote access usefulness, in general, can the configuration memory buffer in the memorizer memory devices.For example, when from host computer system, receiving the data that write instruction and want to write, memory management circuitry can be with the data wanting to write and relevant information thereof (for example, this data writing is to belong to that logical page (LPAGE)) be temporary in after the memory buffer, i.e. transmission is informed and is finished this affirmation information that writes instruction to host computer system, shortens the response time thus.Afterwards, when memory buffer is filled with, just the data in the memory buffer are write in the duplicative nonvolatile memory module, store the next record data writing with the storage area of vacating memory buffer.

Yet, under the situation that memory buffer has been filled with and the physical blocks in idle district also exhausts soon, if receive come from host computer system write instruction the time, memory management circuitry need be finished the data union operation and can carry out this and write instruction.Because the executing data union operation need to spend quite a lot of time, therefore, compared to carrying out other access instructions, host computer system need be waited for that considerable time could receive and inform and finish this response message that writes instruction (response message) from memorizer memory devices.Often in this process, the user of host computer system can take for memorizer memory devices when machine or sensory memory storage device very unstable.Therefore, under the situation that memory buffer has been filled with and the idle physical blocks of distinguishing also exhausts soon, how shortening the time that host computer system receives response message, is the problem that this those skilled in the art's wish solves.

Summary of the invention

The invention provides a kind of instruction executing method, Memory Controller and memorizer memory devices, its can be on average during the executing data union operation a plurality of times that write instruction of carrying out simultaneously.

Exemplary embodiment of the present invention proposes a kind of instruction executing method, be used for memorizer memory devices, wherein this memorizer memory devices has memory buffer and duplicative nonvolatile memory module, duplicative nonvolatile memory module has a plurality of physical blocks, these physical blocks logically are grouped into data field and idle district at least, and the physical blocks of data field is mapped to a plurality of logical blocks.This instruction executing method comprises that to the first logical blocks executing data union operation among these logical blocks the valid data that wherein belong to the first logical blocks in this data union operation can be copied to the first instance block and the first instance block that extract and have a plurality of physical page from the physical blocks in idle district.This instruction executing method also comprises, during carrying out this data union operation, writes instruction from the host computer system reception and writes the data writing of instruction with corresponding this.This instruction executing method also comprises, judges that whether the number of a plurality of physical page that have been written into data among the physical page of first instance block is greater than default physical page number.This instruction executing method also comprises, when the number of the physical page that has been written into data among the physical page of first instance block non-during greater than default physical page number, data writing is temporary in this memory buffer and a time delay point transmit a response message to this host computer system, wherein this, point was to finish the time point that data writing is temporary in memory buffer to add that the dummy delay time is set and this response message writes instruction and is done in order to inform this time delay.

In one embodiment of this invention, above-mentioned instruction executing method also comprises, when the number of the physical page that has been written into data among the physical page of first instance block during greater than default physical page number, transmit above-mentioned response message to host computer system finishing the time point that data writing is temporary in memory buffer.

In one embodiment of this invention, whether above-mentioned instruction executing method also comprises the number of physical blocks that whether residual capacity of judging memory buffer belong to idle district less than pre-defined capacity and judgement less than pre-defined number, and whether this number that wherein has been written into the physical page of data among the above-mentioned physical page of judging the first instance block is to be performed during less than pre-defined number less than pre-defined capacity and the number that belongs to the idle physical blocks of distinguishing when the residual capacity of memory buffer greater than the step of default physical page number.

In one embodiment of this invention, above-mentioned instruction executing method also comprises, non-less than pre-defined capacity or to belong to the number of physical blocks in idle district non-during less than pre-defined number when the residual capacity of memory buffer, transmit above-mentioned response message to host computer system finishing the time point that data writing is temporary in memory buffer.

In one embodiment of this invention, above-mentioned instruction executing method also comprises the above-mentioned dummy delay time is set as a fixing predetermined value.

In one embodiment of this invention, above-mentioned instruction executing method also comprises according to the implementation progress of the above-mentioned data union operation of correspondence and dynamically sets the above-mentioned dummy delay time.

Exemplary embodiment of the present invention proposes a kind of Memory Controller, in order to control duplicative nonvolatile memory module.This Memory Controller comprises host interface, memory interface, memory management circuitry and memory buffer.Host interface is in order to be electrically connected to host computer system.Memory interface is electrically connected to duplicative nonvolatile memory module, and wherein this duplicative nonvolatile memory module has a plurality of physical blocks.Memory management circuitry is electrically connected to host interface and memory interface.Memory buffer is electrically connected to memory management circuitry.Memory management circuitry is distinguished with idle in order to these physical blocks logically are grouped at least the data field, and disposes a plurality of logical blocks with the physical blocks in mapping (enum) data district.In addition, memory management circuitry is to the first logical blocks executing data union operation among these logical blocks, and the valid data that belong to the first logical blocks in this data union operation can be copied to the first instance block that extracts from the physical blocks in idle district, wherein the first instance block has a plurality of physical page.In addition, during carrying out this data union operation, memory management circuitry can write instruction from the host computer system reception and write the data writing of instruction with corresponding this.In addition, memory management circuitry can judge that whether the number of the physical page that has been written into data among the physical page of first instance block is greater than default physical page number.When the number of the physical page that has been written into data among the physical page of first instance block non-during greater than default physical page number, memory management circuitry this data writing can be temporary in the memory buffer and a time delay point transmit response message to host computer system, wherein this time delay point be finish that the time point that this data writing is temporary in this memory buffer adds that the dummy delay time is set and this response message in order to inform that writing instruction is done.

In one embodiment of this invention, wherein when the number of the physical page that has been written into data among the physical page of first instance block during greater than default physical page number, memory management circuitry transmits above-mentioned response message to host computer system finishing this time point that this data writing is temporary in memory buffer.

In one embodiment of this invention, whether whether above-mentioned memory management circuitry also belong to the number of the idle physical blocks of distinguishing less than pre-defined number less than pre-defined capacity and judgement in order to the residual capacity of judging memory buffer, wherein only when the residual capacity of memory buffer less than pre-defined capacity and the number of physical blocks that belongs to idle district during less than pre-defined number, above-mentioned memory management circuitry judges that just whether the number of the physical page that has been written into data among the physical page of first instance block is greater than default physical page number.

In one embodiment of this invention, non-less than pre-defined capacity or to belong to the number of physical blocks in idle district non-during less than pre-defined number when the residual capacity of memory buffer, memory management circuitry transmits above-mentioned response message to host computer system finishing this time point that this data writing is temporary in memory buffer.

In one embodiment of this invention, the above-mentioned dummy delay time is a fixing predetermined value.

In one embodiment of this invention, above-mentioned memory management circuitry is dynamically set the above-mentioned dummy delay time according to the implementation progress of the above-mentioned data union operation of correspondence.

Exemplary embodiment of the present invention proposes a kind of memorizer memory devices, and it comprises connector, duplicative nonvolatile memory module and Memory Controller.Connector is in order to be electrically connected to host computer system.Duplicative nonvolatile memory module has a plurality of physical blocks.Memory Controller is electrically connected to duplicative nonvolatile memory module and connector.Memory Controller is distinguished with idle in order to these physical blocks logically are grouped at least the data field, and disposes a plurality of logical blocks with the physical blocks in mapping (enum) data district.In addition, Memory Controller is to the first logical blocks executing data union operation among these logical blocks, and the valid data that belong to the first logical blocks in this data union operation can be copied to the first instance block that extracts from the physical blocks in idle district, wherein the first instance block has a plurality of physical page.In addition, during carrying out this data union operation, Memory Controller can write instruction from the host computer system reception and write the data writing of instruction with corresponding this.In addition, Memory Controller can judge that whether the number of the physical page that has been written into data among the physical page of first instance block is greater than default physical page number.When the number of the physical page that has been written into data among the physical page of first instance block non-during greater than default physical page number, Memory Controller this data writing can be temporary in the memory buffer and a time delay point transmit response message to host computer system, wherein this time delay point be finish that the time point that this data writing is temporary in this memory buffer adds that the dummy delay time is set and this response message in order to inform that writing instruction is done.

In one embodiment of this invention, when the number of the physical page that has been written into data among the physical page of first instance block during greater than default physical page number, Memory Controller transmits above-mentioned response message to host computer system finishing this time point that this data writing is temporary in memory buffer.

In one embodiment of this invention, whether whether Memory Controller also belong to the number of the idle physical blocks of distinguishing less than pre-defined number less than pre-defined capacity and judgement in order to the residual capacity of judging memory buffer, wherein only when the residual capacity of memory buffer less than pre-defined capacity and the number of physical blocks that belongs to idle district during less than pre-defined number, above-mentioned Memory Controller judges that just whether the number of the physical page that has been written into data among the physical page of first instance block is greater than default physical page number.

In one embodiment of this invention, non-less than pre-defined capacity or to belong to the number of physical blocks in idle district non-during less than pre-defined number when the residual capacity of memory buffer, Memory Controller transmits above-mentioned response message to host computer system finishing this time point that this data writing is temporary in memory buffer.

In one embodiment of this invention, above-mentioned Memory Controller is dynamically set the above-mentioned dummy delay time according to the implementation progress of the above-mentioned data union operation of correspondence.

Exemplary embodiment of the present invention proposes a kind of instruction executing method, be used for memorizer memory devices, wherein this memorizer memory devices has memory buffer and duplicative nonvolatile memory module, this duplicative nonvolatile memory module has a plurality of physical blocks, these physical blocks logically are grouped into data field and idle district at least, and the physical blocks of data field is mapped to a plurality of logical blocks.This instruction executing method comprises that to the first logical blocks executing data union operation among these logical blocks the valid data that wherein belong to the first logical blocks in this data union operation can be copied to the first instance block that extracts from the physical blocks in idle district.This instruction executing method also comprises, during carrying out this data union operation, receives first from host computer system and writes instruction and corresponding first and write the first data writing of instruction and the first data writing is temporary in the memory buffer.This instruction executing method also comprises, transmit the first response message to host computer system at very first time point, wherein very first time point be finish that the time point that the first data writing is temporary in memory buffer adds that the first dummy delay time was set and the first response message in order to inform that first writes instruction and be done.

In one embodiment of this invention, above-mentioned instruction executing method also is included in to be carried out during this data union operation, receives second from host computer system and writes instruction and corresponding second and write the second data writing of instruction and the second data writing is temporary in this memory buffer.

Above-mentioned instruction executing method also is included in the second time point and transmits the second response message to host computer system, wherein the second time point be finish that the time point that the second data writing is temporary in memory buffer adds that the second dummy delay time was set and the second response message in order to inform that second writes instruction and be done.

Above-mentioned instruction executing method also is included in during the executing data union operation, receives the 3rd from host computer system and writes instruction and the corresponding the 3rd and write the 3rd data writing of instruction and the 3rd data writing is temporary in the memory buffer.

Above-mentioned instruction executing method also is included in the 3rd time point and transmits the 3rd response message to host computer system, wherein the 3rd time point be finish that the time point that the 3rd data writing is temporary in memory buffer adds that the 3rd dummy delay time was set and the 3rd response message in order to inform that the 3rd writes instruction and be done.

In one embodiment of this invention, above-mentioned instruction executing method also comprises, during the executing data union operation, receive the 4th from host computer system and write instruction and the corresponding the 4th and write the 4th data writing of instruction and the 4th data writing is temporary in the memory buffer.Above-mentioned instruction executing method also is included in the 4th time point and transmits the 4th response message to host computer system, wherein the 4th time point be finish the 4th data writing is temporary in memory buffer and finishes the data union operation after, wherein the 4th response message is in order to inform that the 4th writes instruction and be done.

In one embodiment of this invention, above-mentioned instruction executing method also comprises the first dummy delay time, the second dummy delay time and the 3rd dummy delay time is set as fixedly predetermined value.

In one embodiment of this invention, above-mentioned instruction executing method also comprises according to the implementation progress of corresponding data union operation and sets respectively the first dummy delay time, the second dummy delay time and the 3rd dummy delay time.At this, above-mentioned first instance block has a plurality of physical page, and at above-mentioned very first time point, has finished the page number of the physical page of above-mentioned data union operation among the physical page of first instance block and counted threshold value more than or equal to first page.In addition, at the second time point, finished the page number of physical page of above-mentioned data union operation among the physical page of first instance block more than or equal to the second page number threshold value, and at the 3rd time point, finished the page number of physical page of above-mentioned data union operation among the physical page of first instance block more than or equal to the 3rd page number threshold value.

Exemplary embodiment of the present invention proposes a kind of Memory Controller, in order to control duplicative nonvolatile memory module.This Memory Controller comprises host interface, memory interface, memory management circuitry and memory buffer.Host interface is in order to be electrically connected to host computer system.Memory interface is electrically connected to duplicative nonvolatile memory module, and wherein this duplicative nonvolatile memory module has a plurality of physical blocks.Memory management circuitry is electrically connected to host interface and memory interface.Memory buffer is electrically connected to memory management circuitry.Memory management circuitry is distinguished with idle in order to these physical blocks logically are grouped at least the data field, and disposes a plurality of logical blocks with the physical blocks in mapping (enum) data district.In addition, memory management circuitry is to the first logical blocks executing data union operation among these logical blocks, and the valid data that belong to the first logical blocks in the data union operation can be copied to the first instance block that extracts from the physical blocks in idle district.In addition, memory management circuitry receives first from host computer system and writes instruction and corresponding first and write the first data writing of instruction and the first data writing is temporary in the memory buffer during the executing data union operation.Moreover, memory management circuitry transmits the first response message to host computer system at very first time point, wherein very first time point be finish that the time point that the first data writing is temporary in memory buffer adds that the first dummy delay time was set and the first response message in order to inform that first writes instruction and be done.

Exemplary embodiment of the present invention proposes a kind of memorizer memory devices, and it comprises connector, duplicative nonvolatile memory module and Memory Controller.Connector is in order to be electrically connected to host computer system.Duplicative nonvolatile memory module has a plurality of physical blocks.Memory Controller is electrically connected to duplicative nonvolatile memory module and connector.Memory Controller is distinguished with idle in order to these physical blocks logically are grouped at least the data field, and disposes a plurality of logical blocks with the physical blocks in mapping (enum) data district.In addition, Memory Controller is to the first logical blocks executing data union operation among these logical blocks, and the valid data that belong to the first logical blocks in the data union operation can be copied to the first instance block that extracts from the physical blocks in idle district.In addition, Memory Controller receives first from host computer system and writes instruction and corresponding first and write the first data writing of instruction and the first data writing is temporary in the memory buffer during the executing data union operation.Moreover, Memory Controller transmits the first response message to host computer system at very first time point, wherein very first time point be finish that the time point that the first data writing is temporary in memory buffer adds that the first dummy delay time was set and the first response message in order to inform that first writes instruction and be done.

Based on above-mentioned, exemplary embodiment of the present invention can so that during the executing data union operation response each write time of instruction can be average, shorten thus the maximum access time and so that the access of memorizer memory devices is more smooth and easy.

For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate accompanying drawing to be described in detail below.

Description of drawings

Figure 1A is according to the host computer system shown in this exemplary embodiment and memorizer memory devices.

Figure 1B is the synoptic diagram according to the computing machine shown in this exemplary embodiment, input/output device and memorizer memory devices.

Fig. 1 C is according to the host computer system shown in this another exemplary embodiment and the synoptic diagram of memorizer memory devices.

Fig. 2 is the summary block scheme of the memorizer memory devices shown in Figure 1A.

Fig. 3 is the summary block scheme according to the Memory Controller shown in this exemplary embodiment.

Fig. 4 and Fig. 5 are the synoptic diagram according to the physical blocks of the duplicative of management shown in this exemplary embodiment nonvolatile memory module.

Fig. 6～Fig. 8 writes the more example of new data according to the usefulness fructification block shown in this exemplary embodiment.

Fig. 9 is the synoptic diagram according to the use fructification block shown in this exemplary embodiment and chaotic physical blocks data writing.

Figure 10 is the synoptic diagram according to the use fructification block shown in this exemplary embodiment and chaotic physical blocks data writing.

Figure 11 and 12 is the process flow diagram that writes instruction and the sequential charts that come from host computer system according to the execution shown in this exemplary embodiment.

Figure 13 is the process flow diagram according to the instruction executing method shown in this exemplary embodiment.

Figure 14 is the process flow diagram according to the instruction executing method shown in another exemplary embodiment.

Reference numeral:

1000: host computer system

1100: computing machine

1102: microprocessor

1104: random access memory

1106: input/output device

1108: system bus

1110: data transmission interface

1202: mouse

1204: keyboard

1206: display

1208: printer

1212: Portable disk

1214: memory card

1216: solid state hard disc

1310: digital camera

The 1312:SD card

The 1314:MMC card

1316: memory stick

The 1318:CF card

1320: embedded storage device

100: memorizer memory devices

102: connector

104: Memory Controller

106: duplicative nonvolatile memory module

202: memory management circuitry

204: host interface

206: memory interface

208: memory buffer

254: electric power management circuit

256: bug check and correcting circuit

502: the data field

504: idle district

506: system region

508: replace the district

410 (0)～410 (N): physical blocks

610 (0)～610 (H): logical blocks

710 (0)～710 (K): logic access address

S1101, S1103, S1105, S1107, S1109, S1111, S1113, S1115, S1117: the step of carrying out instruction

T1, T2, T3, T4: carry out the instruction time

D1, D2, D3: dummy delay time

DM: executing data union operation

S1301, S1303, S1305, S1307, S1309: the step of instruction executing method

S1401, S1403, S1405, S1407, S1409, S1411, S1413: the step of instruction executing method

Embodiment

Generally speaking, memorizer memory devices (also claiming memory storage system) comprises duplicative nonvolatile memory module and controller (also claiming control circuit).Usually memorizer memory devices is to use with host computer system, so that host computer system can write to data memorizer memory devices or reading out data from memorizer memory devices.

Figure 1A is the host computer system shown in the exemplary embodiment and memorizer memory devices according to the present invention.

Please refer to Figure 1A, host computer system 1000 generally comprises computing machine 1100 and I/O (input/output, I/O) device 1106.Computing machine 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, the display 1206 and printer 1208 such as Figure 1B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.

In embodiments of the present invention, memorizer memory devices 100 is to connect 1110 by data transmission to be electrically connected with other elements of host computer system 1000.Data can be write to memorizer memory devices 100 or reading out data from memorizer memory devices 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106.For example, memorizer memory devices 100 can be the duplicative non-volatile memory storage device of Portable disk 1212, memory card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 etc. as shown in Figure 1B.

Generally speaking, host computer system 1000 can be any system that can cooperate with memorizer memory devices 100 with storage data substantially.Although in this exemplary embodiment, host computer system 1000 is to explain with computer system, yet host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.For example, be digital camera (video camera) 1310 o'clock in host computer system, duplicative non-volatile memory storage device then is its employed SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded storage device 1320 (shown in Fig. 1 C).Embedded storage device 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that embedded multi-media card is directly to be electrically connected on the substrate of host computer system.

Please refer to Fig. 2, memorizer memory devices 100 comprises connector 102, Memory Controller 104 and duplicative nonvolatile memory module 106.

In this exemplary embodiment, connector 102 is to be compatible to Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) standard.Yet, it must be appreciated, the invention is not restricted to this, connector 102 can also be to meet Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, USB (universal serial bus) (Universal Serial Bus, USB) standard, parallel Advanced Technology Attachment (Parallel Advanced Technology Attachment, PATA) standard, safe digital (Secure Digital, SD) interface standard, memory stick (Memory Stick, MS) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, compact flash (Compact Flash, CF) interface standard, integrated form drives electrical interface (Integrated Device Electronics, IDE) standard or other standards that is fit to.

Memory Controller 104 is in order to carrying out a plurality of logic gates or the steering order with hardware pattern or firmware pattern implementation, and carries out the runnings such as writing, read, erase and merge of data in duplicative nonvolatile memory module 106 according to the instruction of host computer system 1000.

Duplicative nonvolatile memory module 106 is to be electrically connected to Memory Controller 104, and has the data that a plurality of physical blocks are write to store host computer system 1000.In this exemplary embodiment, each physical blocks has respectively a plurality of physical page, and the physical page that wherein belongs to same physical blocks can be write and side by side be erased independently.For example, each physical blocks is comprised of 128 physical page, and the capacity of each physical page is 4 kilobit tuples (Kilobyte, KB).Yet, it must be appreciated that the invention is not restricted to this, each physical blocks can be comprised of 64 physical page, 256 physical page or other arbitrarily individual physical page.

In more detail, physical blocks is the least unit of erasing.That is each physical blocks contains the storage unit of being erased in the lump of minimal amount.Physical page is the minimum unit of programming.That is, physical page is the minimum unit of data writing.Yet, it must be appreciated that in another exemplary embodiment of the present invention, the least unit of data writing can also be entity sector or other sizes.Each physical page generally includes data bit element district and redundant bit district.The data bit element district is in order to storing user's data, and redundant bit district is in order to the data (for example, bug check and correcting code) of stocking system.

In this exemplary embodiment, duplicative nonvolatile memory module 106 is multi-level cell memory (Multi Level Cell, MLC) NAND flash memory module.Yet, the invention is not restricted to this, also single-order storage unit (Single Level Cell, SLC) NAND flash memory module, other flash memory modules or other have the memory module of identical characteristics to duplicative nonvolatile memory module 106.

Fig. 3 is the summary block scheme of the Memory Controller shown in the exemplary embodiment according to the present invention.

Please refer to Fig. 3, Memory Controller 104 comprises memory management circuitry 202, host interface 204, memory interface 206 and memory buffer 208.

Memory management circuitry 202 is in order to the overall operation of control store controller 104.Specifically, memory management circuitry 202 has a plurality of steering orders, and when memorizer memory devices 100 running, these a little steering orders can be performed to carry out the runnings such as writing, read, erase and merge of data according to the instruction of host computer system 1000 in duplicative nonvolatile memory module 106.

In this exemplary embodiment, the steering order of memory management circuitry 202 is to come implementation with the firmware pattern.For example, memory management circuitry 202 has microprocessor unit (not shown) and ROM (read-only memory) (not shown), and these a little steering orders are to be burned onto in this ROM (read-only memory).When memorizer memory devices 100 running, these a little steering orders can be carried out to carry out by microprocessor unit the runnings such as writing, read and erase of data.

In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 can also the procedure code pattern be stored in the specific region (for example, being exclusively used in the system region of storage system data in the memory module) of duplicative nonvolatile memory module 106.In addition, memory management circuitry 202 has microprocessor unit (not shown), ROM (read-only memory) (not shown) and random access memory (not shown).Particularly, this ROM (read-only memory) has the code of driving section, and when Memory Controller 104 was enabled, microprocessor unit can be carried out first this driving code section steering order that will be stored in the duplicative nonvolatile memory module 106 and be loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can turn round these a little steering orders to carry out the runnings such as writing, read and erase of data.In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 can also a hardware pattern be come implementation.

Host interface 204 is instruction and the data that are electrically connected to memory management circuitry 202 and transmit in order to reception and identification host computer system 1000.That is to say that the instruction that host computer system 1000 transmits and data can be sent to memory management circuitry 202 by host interface 204.In this exemplary embodiment, host interface 204 is to be compatible to the SATA standard.Yet, it must be appreciated to the invention is not restricted to this that host interface 204 can also be to be compatible to PATA standard, IEEE1394 standard, PCI Express standard, USB standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other data transmission standards that is fit to.

Memory interface 206 is to be electrically connected to memory management circuitry 202 and in order to access duplicative nonvolatile memory module 106.That is to say that the data of wanting to write to duplicative nonvolatile memory module 106 can be converted to 106 receptible forms of duplicative nonvolatile memory module via memory interface 206.

Memory buffer 208 is to be electrically connected to memory management circuitry 202 and in order to the temporary data that come from the data and instruction of host computer system 1000 or come from duplicative nonvolatile memory module 106.Particularly, when from host computer system, receiving the data that write instruction and want to write, memory management circuitry can be with the data wanting to write and relevant information thereof (for example, this data writing is to belong to that logical page (LPAGE)) be temporary in after the memory buffer, i.e. transmission is informed and is finished this affirmation information that writes instruction to host computer system, shortens the response time thus.Until memory buffer 208 is when being filled with, memory management circuitry 202 just can write to data writing duplicative nonvolatile memory module 106 practically.

It is worth mentioning that in this exemplary embodiment, memory management circuitry 202 is to design with multiplex (MUX) (multi-task) framework.Specifically, owing to far be shorter than by memory interface 206 from the required time that host computer system 1000 receives instructions and data by host interface 204 and transmit data to duplicative nonvolatile memory module 106 and wait the required time of duplicative nonvolatile memory module 106 programming datas, therefore, carry out writing of data by the multiplex (MUX), can effectively promote the writing speed of memorizer memory devices.For example, duplicative nonvolatile memory module 106 is assigned write instruction after, memory management circuitry 202 can continue to receive next instructions from host computer system 1000, and need not to wait for that duplicative nonvolatile memory module 106 finishes this and write instruction.

In the present invention's one exemplary embodiment, Memory Controller 104 also comprises electric power management circuit 254.Electric power management circuit 254 is to be electrically connected to memory management circuitry 202 and in order to the power supply of control store storage device 100.

In the present invention's one exemplary embodiment, Memory Controller 104 also comprises bug check and correcting circuit 256.Bug check and correcting circuit 256 be electrically connected to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives from host computer system 1000 when writing instruction, bug check can produce corresponding bug check and correcting code (Error Checking and Correcting Code for the corresponding data that this writes instruction with correcting circuit 256, ECC Code), and memory management circuitry 202 the corresponding data that this writes instruction can be write in the duplicative nonvolatile memory module 106 with corresponding bug check and correcting code.Afterwards, when memory management circuitry 202 can read bug check corresponding to these data and correcting code during reading out data simultaneously from duplicative nonvolatile memory module 106, and bug check and correcting circuit 256 can be according to this bug check and correcting code data execution error inspection and the correction program to reading.

Fig. 4 and Fig. 5 are the synoptic diagram of the physical blocks of the duplicative of management shown in exemplary embodiment nonvolatile memory module according to the present invention.

Please refer to Fig. 4, duplicative nonvolatile memory module 106 has physical blocks 410 (0)～410 (N), and the memory management circuitry 202 of Memory Controller 104 can logically be grouped into physical blocks 410 (0)～410 (N) data field (data area) 502, idle district (free area) 504, system region (system area) 506 and replace district (replacement area) 508.

The physical blocks that belongs in logic data field 502 and idle district 504 is the data that come from host computer system 1000 in order to storage.Specifically, the physical blocks of data field 502 (also being called the data entity block) is to be regarded as the physical blocks of storage data, and the physical blocks (also being called idle physical blocks) in idle district 504 is the physical blocks that write new data.For example, when receiving from host computer system 1000 when writing instruction with the data wanting to write, memory management circuitry 202 can be extracted physical blocks from idle district 504, and data are write so far in the physical blocks.Again for example, when to a certain logical blocks executing data union operation, memory management circuitry 202 can be extracted physical blocks and come data writing as the new data physical blocks of corresponding this logical blocks from idle district 504, and replaces the data entity block of original this logical blocks of mapping.

The physical blocks that belongs in logic system region 506 is in order to the register system data.For example, system data comprises about the manufacturer of duplicative nonvolatile memory module and model, the physical blocks number of duplicative nonvolatile memory module, physical page number of each physical blocks etc.

Belonging in logic the physical blocks that replaces in the district 508 is to replace program for bad physical blocks, with replacing damaged physical blocks.Specifically, if when replacing the physical blocks damage that still has normal physical blocks and data field 502 in the district 508, memory management circuitry 202 can be extracted the physical blocks that normal physical blocks is changed damage from replace district 508.

Based on above-mentioned, in the running of memorizer memory devices 100, data field 502, idle district 504, system region 506 can dynamically change with the physical blocks that replaces district 508.For example, the physical blocks in order to the storage data of rotating can belong to data field 502 or idle district 504 with changing.

It is worth mentioning that in this exemplary embodiment, memory management circuitry 202 is to manage take each physical blocks as unit.Yet, the invention is not restricted to this, in another exemplary embodiment, memory management circuitry 202 also can be grouped into physical blocks a plurality of solid elements, and manages take solid element as unit.For example, each solid element can be comprised of at least one physical blocks in same storer submodule group or the different memory submodule group.In addition, in another exemplary embodiment of the present invention, these a little physical blocks or solid element also can be divided into a plurality of zones and manage respectively.

Please refer to Fig. 5, memory management circuitry 202 can configuration logic blocks 610 (0)～610 (H) with the physical blocks in mapping (enum) data district 502, wherein each logical blocks has a plurality of logical page (LPAGE)s and this a little logical page (LPAGE)s are the physical page of shining upon in order corresponding data entity block.For example, when memorizer memory devices 100 was formatted, logical blocks 610 (0)～610 (H) is the physical blocks 410 (0)～410 (F-1) in mapping (enum) data district 502 initially.

In exemplary embodiment of the present invention, memory management circuitry 202 meeting service logic block-physical blocks mapping tables (logical block-physical block mapping table) are with the mapping relations between the physical blocks of record logical blocks 610 (0)～610 (H) and data field 502.In addition, because host computer system 1000 with the logic access address (for example is, sector (Sector)) for unit comes access data, memory management circuitry 202 can convert the logic access address 710 (0)～710 (K) of corresponding stored device storage device 100 to corresponding logical page (LPAGE) when host computer system 1000 access data.For example, when host computer system 1000 is wanted a certain logic of access access address, memory management circuitry 202 can be converted to the logic access address of 1000 accesses of host computer system the multi-dimensional address that logical blocks and logical page (LPAGE) with correspondence are consisted of, and passes through logical blocks-physical blocks mapping table access data in the physical page of correspondence.For example, when memorizer memory devices 100 was formatted, memory management circuitry 202 can be initially maps to logical blocks 610 (0)～610 (H) with the physical blocks of data field 502.Particularly, after initialization, although the physical blocks of data field 502 is not written into data practically, it still can be regarded as the physical blocks of storage data.

Through after the above-mentioned initialize routine, but memorizer memory devices 100 just the instruction that writes of Receiving Host system 1000 come data writing.

Fig. 6～Fig. 8 is that the usefulness fructification block shown in the exemplary embodiment writes the more example of new data according to the present invention.

Please be simultaneously with reference to Fig. 6～Fig. 8, for example, to map under the mapping status of physical blocks 410 (0) in logical blocks 610 (0), write instruction and want data writing when belonging to the logical page (LPAGE) of logical blocks 610 (0) when Memory Controller 104 receives from host computer system 1000, memory management circuitry 202 can be to map to physical blocks 410 (0) and extract the as an alternative physical blocks physical blocks 410 (0) of rotating of physical blocks 410 (F) from idle district 504 according to logical blocks-physical blocks mapping table recognition logic block 610 (0) at present.Yet, when memory management circuitry 202 write to physical blocks 410 (F) with new data, memory management circuitry 202 can not moved all valid data in the physical blocks 410 (0) to physical blocks 410 (F) and the physical blocks 410 (0) of erasing at once.Specifically, memory management circuitry 202 can write physical page valid data before (namely with wanting in the physical blocks 410 (0), the 0th physical page of physical blocks 410 (0) and the data in the 1st physical page) be copied in the 0th physical page of physical blocks 410 (F) and the 1st physical page (as shown in Figure 6), and new data is write in the 2nd～4 physical page of physical blocks 410 (F) (as shown in Figure 7).At this moment, memory management circuitry 202 is namely finished the running that writes.Because the valid data in the physical blocks 410 (0) might be in next operation (for example, write instruction) in become invalidly, therefore at once other valid data in the physical blocks 410 (0) are moved to physical blocks 410 (F) and may be caused meaningless moving.In addition, data must write to the physical page in the physical blocks in order, therefore, memory management circuitry 202 only can be moved first and want to write physical page valid data before (namely, be stored in data in the 0th physical page of physical blocks 410 (0) and the 1st physical page), and wouldn't move all the other valid data (that is, being stored in data in the 5th～K physical page of physical blocks 410 (0)).

In this exemplary embodiment, the running of temporarily keeping these transient state relations is called unlatching (open) mother and child blocks, and former physical blocks (for example, above-mentioned physical blocks 410 (0)) is called female physical blocks and replaces physical blocks (for example, above-mentioned with physical blocks 410 (F)) and be called the fructification block.At this, female physical blocks with and corresponding at least one fructification block be called the mother and child blocks group.

Afterwards, in the time the data of physical blocks 410 (0) and physical blocks 410 (F) need to being merged (merge), memory management circuitry 202 can be whole and to a physical blocks with the data of physical blocks 410 (F) with physical blocks 410 (0), promotes thus the service efficiency of physical blocks.At this, the running that merges mother and child blocks is called the data union operation or closes (close) mother and child blocks.For example, as shown in Figure 9, when closing mother and child blocks, memory management circuitry 202 can be with remaining valid data in the physical blocks 410 (0) (namely, data in the 5th～K physical page of physical blocks 410 (0)) be copied in the 5th physical page of replacing physical blocks 410 (F)～K physical page, then the physical blocks 410 (0) of physical blocks 410 (0) being carried out after erase operation for use also will be erased is associated to idle district 504, simultaneously, physical blocks 410 (F) is associated to data field 502.That is to say that memory management circuitry 202 can remap logical blocks 610 (0) to physical blocks 410 (F) in logical blocks-physical blocks mapping table.In addition, in this exemplary embodiment, memory management circuitry 202 can be set up idle district physical blocks table (not shown) and record the physical blocks that is associated at present idle district 504.It is worth mentioning that the number of physical blocks is limited in the idle district 504, base this, during memorizer memory devices 100 runnings, the number of the mother and child blocks group of having opened also can be restricted.Therefore, when memorizer memory devices 100 receive come from host computer system 1000 write instruction the time, when if the number of physical blocks is less than pre-defined number in the idle district 504, memory management circuitry 202 need be closed and just can be carried out this after at least one group of mother and child blocks group of having opened at present and write instruction.For example, in this exemplary embodiment, this pre-defined number can be set to 2.But it must be appreciated that pre-defined number also can be other suitable numbers.

Write more the new data with the fructification block except above-mentioned, in this exemplary embodiment, in this exemplary embodiment, memory management circuitry 202 also can be extracted at least one physical blocks and write more new data as chaotic (Random) physical blocks and with chaotic physical blocks from idle district 504.For example, if when the data of the logical page (LPAGE) that host computer system 1000 wishs are upgraded have been written into the fructification block, this more new data can be written into chaotic physical blocks, to avoid repeatedly carrying out above-mentioned data union operation.

Fig. 9 is the synoptic diagram of the use fructification block shown in the exemplary embodiment and chaotic physical blocks data writing according to the present invention.

Please refer to Fig. 9, suppose that physical blocks 410 (S-1) is extracted as chaotic physical blocks and under storing state shown in Figure 7 when host computer system 1000 wants to write new data more to the 1st logical page (LPAGE) of logical blocks 610 (0), memory management circuitry 202 can with this more new data write in first empty physical page in the chaotic physical blocks (for example, the 0th physical page of physical blocks 410 (S-1)).

In this exemplary embodiment, when present employed chaotic physical blocks has been fully written, memory management circuitry 202 meetings are extracted another physical blocks as new chaotic physical blocks again from idle district 504, until the idle number of physical blocks in 504 of distinguishing is less than pre-defined number.Specifically, the physical blocks in idle district 504 is limited, therefore, also can be restricted as the number of the physical blocks of chaotic physical blocks.When the number of physical blocks in the idle district 504 during less than pre-defined number, memory management circuitry 202 can be carried out above-mentioned data union operation, and the chaotic physical blocks that stored data are all invalid data is carried out the physical blocks of erasing running and will erase and is associated to idle district 504.Thus, when the execution next one write instruction, memory management circuitry 202 just can be extracted empty physical blocks as chaotic physical blocks from idle district 504 again.

Figure 10 is the example according to the executing data union operation shown in this exemplary embodiment.

Please refer to Figure 10, if under state shown in Figure 9 during to logical blocks 610 (0) executing data union operation, memory management circuitry 202 can be extracted the physical blocks 410 (F+1) of a sky from idle district 504, the valid data that will belong to logical blocks 610 (0) copy to physical blocks 410 (F+1) from female physical blocks 410 (0), fructification block 410 (F) and chaotic physical blocks 410 (S-1), and logical blocks 610 (0) is remapped to physical blocks 410 (F+1).

Specifically, in the valid data reproduction process, the data in the 0th physical page of physical blocks 410 (0) can be read and be written into the 0th physical page of physical blocks 410 (F+1).Then, the data in the 1st physical page of physical blocks 410 (S-1) can be read and be written into the 1st physical page of physical blocks 410 (F+1).Afterwards, the data in the 2nd～4 physical page of physical blocks 410 (F) can be read and be written in order the 2nd～4 physical page of physical blocks 410 (F+1) in order.At last, the data in the 5th～K physical page of physical blocks 410 (0) can be read and be written in order the 5th～K physical page of physical blocks 410 (F+1) in order.That is to say, in the data union operation, memory management circuitry 202 must be constantly assigned duplicative nonvolatile memory module 106 and is read and write instruction and duplicative nonvolatile memory module 106 and need cost considerable time just can finish this to read and write instruction.

As mentioned above, because memory management circuitry 202 has multiplex's function, therefore, after duplicative nonvolatile memory module 106 was assigned instruction, memory management circuitry 202 still can receive instruction from host computer system 1000.Particularly, in this exemplary embodiment, when to duplicative nonvolatile memory module 106 executing data union operations and receive when writing instruction and corresponding this and writing the data writing of instruction from host computer system 1000 simultaneously, the residual capacity (that is, available storage area) that memory management circuitry 202 can be judged memory buffer 208 whether less than pre-defined capacity and the number of judging the physical blocks in the idle district 504 whether less than pre-defined number.At this, for example, pre-defined capacity is to be set to 16KB, but the invention is not restricted to this.

If the residual capacity of memory buffer 208 is less than the number of the physical blocks in pre-defined capacity and the idle district 504 during less than pre-defined number, after corresponding this data writing that writes instruction is temporary in memory buffer 208, memory management circuitry 202 can wait one section dummy delay and just will indicate the response message of having finished instruction to send host computer system 1000 to after the time, and can not send this response message to host computer system 1000 immediately.

In more detail, owing to the time that the executing data union operation is required is longer, therefore, during the executing data union operation, memory management circuitry 202 may receive a plurality of instructions that write from host computer system 1000.If when memory buffer 208 has been fully written in receiving this process that writes a bit instruction, what memory management circuitry 202 must could continue after finishing the data union operation and the partial data memory buffer 208 in write to duplicative nonvolatile memory module 106 that reception comes from host computer system 1000 writes instruction and data writing thereof.That is to say that finish the data union operation at need and could continue to carry out and write in the situation of instruction, several write instruction with respect to the front, host computer system 1000 must wait long time can receive that just corresponding this writes the instruction response message.Therefore, in exemplary embodiment of the present invention, memory management circuitry 202 can wait one dummy delay period after writing instruction and just transmit response message carrying out this, so that it is comparatively average to carry out each time that writes instruction.

Figure 11 and 12 is the process flow diagram that writes instruction and the sequential charts that come from host computer system 1000 according to the execution shown in this exemplary embodiment, it carries out a plurality of examples that write instruction during being presented at the executing data consolidation procedure simultaneously, wherein the residual capacity of memory buffer 208 less than the number of the physical blocks in pre-defined capacity and the idle district 504 less than pre-defined number.

Please be simultaneously with reference to Figure 11 and Figure 12, the residual capacity of supposing memory buffer 208 only can be deposited in the situation of corresponding 3 data writings that write instruction again, in step S1101, memory management circuitry 202 can be to a logical blocks (hereinafter referred to as the first logical blocks) beginning executing data union operation DM (that is the valid data that, will belong to the first logical blocks copy to a physical blocks (hereinafter referred to as the first instance block)).

In step S1103, memory management circuitry 202 can receive from host computer system 1000 and write instruction (writing instruction hereinafter referred to as first) and write the data writing (hereinafter referred to as the first data writing) of instruction with corresponding this.Then, in step S1105, memory management circuitry 202 cost a period of time T1 carry out this and first write instruction so that the first data writing is temporary in the memory buffer 208, and finish first write instruction and wait a dummy delay time D 1 (hereinafter referred to as the first dummy delay time) after, indication first is write the response message (hereinafter referred to as the first response message) that instruction has been done sends host computer system 1000 to.At this, the time point that transmits the first response message also is called very first time point.

Afterwards, in step S1107, memory management circuitry 202 receives the next one from host computer system 1000 and writes instruction (writing instruction hereinafter referred to as second) and write the data writing (hereinafter referred to as the second data writing) of instruction with corresponding this.Then, in step S1109, memory management circuitry 202 cost a period of time T2 carry out this and second write instruction so that the second data writing is temporary in the memory buffer 208, and finish second write instruction and wait a dummy delay time D 2 (hereinafter referred to as the second dummy delay time) after, indication second is write the response message (hereinafter referred to as the second response message) that instruction has been done sends host computer system 1000 to.At this, the time point that transmits the second response message also is called the second time point.

Afterwards, in step S1111, memory management circuitry 202 receives the next one from host computer system 1000 and writes instruction (writing instruction hereinafter referred to as the 3rd) and write the data writing (hereinafter referred to as the 3rd data writing) of instruction with corresponding this.Then, in step S1113, memory management circuitry 202 cost a period of time T3 carry out this and the 3rd write instruction so that the 3rd data writing is temporary in the memory buffer 208, and finish the 3rd write instruction and wait a dummy delay time D 3 (hereinafter referred to as the 3rd dummy delay time) after, indication the 3rd is write the response message (hereinafter referred to as the 3rd response message) that instruction has been done sends host computer system 1000 to.At this, the time point that transmits the 3rd response message also is called the 3rd time point.

Afterwards, in step S1115, when memory management circuitry 202 receives the next one and writes instruction (writing instruction hereinafter referred to as the 4th) and write the data writing (hereinafter referred to as the 4th data writing) of instruction with corresponding this from host computer system 1000.Then, in step S1117, memory management circuitry 202 cost a period of time T4 carry out this and the 4th write instruction so that the 4th data writing is temporary in the memory buffer 208, and finish the 4th write instruction after, indication the 4th is write the response message (hereinafter referred to as the 4th response message) that instruction has been done sends host computer system 1000 to.At this, the time point that transmits the 4th response message also is called the 4th time point.Particularly, because memory buffer 208 is filled with, therefore, memory management circuitry 202 need finish data union operation DM and with memory buffer 208 in after the data of part write to duplicative nonvolatile memory module 106, the 4th data writing could be temporary in the memory buffer 208.Therefore, compared to time T 1, time T 2 and time T 3, finish the 4th write the required time T of instruction 4 can be longer.

In this example, the first dummy delay time D 1, the second dummy delay time D 2 are identical fixedly preset values of setting in advance with the 3rd dummy delay time D 3, and it can make time T 1 add that the time of the first dummy delay time D 1, time that time T 2 adds the second dummy delay time D 2, time and time T 4 difference each other that time T 3 adds the 3rd dummy delay time D 3 are less.For example, in the example of Figure 11, the required time of executing data union operation can approximately be estimated and the first dummy delay time D 1, the second dummy delay time D 2 and the 3rd dummy delay time D 3 can be set the estimated time divided by 4.

In addition, in another exemplary embodiment of the present invention, memory management circuitry 202 also can be set the first dummy delay time D 1, the second dummy delay time D 2 and the 3rd dummy delay time D 3 respectively according to the implementation progress of corresponding data union operation.

For example, in Figure 11 and the described example of Figure 12, memory management circuitry 202 can decide the first dummy delay time D 1, the second dummy delay time D 2 and the 3rd dummy delay time D 3 according to the page number that the first instance block has been written into valid data.Specifically, when finishing first when writing instruction, memory management circuitry 202 can continue to judge whether the number of having finished the physical page (that is, being written into the physical page of valid data) of data union operation in the first instance block counts threshold value more than or equal to first page.When the number of the physical page of having finished the data union operation in the first instance block was counted threshold value more than or equal to first page, memory management circuitry 202 can transmit the first response message to host computer system 1000.And when finishing second when writing instruction, memory management circuitry 202 can continue judge that whether the number of the physical page of having finished the data union operation in the first instance block is more than or equal to the second page number threshold value.When the number of the physical page of having finished the data union operation in the first instance block during more than or equal to the second page number threshold value, memory management circuitry 202 can transmit the second response message to host computer system 1000.Similarly, finish the 3rd when writing instruction, memory management circuitry 202 can continue judge that whether the number of the physical page of having finished the data union operation in the first instance block is more than or equal to the 3rd page number threshold value.When the number of the physical page of having finished the data union operation in the first instance block during more than or equal to the 3rd page number threshold value, memory management circuitry 202 can transmit the 3rd response message to host computer system 1000.For example, in this exemplary embodiment, a physical blocks has 128 physical page, and first page is counted threshold value, the second page number threshold value and the 3rd page number threshold value and can be set as respectively accordingly 32,64 and 96.

That is to say that the first dummy delay time D 1, the second dummy delay time D 2 and the 3rd dummy delay time D 3 are that the implementation progress according to the data union operation is dynamically determined.

Figure 13 is the process flow diagram according to the instruction executing method shown in this exemplary embodiment, and it carries out a plurality of steps that write instruction during being presented at the executing data consolidation procedure continuously.

Please refer to Figure 13, beginning to some logical blocks (namely, the first above-mentioned logical blocks) the executing data union operation (namely, step S1301) afterwards, in step S1303, memory management circuitry 202 meetings reception from host computer system 1000 writes instruction and corresponding this writes the data writing of instruction, and in step S1305, memory management circuitry 202 can judge whether the number for the physical page that has been written into valid data in the target entity block (that is, above-mentioned first instance block) that writes valid data presets number of pages greater than one in the data union operation.For example, default number of pages can be set to a physical blocks the physical page number 75%.For example, in this exemplary embodiment, a physical blocks has 128 physical page, and default number of pages is set to 96.

If being used for writing the target entity block of valid data in the data union operation, to be written into the number of physical page of valid data non-during greater than default number of pages, in step S1307, memory management circuitry 202 can be temporary in data writing in the memory buffer 208 and wait one section dummy delay after the time (that is, at some time delay) transmit indication finish write instruction response message to host computer system 1000.

If when in the data union operation, being used for writing the number of physical page that the target entity block of valid data has been written into valid data greater than default number of pages, in step S1309, memory management circuitry 202 can after the data union operation is finished, be temporary in data writing in the memory buffer 208 and transmit indication finish write instruction response message to host computer system 1000.

It is worth mentioning that, as mentioned above, if memory buffer 208 still has enough residual capacities or idle district 504 when still having enough physical blocks, memory management circuitry 202 can keep in the data writing that comes from host computer system 1000 to memory buffer 208 rapidly or temporarily write in the chaotic physical blocks, shortens thus response and writes the required time of instruction.Therefore, Figure 13 be process flow diagram according to the instruction executing method shown in this exemplary embodiment can also comprise judge memory buffer 208 residual capacity whether less than pre-defined capacity and the number of judging the physical blocks in the idle district 504 whether less than the step (as shown in figure 14) of pre-defined number.

Figure 14 is the process flow diagram according to the instruction executing method shown in another exemplary embodiment, and it carries out a plurality of steps that write instruction during being presented at the executing data consolidation procedure continuously.

Please refer to Figure 14, beginning to some logical blocks (namely, the first above-mentioned logical blocks) the executing data union operation (namely, step S1401) afterwards, in step S1403, memory management circuitry 202 meetings reception from host computer system 1000 writes instruction and corresponding this writes the data writing of instruction, and in step S1405, whether the residual capacity that memory management circuitry 202 can be judged memory buffer 208 is less than pre-defined capacity and judge that whether the idle number of the physical blocks in 504 of distinguishing is less than pre-defined number.

If the non-number less than the physical blocks in pre-defined capacity or the idle district 504 of the residual capacity of memory buffer 208 is non-during less than pre-defined number, in step S1407, memory management circuitry 202 can be temporary in data writing in the memory buffer 208 and transmit immediately afterwards indication finish write instruction response message to host computer system 1000.

If the residual capacity of memory buffer 208 is less than the number of the physical blocks in pre-defined capacity and the idle district 504 during less than pre-defined number, in step S1409, memory management circuitry 202 can judge whether the number for the physical page that has been written into valid data in the target entity block (that is, above-mentioned first instance block) that writes valid data presets number of pages greater than one in the data union operation.

If being used for writing the target entity block of valid data in the data union operation, to be written into the number of physical page of valid data non-during greater than default number of pages, in step S1411, memory management circuitry 202 can be temporary in data writing in the memory buffer 208 and wait one section dummy delay after the time (that is, at some time delay) transmit indication finish write instruction response message to host computer system 1000.

If when in the data union operation, being used for writing the number of physical page that the target entity block of valid data has been written into valid data greater than default number of pages, in step S1413, memory management circuitry 202 can after the data union operation is finished, be temporary in data writing in the memory buffer 208 and transmit indication finish write instruction response message to host computer system 1000.

In sum, when during the data union operation, carry out come from host computer system write instruction the time, the instruction executing method of exemplary embodiment of the present invention, Memory Controller and memorizer memory devices can finish write instruction and wait one section dummy delay the time after just transmission indicate and finish the response message of instruction to host computer system.Thus, during the executing data union operation with corresponding each write the response time equalization of instruction and so that the access of memorizer memory devices is more smooth and easy.

Although the present invention discloses as above with embodiment, so it is not to limit the present invention, any person of an ordinary skill in the technical field, but do a little change and retouching, and do not break away from the spirit and scope of the present invention.

Claims

1. instruction executing method, be used for a memorizer memory devices, wherein this memorizer memory devices has a memory buffer and a duplicative nonvolatile memory module, this duplicative nonvolatile memory module has a plurality of physical blocks, those physical blocks logically are grouped into a data field and an idle district at least, and those physical blocks of this data field are mapped to a plurality of logical blocks, and this instruction executing method comprises:

One first logical blocks among those logical blocks is carried out a data union operation, and the valid data that wherein belong to this first logical blocks in this data union operation can be copied to the first instance block and this first instance block that extract and have a plurality of physical page from those physical blocks in this idle district;

During carrying out this data union operation, from a host computer system receive one write instruction with to writing a data writing of instruction;

Judge that whether a number of a plurality of physical page that have been written into data among those physical page of this first instance block is greater than a default physical page number; And

When the number of those physical page that have been written into data among those physical page of this first instance block non-during greater than this default physical page number, this data writing is temporary in this memory buffer and a time delay point transmit a response message to this host computer system, wherein should put time delay is to finish the time point that this data writing is temporary in this memory buffer to add that the dummy delay time is set and this response message writes instruction and is done in order to inform this.

2. instruction executing method according to claim 1 wherein also comprises:

When the number of those physical page that have been written into data among those physical page of this first instance block during greater than this default physical page number, transmit this response message to this host computer system finishing this time point that this data writing is temporary in this memory buffer.

3. instruction executing method according to claim 1 wherein also comprises:

Whether the number of those physical blocks whether a residual capacity of judging this memory buffer belongs to this idle district less than a pre-defined capacity and judgement less than a pre-defined number,

Whether this number of wherein judging those physical page that have been written into data among those physical page of this first instance block is to be performed during less than this pre-defined number less than this pre-defined capacity and this number of those physical blocks of belonging to this idle district when this residual capacity of this memory buffer greater than the step of this default physical page number.

4. instruction executing method according to claim 3 wherein also comprises:

Non-less than this pre-defined capacity or to belong to this number of those physical blocks in this idle district non-during less than this pre-defined number when this residual capacity of this memory buffer, transmit this response message to this host computer system finishing this time point that this data writing is temporary in this memory buffer.

5. instruction executing method according to claim 1 wherein also comprises:

This dummy delay time is set as a fixing predetermined value.

6. instruction executing method according to claim 1 wherein also comprises:

According to a implementation progress that should the data union operation is dynamically set this dummy delay time.

7. Memory Controller, in order to control a duplicative nonvolatile memory module, this Memory Controller comprises:

One host interface is in order to be electrically connected to a host computer system;

One memory interface is electrically connected to this duplicative nonvolatile memory module, and wherein this duplicative nonvolatile memory module has a plurality of physical blocks;

One memory management circuitry is electrically connected to this host interface and this memory interface; And

One memory buffer is electrically connected to this memory management circuitry,

Wherein this memory management circuitry is in order to logically being grouped into those physical blocks at least one data field and an idle district, and disposes a plurality of logical blocks shining upon those physical blocks of this data field,

Wherein this memory management circuitry is carried out a data union operation to one first logical blocks among those logical blocks, and the valid data that belong to this first logical blocks in this data union operation can be copied to a first instance block that extracts from those physical blocks in this idle district, wherein this first instance block has a plurality of physical page

Wherein this memory management circuitry is during carrying out this data union operation, from this host computer system receive one write instruction with to should writing a data writing of instruction,

Wherein this memory management circuitry can judge a plurality of physical page that have been written into data among those physical page of this first instance block a number whether greater than a default physical page number,

Wherein when the number of those physical page that have been written into data among those physical page of this first instance block non-during greater than this default physical page number, this memory management circuitry this data writing can be temporary in this memory buffer and a time delay point transmit a response message to this host computer system, wherein should put time delay is to finish the time point that this data writing is temporary in this memory buffer to add that the dummy delay time is set and this response message writes instruction and is done in order to inform this.

8. Memory Controller according to claim 7,

Wherein when the number of those physical page that have been written into data among those physical page of this first instance block during greater than this default physical page number, this memory management circuitry transmits this response message to this host computer system finishing this time point that this data writing is temporary in this memory buffer.

9. Memory Controller according to claim 7,

Wherein this memory management circuitry also whether belong to this idle district less than a pre-defined capacity and judgement in order to a residual capacity of judging this memory buffer a number of those physical blocks whether less than a pre-defined number,

Wherein only when this residual capacity of this memory buffer less than this pre-defined capacity and this number of those physical blocks of belonging to this idle district during less than this pre-defined number, this memory management circuitry judges that just whether this number of those physical page that have been written into data among those physical page of this first instance block is greater than this default physical page number.

10. Memory Controller according to claim 9,

Wherein non-less than this pre-defined capacity or to belong to this number of those physical blocks in this idle district non-during less than this pre-defined number when this residual capacity of this memory buffer, this memory management circuitry transmits this response message to this host computer system finishing this time point that this data writing is temporary in this memory buffer.

11. Memory Controller according to claim 7, wherein this dummy delay time is a fixing predetermined value.

12. Memory Controller according to claim 7, wherein this memory management circuitry is according to a implementation progress that should the data union operation is dynamically set this dummy delay time.

13. a memorizer memory devices comprises:

A connector is in order to be electrically connected to a host computer system;

One duplicative nonvolatile memory module has a plurality of physical blocks; And

One Memory Controller is electrically connected to this duplicative nonvolatile memory module and this connector,

Wherein this Memory Controller is in order to logically being grouped into those physical blocks at least one data field and an idle district, and disposes a plurality of logical blocks shining upon those physical blocks of this data field,

Wherein this Memory Controller is carried out a data union operation to one first logical blocks among those logical blocks, and the valid data that belong to this first logical blocks in this data union operation can be copied to a first instance block that extracts from those physical blocks in this idle district, wherein this first instance block has a plurality of physical page

Wherein this Memory Controller is during carrying out this data union operation, from this host computer system receive one write instruction with to should writing a data writing of instruction,

Wherein this Memory Controller can judge a plurality of physical page that have been written into data among those physical page of this first instance block a number whether greater than a default physical page number,

Wherein when the number of those physical page that have been written into data among those physical page of this first instance block non-during greater than this default physical page number, this Memory Controller this data writing can be temporary in this memory buffer and a time delay point transmit a response message to this host computer system, wherein should put time delay is to finish the time point that this data writing is temporary in this memory buffer to add that the dummy delay time is set and this response message writes instruction and is done in order to inform this.

14. memorizer memory devices according to claim 13,

Wherein when the number of those physical page that have been written into data among those physical page of this first instance block during greater than this default physical page number, this Memory Controller transmits this response message to this host computer system finishing this time point that this data writing is temporary in this memory buffer.

15. memorizer memory devices according to claim 13,

Wherein this Memory Controller also whether belong to this idle district less than a pre-defined capacity and judgement in order to a residual capacity of judging this memory buffer a number of those physical blocks whether less than a pre-defined number,

Wherein only when this residual capacity of this memory buffer less than this pre-defined capacity and this number of those physical blocks of belonging to this idle district during less than this pre-defined number, this Memory Controller judges that just whether this number of those physical page that have been written into data among those physical page of this first instance block is greater than this default physical page number.

16. memorizer memory devices according to claim 15, wherein non-less than this pre-defined capacity or to belong to this number of those physical blocks in this idle district non-during less than this pre-defined number when this residual capacity of this memory buffer, this Memory Controller transmits this response message to this host computer system finishing this time point that this data writing is temporary in this memory buffer.

17. memorizer memory devices according to claim 13, wherein this dummy delay time is a fixing predetermined value.

18. memorizer memory devices according to claim 13, wherein this Memory Controller is according to a implementation progress that should the data union operation is dynamically set this dummy delay time.

19. instruction executing method, be used for a memorizer memory devices, wherein this memorizer memory devices has a memory buffer and a duplicative nonvolatile memory module, this duplicative nonvolatile memory module has a plurality of physical blocks, those physical blocks logically are grouped into a data field and an idle district at least, and those physical blocks of this data field are mapped to a plurality of logical blocks, and this instruction executing method comprises:

One first logical blocks among those logical blocks is carried out a data union operation, and the valid data that wherein belong to this first logical blocks in this data union operation can be copied to a first instance block that extracts from those physical blocks in this idle district;

During carrying out this data union operation, from a host computer system receive one first write instruction with to should first writing one first data writing of instruction and this first data writing be temporary in this memory buffer; And

Transmit one first response message to this host computer system at very first time point, wherein should put the very first time is to finish that the time point that this first data writing is temporary in this memory buffer adds that one first dummy delay time was set and this first response message first writes instruction and is done in order to inform this.

20. instruction executing method according to claim 19 wherein also comprises:

During carrying out this data union operation, from this host computer system receive one second write instruction with to should second writing one second data writing of instruction and this second data writing be temporary in this memory buffer;

Transmit one second response message at one second time point and give this host computer system, wherein this second time point is to finish that the time point that this second data writing is temporary in this memory buffer adds that one second dummy delay time was set and this second response message second writes instruction and is done in order to inform this;

During carrying out this data union operation, from this host computer system receive one the 3rd write instruction with to should the 3rd writing one the 3rd data writing of instruction and the 3rd data writing be temporary in this memory buffer;

Transmit one the 3rd response message at one the 3rd time point and give this host computer system, wherein the 3rd time point be finish that the time point that the 3rd data writing is temporary in this memory buffer adds that one the 3rd dummy delay time was set and the 3rd response message in order to inform that the 3rd writes instruction and be done.

21. instruction executing method according to claim 19 wherein also comprises:

During carrying out this data union operation, from this host computer system receive one the 4th write instruction with to should the 4th writing one the 4th data writing of instruction and the 4th data writing be temporary in this memory buffer; And

Transmit one the 4th response message to this host computer system at one the 4th time point, wherein the 4th time point be finish the 4th data writing is temporary in this memory buffer and finishes this data union operation after, wherein the 4th response message is in order to inform that the 4th writes instruction and be done.

22. instruction executing method according to claim 20 wherein also comprises:

This first dummy delay time, this second dummy delay time and the 3rd dummy delay time are set as a fixing predetermined value.

23. instruction executing method according to claim 20 wherein also comprises:

According to a implementation progress that should the data union operation is set this first dummy delay time, this second dummy delay time and the 3rd dummy delay time respectively,

Wherein this first instance block has a plurality of physical page,

Wherein at this very first time point, finished a page number of a plurality of physical page of this data union operation among those physical page of this first instance block and counted threshold value more than or equal to a first page,

Wherein at this second time point, finished this page number of those physical page of this data union operation among those physical page of this first instance block more than or equal to one second page number threshold value,

Wherein at the 3rd time point, finished this page number of those physical page of this data union operation among those physical page of this first instance block more than or equal to one the 3rd page number threshold value.

24. a Memory Controller, in order to control a duplicative nonvolatile memory module, this Memory Controller comprises:

Wherein this memory management circuitry is carried out a data union operation to one first logical blocks among those logical blocks, and the valid data that belong to this first logical blocks in this data union operation can be copied to a first instance block that extracts from those physical blocks in this idle district

Wherein this memory management circuitry is during carrying out this data union operation, from this host computer system receive one first write instruction with to should first writing one first data writing of instruction and this first data writing be temporary in this memory buffer,

Wherein this memory management circuitry transmits one first response message to this host computer system at very first time point, and wherein should put the very first time is to finish that the time point that this first data writing is temporary in this memory buffer adds that one first dummy delay time was set and this first response message first writes instruction and is done in order to inform this.

25. a memorizer memory devices comprises:

A connector is in order to be electrically connected to a host computer system;

Wherein this Memory Controller is carried out a data union operation to one first logical blocks among those logical blocks, and the valid data that belong to this first logical blocks in this data union operation can be copied to a first instance block that extracts from those physical blocks in this idle district

Wherein this Memory Controller is during carrying out this data union operation, from this host computer system receive one first write instruction with to should first writing one first data writing of instruction and this first data writing be temporary in this memory buffer,

Wherein this Memory Controller transmits one first response message to this host computer system at very first time point, and wherein should put the very first time is to finish that the time point that this first data writing is temporary in this memory buffer adds that one first dummy delay time was set and this first response message first writes instruction and is done in order to inform this.