CN102882412A - Single-phase seven-level inverter - Google Patents
Single-phase seven-level inverter Download PDFInfo
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- CN102882412A CN102882412A CN2012104212058A CN201210421205A CN102882412A CN 102882412 A CN102882412 A CN 102882412A CN 2012104212058 A CN2012104212058 A CN 2012104212058A CN 201210421205 A CN201210421205 A CN 201210421205A CN 102882412 A CN102882412 A CN 102882412A
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Abstract
The invention discloses a single-phase seven-level inverter and an application circuit thereof. The single-phase seven-level inverter comprises two direct current power supplies, a boosted circuit, eight switching tubes, and six diodes. With respect to the phenomenon that voltage-sharing measures and a large filter need to be adopted in the prior art to prevent the problems of large size, increased cost, much loss and low efficiency of the inverter, resulting from overvoltage across the diode; and compared with the prior art, the numbers of diodes, the switching tubes and capacitance devices are greatly reduced relative to the traditional diode clamping multi-level inverter. While a channel is provided for the current, small size small loss and high efficiency of the whole inverter are ensured at the same time; and meanwhile the boosted circuit widens the voltage input range, and is applicable to situations with a higher voltage.
Description
Technical field
The present invention relates to electric and electronic technical field, particularly a kind of single-phase seven electrical level inverters.
Background technology
In recent years, multilevel converter is more and more concerned, compares two traditional Level Technology, and multilevel converter has that devices switch stress is low, and switching loss is little, the characteristics that output filter is little and harmonic content is little, and it is mainly used in big-and-middle three-phase inverter.
Referring to figure l, this figure is the diode clamping type five-electrical level inverter topology that provides in the prior art.
In the structure of the five-electrical level inverter of the diode clamping type shown in the figure l, diode DB1, DB2, DB3, DB4, DB5 and DB6 are clamped formula diode, and its effect is to provide path and protection electric capacity not by short circuit for electric current.For example, the first diode DB1 is used for the current potential of switch transistor T l lower end is clamped in the lower end of the first capacitor C l; The second diode DB2 is used for the current potential of switch transistor T 5 lower ends is clamped in the lower end of the first capacitor C l; Other diodes DB3, DB4, DB5 and DB6 are similar, do not repeat them here.
Yet; being reached for electric current provides path and protection electric capacity not by the purpose of short circuit; clamped formula diode then needs to block many times of level voltages; usually need the clamped formula diode series connection of a plurality of same nominal values; but be based on the dispersiveness of clamped formula diode and the impact of stray parameter; the pressure that the clamped formula diode that nominal value is identical can bear is difference to some extent also, and being together in series like this to cause the clamped formula diode two ends overvoltage that has.Therefore, need to all press measure and very large RC(phase-shift circuit) absorbing circuit, but will cause like this long-pending huge of inductance in the inverter and filter capacitor, the cost increase.
Summary of the invention
In view of this, the application provides a kind of single-phase seven electrical level inverters, in order to solve five-electrical level inverter systems bulky and the higher technical problem of cost of existing diode clamping type.
A kind of single-phase seven electrical level inverters is characterized in that, comprising:
The first DC source and second DC source of series connection;
Input is connected in parallel on the booster circuit at the first DC source two ends;
The first electric capacity, the second electric capacity and the 3rd electric capacity of connecting successively; The common port of described the second electric capacity and the 3rd electric capacity links to each other with the first output of described booster circuit and the negative pole of the first DC source respectively; The end that described the first electric capacity does not connect the second electric capacity links to each other with the second output of described booster circuit; The common port of described the first electric capacity and the second electric capacity links to each other with the positive pole of the first DC source;
The first diode that negative electrode links to each other with the common port of described the first electric capacity and the second electric capacity, the anodic bonding of described the first diode has the input of the first switching tube;
The second diode that anode links to each other with the common port of described the first electric capacity and the second electric capacity, the negative electrode of described the second diode is connected with the input of second switch pipe;
The 3rd diode that anode links to each other with the common port of described the second electric capacity and the 3rd electric capacity, the negative electrode of described the 3rd diode is connected with the input of the 3rd switching tube;
The 4th diode that negative electrode links to each other with the common port of described the second electric capacity and the 3rd electric capacity, the anodic bonding of described the 4th diode has the input of the 4th switching tube;
The output of described the first switching tube links to each other with the output of the 4th switching tube;
The output of described second switch pipe links to each other with the output of the 3rd switching tube;
The 5th switching tube that output links to each other with the second output of described booster circuit, the input of described the 5th switching tube is connected with the output of the 6th switching tube, and the input of described the 6th switching tube links to each other with the negative pole of the second DC source;
The 7th switching tube that output links to each other with the output of the 5th switching tube, the input of described the 7th switching tube links to each other with the output of described the 3rd switching tube;
The 8th switching tube that input links to each other with the negative pole of the second DC source, the output of described the 8th switching tube links to each other with the output of described four switching tubes;
The 5th diode that negative electrode links to each other with the second output of described booster circuit, the anode of described the 5th diode links to each other with the output of described the 4th switching tube;
The 6th diode that anode links to each other with the negative pole of the second DC source, the negative electrode of described the 6th diode links to each other with the output of described the 3rd switching tube.
Preferably, described switching tube is MOS (metal-oxide-semiconductor) transistor or technotron or insulated gate bipolar transistor;
When described switching tube was MOS (metal-oxide-semiconductor) transistor pipe or technotron, the input of described switching tube was source electrode, and described output is drain electrode, and the control end of the described pipe that opens the light is grid;
When described switching tube was insulated gate bipolar transistor, the input of described switching tube was collector electrode, and the output of the described pipe that opens the light is emitter, and described control end is base stage.
Preferably, described diode is silicon carbide diode or fast recovery diode or supper-fast recovery diode.
Preferably, filtering and the net unit of single-phase seven electrical level inverters comprise: the first inductance, the second inductance and filter capacitor, wherein:
The filter capacitor first end links to each other with the 5th switching tube input;
The first inductance and the second inductance are in series;
The common port of the first inductance and the second inductance links to each other with the second end of filter capacitor, and the end that the first inductance does not link to each other with the second inductance links to each other with the output of the 3rd switching tube; The end that the second inductance does not link to each other with the first inductance links to each other with the output of the 4th switching tube.
Preferably, the control end of described the first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube and the 8th switching tube is connected with control chip, and described control chip is controlled described single-phase seven electrical level inverters and realized eight kinds of meritorious operation modes;
When being in first mode, described control chip is controlled described the 7th switching tube and the 6th switching tube conducting, and the rest switch pipe is cut-off:
When being in second mode, described control chip is controlled described second switch pipe and the 6th switching tube conducting, and the rest switch pipe is cut-off;
When being in the 3rd mode, described control chip is controlled described the 3rd switching tube and the 6th switching tube conducting, and the rest switch pipe is cut-off;
When being in the 4th mode, described control chip is controlled described the 6th switching tube conducting, and the rest switch pipe is cut-off;
When being in the 5th mode, described control chip is controlled described the 8th switching tube and the 5th switching tube conducting, and the rest switch pipe is cut-off;
When being in the 6th mode, described control chip is controlled described the 4th switching tube and the 5th switching tube conducting, and the rest switch pipe is cut-off;
When being in the 7th mode, described control chip is controlled described the first switching tube and the 5th switching tube conducting, and the rest switch pipe is cut-off;
When being in the 8th mode, described control chip is controlled described the 5th switching tube conducting, and the rest switch pipe is cut-off;
Preferably, described control chip is controlled described single-phase seven electrical level inverters and is realized eight kinds of idle operation modes:
When being in the 9th mode, described control chip is controlled described the 8th switching tube and the 6th switching tube conducting, and the rest switch pipe is cut-off;
When being in the tenth mode, described control chip is controlled described the 4th switching tube and the 6th switching tube conducting, and the rest switch pipe is cut-off;
When being in 11 mode, described control chip is controlled described the first switching tube and the 6th switching tube conducting, and the rest switch pipe is cut-off;
When being in 12 mode, described control chip is controlled described the 6th switching tube conducting, and the rest switch pipe is cut-off;
When being in 13 mode, described control chip is controlled described the 7th switching tube and the 5th switching tube conducting, and the rest switch pipe is cut-off;
When being in 14 mode, described control chip is controlled described second switch pipe and the 5th switching tube conducting, and the rest switch pipe is cut-off;
When being in 15 mode, described control chip is controlled described the 3rd switching tube and the 5th switching tube conducting, and the rest switch pipe is cut-off;
When being in 16 mode, described control chip is controlled described the 5th switching tube conducting, and the rest switch pipe is cut-off;
Preferably, filtering and the net unit of described single-phase seven electrical level inverters comprise: the first inductance, the second inductance, filter capacitor and isolating transformer, wherein:
The first end of isolating transformer primary coil links to each other with the 5th switching tube input;
The first inductance and the second inductance are in series;
The common port of the first inductance and the second inductance links to each other with the second end of isolating transformer primary coil, and the end that the first inductance does not link to each other with the second inductance links to each other with the output of the 3rd switching tube; The end that the second inductance does not link to each other with the first inductance links to each other with the output of the 4th switching tube;
Two terminals of filter capacitor link to each other with two terminals of isolating transformer secondary coil respectively.
A kind of single-phase seven level inverse conversion unit is characterized in that, are applied to single-phase seven electrical level inverters, comprising:
The first electric capacity, the second electric capacity and the 3rd electric capacity of connecting successively; The common port of described the second electric capacity and the 3rd electric capacity links to each other with the negative pole of described the first DC source and the positive pole of the second DC source respectively; The common port of described the first electric capacity and the second electric capacity links to each other with the positive pole of the first DC source;
The first diode that negative electrode links to each other with the common port of described the first electric capacity and the second electric capacity, the anodic bonding of described the first diode has the input of the first switching tube;
The second diode that anode links to each other with the common port of described the first electric capacity and the second electric capacity, the negative electrode of described the second diode is connected with the input of second switch pipe;
The 3rd diode that anode links to each other with the common port of described the second electric capacity and the 3rd electric capacity, the negative electrode of described the 3rd diode is connected with the input of the 3rd switching tube;
The 4th diode that negative electrode links to each other with the common port of described the second electric capacity and the 3rd electric capacity, the anodic bonding of described the 4th diode has the input of the 4th switching tube;
The output of described the first switching tube links to each other with the output of the 4th switching tube;
The output of described second switch pipe links to each other with the output of the 3rd switching tube;
The 5th switching tube that output links to each other with the end that described the first electric capacity does not link to each other with the second electric capacity, the input of described the 5th switching tube is connected with the output of the 6th switching tube, and the input of described the 6th switching tube links to each other with the negative pole of the second DC source;
The 7th switching tube that output links to each other with the output of the 5th switching tube, the input of described the 7th switching tube links to each other with the output of described the 3rd switching tube;
The 8th switching tube that input links to each other with the negative pole of the second DC source, the output of described the 8th switching tube links to each other with the output of described four switching tubes;
The 5th diode that negative electrode links to each other with described the 5th switching tube output, the anode of described the 5th diode links to each other with the output of described the 4th switching tube;
The 6th diode that anode links to each other with the negative pole of the second DC source, the negative electrode of described the 6th diode links to each other with the output of described the 3rd switching tube.
Preferably, filtering and the net unit of described single-phase seven level inverse conversion unit comprise: the first inductance, the second inductance and filter capacitor, wherein:
The filter capacitor first end links to each other with the 5th switching tube input;
The first inductance and the second inductance are in series;
The common port of the first inductance and the second inductance links to each other with the second end of filter capacitor, and the end that the first inductance does not link to each other with the second inductance links to each other with the output of the 3rd switching tube; The end that the second inductance does not link to each other with the first inductance links to each other with the output of the 4th switching tube.
Preferably, filtering and the net unit of described single-phase seven level inverse conversion unit comprise: the first inductance, the second inductance, filter capacitor and isolating transformer, wherein:
The first end of isolating transformer primary coil links to each other with the 5th switching tube input;
The first inductance and the second inductance are in series;
The common port of the first inductance and the second inductance links to each other with the second end of isolating transformer primary coil, and the end that the first inductance does not link to each other with the second inductance links to each other with the output of the 3rd switching tube; The end that the second inductance does not link to each other with the first inductance links to each other with the output of the 4th switching tube;
Two terminals of filter capacitor link to each other with two terminals of isolating transformer secondary coil respectively.
Preferably, single-phase seven level inverse conversion unit also comprise:
Input is connected in parallel on the booster circuit at the first DC source two ends;
The first output of described booster circuit links to each other with the common port of described the second electric capacity and the 3rd electric capacity; The second output of booster circuit is not connected the second electric capacity with the first electric capacity a end links to each other.
By such scheme as can be known the present invention do not comprise the clamped formula diode of using in the diode clamping type five-electrical level inverter in the prior art, to solve existing diode clamping type five-electrical level inverter systems bulky and the higher technical problem of cost.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The five-electrical level inverter topology of the diode clamping type that provides in the prior art is provided Fig. 1;
Fig. 2 is the circuit diagram of disclosed a kind of single-phase seven electrical level inverters of the embodiment of the invention;
Single-phase seven electrical level inverters that Fig. 3 provides for the embodiment of the invention are in the circuit diagram of the first meritorious mode;
Single-phase seven electrical level inverters that Fig. 4 provides for the embodiment of the invention are in the circuit diagram of the second meritorious mode;
Single-phase seven electrical level inverters that Fig. 5 provides for the embodiment of the invention are in the circuit diagram of the 3rd meritorious mode;
Single-phase seven electrical level inverters that Fig. 6 provides for the embodiment of the invention are in the circuit diagram of the 4th meritorious mode;
Single-phase seven electrical level inverters that Fig. 7 provides for the embodiment of the invention are in the circuit diagram of the 5th meritorious mode;
Single-phase seven electrical level inverters that Fig. 8 provides for the embodiment of the invention are in the circuit diagram of the 6th meritorious mode;
Single-phase seven electrical level inverters that Fig. 9 provides for the embodiment of the invention are in the circuit diagram of the 7th meritorious mode;
Single-phase seven electrical level inverters that Figure 10 provides for the embodiment of the invention are in the circuit diagram of the 8th meritorious mode;
Figure 11 is different constantly output voltage variation diagrams corresponding to single-phase seven electrical level inverters;
Single-phase seven electrical level inverters that Figure 12 provides for the embodiment of the invention are in the circuit diagram of the 9th idle mode;
Single-phase seven electrical level inverters that Figure 13 provides for the embodiment of the invention are in the circuit diagram of the tenth idle mode;
Single-phase seven electrical level inverters that Figure 14 provides for the embodiment of the invention are in the circuit diagram of the 11 idle mode;
Single-phase seven electrical level inverters that Figure 15 provides for the embodiment of the invention are in the circuit diagram of the 12 idle mode;
Single-phase seven electrical level inverters that Figure 16 provides for the embodiment of the invention are in the circuit diagram of the 13 idle mode;
Single-phase seven electrical level inverters that Figure 17 provides for the embodiment of the invention are in the circuit diagram of the 14 idle mode;
Single-phase seven electrical level inverters that Figure 18 provides for the embodiment of the invention are in the circuit diagram of the 15 idle mode;
Single-phase seven electrical level inverters that Figure 19 provides for the embodiment of the invention are in the circuit diagram of the 16 idle mode;
Figure 20 is the circuit diagram of disclosed a kind of single-phase seven electrical level inverters of the embodiment of the invention for this figure.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
As shown in Figure 2, be disclosed a kind of single-phase seven electrical level inverters of the embodiment of the invention, comprise:
The first DC source DC of series connection
1With the second DC source DC
2
Input is connected in parallel on the first DC source DC
1The booster circuit Boost at two ends;
First capacitor C of connecting successively
1, the second capacitor C
2With the 3rd capacitor C
3Described the second capacitor C
2With the 3rd capacitor C
3Common port O respectively with the first output and the first DC source DC of described booster circuit Boost
1Negative pole link to each other; Described the first capacitor C
1Do not connect the second capacitor C
2An end link to each other with the second output of described booster circuit Boost; Described the first capacitor C
1With the second capacitor C
2Common port and the first DC source DC
1Positive pole link to each other;
Negative electrode and described the first capacitor C
1With the second capacitor C
2The first diode D of linking to each other of common port
1, described the first diode D
1Anodic bonding the first switching tube Q is arranged
H1Input;
Anode and described the first capacitor C
1With the second capacitor C
2The second diode Q of linking to each other of common port
H2, described the second diode D
2Negative electrode be connected with second switch pipe Q
H2Input;
Anode and described the second capacitor C
2With the 3rd capacitor C
3The 3rd diode D that links to each other of common port
3, described the 3rd diode D
3Negative electrode be connected with the 3rd switching tube Q
H3Input;
Negative electrode and described the second capacitor C
2With the 3rd capacitor C
3The 4th diode D that links to each other of common port O
4, described the 4th diode D
4Anodic bonding the 4th switching tube Q is arranged
H4Input;
Described the first switching tube Q
H1Output and the 4th close pipe Q
H4Output link to each other;
Second switch pipe Q
H2Output and the 3rd switching tube Q
H3Output link to each other;
The 5th switching tube Q that output links to each other with the second output of described booster circuit Boost
L5, described the 5th switching tube Q
L5Input be connected with the 6th switching tube Q
L6Output, described the 6th switching tube Q
L6Input and the second DC source DC
2Negative pole link to each other;
Output and the 5th switching tube Q
L5The 7th switching tube Q that links to each other of output
H7, described the 7th switching tube Q
H7Input and described the 3rd switching tube Q
H3Output link to each other;
Input and the second DC source DC
2The 8th switching tube Q that links to each other of negative pole
H8, described the 8th switching tube Q
H8Output and described four switching tube Q
H4Output link to each other;
The 5th diode D that negative electrode links to each other with the second output of described booster circuit Boost
5, described the 5th diode D
5Anode and described the 4th switching tube Q
H4Output link to each other;
Anode and the second DC source DC
2The 6th diode D that links to each other of negative pole
6, described the 6th diode D
6Negative electrode and described the 3rd switching tube D
6Output link to each other.
The single-phase seven electrical level inverter topologys that the present embodiment provides comprise a Boost circuit; eight switching tubes and six diodes; the switching tube conductings different with control by the metering function of diode just can provide path and protection electric capacity not by short circuit for electric current; cast out the clamped formula diode of using in the prior art; reached the purpose that reduces the inverter volume; and because prime has increased the Boost circuit, so that input voltage range broadens the more high-tension occasion of suitable input.
Need to prove, switching tube can be MOS (metal-oxide-semiconductor) transistor or technotron or insulated gate bipolar transistor;
When described switching tube was MOS (metal-oxide-semiconductor) transistor or technotron, the input of described switching tube was source electrode, and described output is drain electrode, and the control end of the described pipe that opens the light is grid;
When described switching tube was insulated gate bipolar transistor, the input of described switching tube was collector electrode, and the output of the described pipe that opens the light is emitter, and described control end is base stage.Be understandable that above eight switching tubes also can select the switching tube of other types.
Need to prove, described diode is silicon carbide diode or fast recovery diode or supper-fast recovery diode.Be understandable that, described diode also can be selected the diode of other types.
Need to prove, in other embodiments of the invention, filtering and net unit that single-phase seven electrical level inverters comprise as shown in Figure 2, comprising: the first inductance L
1, the second inductance L
2, filter capacitor C
0, wherein:
Filter capacitor C
0First end and the 5th switching tube Q
L5Input links to each other;
The first inductance L
1With the second inductance L
2Be in series;
The first inductance L
1With the second inductance L
2Common port and filter capacitor C
0The second end link to each other the first inductance L
1Not with the second inductance L
2The end and the 3rd switching tube Q that link to each other
H3Output link to each other; The second inductance L
2Not with the first inductance L
1The end and the 4th switching tube Q that link to each other
H4Output link to each other.
In above-mentioned two embodiment of the present invention, described the first switching tube Q
H1, second switch pipe Q
H2, the 3rd switching tube Q
H3, the 4th switching tube Q
H4, the 5th switching tube Q
L5, the 6th switching tube Q
L6, the 7th switching tube Q
H7With the 8th switching tube Q
H8Control end be connected with control chip, described control chip is controlled described single-phase seven electrical level inverters and is realized eight kinds of meritorious operation modes, and each operation mode only has at most two switching tube conductings.
In order to clearly demonstrate eight meritorious operation modes of described single-phase seven electrical level inverters of the embodiment of the invention, come eight operation modes are described in detail below in conjunction with accompanying drawing.
Referring to Fig. 3, this figure is the circuit diagram that single-phase seven electrical level inverters that the embodiment of the invention provides are in the first meritorious mode.
When being in first mode, described control chip is controlled described the 7th switching tube Q
H7With the 6th switching tube Q
L6Conducting, the rest switch pipe is cut-off.
The trend of electric current is Q
H7-L
1-u
g-Q
L6-C
3-C
2-C
1-Q
H7
Referring to Fig. 4, this figure is the circuit diagram that single-phase seven electrical level inverters that the embodiment of the invention provides are in the second meritorious mode.
When being in second mode, described control chip is controlled described second switch pipe Q
H2With the 6th switching tube Q
L6Conducting, the rest switch pipe is cut-off.
The trend of electric current is D
2-Q
H2-L
1-u
g-Q
L6-C
3-C
2-D
2
Referring to Fig. 5, this figure is the circuit diagram that single-phase seven electrical level inverters that the embodiment of the invention provides are in the 3rd meritorious mode.
When being in the 3rd mode, described control chip is controlled described the 3rd switching tube Q
H3With the 6th switching tube Q
L6Conducting, the rest switch pipe is cut-off.
The trend of electric current is D
3-Q
H3-L
1-u
g-Q
L6-C
3-D
3
Referring to Fig. 6, this figure is the circuit diagram that single-phase seven electrical level inverters that the embodiment of the invention provides are in the 4th meritorious mode.
When being in the 4th mode, described control chip is controlled described the 6th switching tube conducting, and the rest switch pipe is cut-off.
The trend of electric current is L
1-u
g-Q
L6-D
6-L
1
Referring to Fig. 7, this figure is the circuit diagram that single-phase seven electrical level inverters that the embodiment of the invention provides are in the 5th meritorious mode.
When being in the 5th mode, described control chip is controlled described the 8th switching tube Q
H8With the 5th switching tube Q
L5Conducting, the rest switch pipe is cut-off.
The trend of electric current is Q
H8-C
3-C
2-C
1-Q
L5-u
g-L
2-Q
H8
Referring to Fig. 8, this figure is the circuit diagram that single-phase seven electrical level inverters that the embodiment of the invention provides are in the 6th meritorious mode.
When being in the 6th mode, described control chip is controlled described the 4th switching tube Q
H4With the 5th switching tube Q
L5Conducting, the rest switch pipe is cut-off.
The trend of electric current is Q
H4-D
4-C
2-C
1-Q
L5-u
g-L
2-Q
H4
Referring to Fig. 9, this figure is the circuit diagram that single-phase seven electrical level inverters that the embodiment of the invention provides are in the 7th meritorious mode.
When being in the 7th mode, described control chip is controlled described the first switching tube Q
H1With the 5th switching tube Q
L5Conducting, the rest switch pipe is cut-off.
The trend of electric current is Q
H1-D
1-C
1-Q
L5-u
g-L
2-Q
H1
Referring to Figure 10, this figure is the circuit diagram that single-phase seven electrical level inverters that the embodiment of the invention provides are in the 8th meritorious mode.
When being in the 8th mode, described control chip is controlled described the 5th switching tube Q
L5Conducting, the rest switch pipe is cut-off.
The trend of electric current is Q
L5-u
g-L
2-D
5-Q
L5
U wherein
gBe load.
As shown in figure 11, this figure is different constantly output voltage variation diagrams corresponding to single-phase seven electrical level inverters.
When inverter worked in meritorious mode, the control chip control inverter was realized the switching between the different modalities, and output voltage also changes along with the variation of inverter operation mode:
t
0-t
1Interior described control chip of time period is controlled described single-phase seven electrical level inverters and is become the 3rd mode by the 4th mode, and output voltage becomes U by output voltage 0
1
t
1-t
2Interior described control chip of time period is controlled described single-phase seven electrical level inverters and is become second mode by the 3rd mode, and output voltage is by U
1Become U
2
t
2-t
3Interior described control chip of time period is controlled described single-phase seven electrical level inverters and is become first mode by second mode, and output voltage is by U
2Become U
3
T in the other times section
3-t
4, t
4-t
5, t
5-t
6, t
6-t
7, t
7-t
8, t
8-t
9, t
9-t
10, t
10-t
11And t
11-t
12Described control chip controls described single-phase seven electrical level inverter Mode variations and the output voltage variation is similar, does not repeat them here.
In order to clearly demonstrate eight idle operation modes of described single-phase seven electrical level inverters of the embodiment of the invention, come eight kinds of idle operation modes are described in detail below in conjunction with accompanying drawing.
Referring to Figure 12, this figure is the circuit diagram that single-phase seven electrical level inverters that the embodiment of the invention provides are in the 9th idle mode.
When being in the 9th mode, described control chip is controlled described the 8th switching tube Q
H8With the 6th switching tube Q
L6Conducting, the rest switch pipe is cut-off;
The trend of electric current is Q
H8-Q
L6-u
g-L
2-Q
H8
Referring to Figure 13, this figure is the circuit diagram that single-phase seven electrical level inverters that the embodiment of the invention provides are in the tenth idle mode.
When being in the tenth mode, described control chip is controlled described the 4th switching tube Q
H4With the 6th switching tube Q
L6Conducting, the rest switch pipe is cut-off;
The trend of electric current is Q
H4-D
4-C
3-Q
L6-u
g-L
2-Q
H4
Referring to Figure 14, this figure is the circuit diagram that single-phase seven electrical level inverters that the embodiment of the invention provides are in the 11 idle mode.
When being in 11 mode, described control chip is controlled described the first switching tube Q
H1With the 6th switching tube Q
L6Conducting, the rest switch pipe is cut-off;
The trend of electric current is Q
H1-D
1-C
2-C
3-Q
L6-u
g-L
2-Q
H1
Referring to Figure 15, single-phase seven electrical level inverters that the embodiment of the invention provides are in the circuit diagram of the 12 idle mode.
When being in 12 mode, described control chip is controlled described the 6th switching tube Q
L6Conducting, the rest switch pipe is cut-off;
The trend of electric current is Q
L6-u
g-L
2-D
5-C
1-C
2-C
3-Q
L6
Referring to Figure 16, this figure is the circuit diagram that single-phase seven electrical level inverters that the embodiment of the invention provides are in the 13 idle mode.
When being in 13 mode, described control chip is controlled described the 7th switching tube Q
H7With the 5th switching tube Q
L5Conducting, the rest switch pipe is cut-off;
The trend of electric current is Q
H7-L
1-u
g-Q
L5-Q
H7
Referring to Figure 17, this figure is the circuit diagram that single-phase seven electrical level inverters that the embodiment of the invention provides are in the 14 idle mode.
When being in 14 mode, described control chip is controlled described second switch pipe Q
H2With the 5th switching tube Q
L5Conducting, the rest switch pipe is cut-off;
The trend of electric current is D
2-Q
H2-L
1-u
g-Q
L5-C
1-D
2
Referring to Figure 18, this figure is the circuit diagram that single-phase seven electrical level inverters that the embodiment of the invention provides are in the 15 idle mode.
When being in 15 mode, described control chip is controlled described the 3rd switching tube Q
H3With the 5th switching tube Q
L5Conducting, the rest switch pipe is cut-off;
The trend of electric current is D
3-Q
H3-L
1-u
g-Q
L5-C
1-C
2-D
3
Referring to Figure 19, this figure is the circuit diagram that single-phase seven electrical level inverters that the embodiment of the invention provides are in the 16 idle mode.
When being in 16 mode, described control chip is controlled described the 5th switching tube Q
L5Conducting, the rest switch pipe is cut-off;
The trend of electric current is D
6-L
1-u
g-Q
L5-C
1-C
2-C
3-D
6
Referring to Figure 20, this figure is the circuit diagram of disclosed a kind of single-phase seven electrical level inverters of the embodiment of the invention.
When high frequency switched, in order to prevent the common mode leakage problem, filtering and the net unit of described single-phase seven electrical level inverters comprised: the first inductance, the second inductance, filter capacitor and isolating transformer, wherein:
The first end of isolating transformer primary coil links to each other with the 5th switching tube input;
The first inductance and the second inductance are in series;
The common port of the first inductance and the second inductance links to each other with the second end of isolating transformer primary coil, and the end that the first inductance does not link to each other with the second inductance links to each other with the output of the 3rd switching tube; The end that the second inductance does not link to each other with the first inductance links to each other with the output of the 4th switching tube;
Two terminals of filter capacitor link to each other with two terminals of isolating transformer secondary coil respectively.
Be understandable that, when high frequency switches, can produce the common mode leakage problem in order to prevent the present invention, described filtering and net unit also can comprise the RC circuit of connecting with filter capacitor.
A kind of single-phase seven level inverse conversion unit disclosed by the invention are applied to single-phase seven electrical level inverters, comprising:
The first electric capacity, the second electric capacity and the 3rd electric capacity of connecting successively; The common port of described the second electric capacity and the 3rd electric capacity links to each other with the negative pole of described the first DC source and the positive pole of the second DC source respectively; The common port of described the first electric capacity and the second electric capacity links to each other with the positive pole of the first DC source;
The first diode that negative electrode links to each other with the common port of described the first electric capacity and the second electric capacity, the anodic bonding of described the first diode has the input of the first switching tube;
The second diode that anode links to each other with the common port of described the first electric capacity and the second electric capacity, the negative electrode of described the second diode is connected with the input of second switch pipe;
The 3rd diode that anode links to each other with the common port of described the second electric capacity and the 3rd electric capacity, the negative electrode of described the 3rd diode is connected with the input of the 3rd switching tube;
The 4th diode that negative electrode links to each other with the common port of described the second electric capacity and the 3rd electric capacity, the anodic bonding of described the 4th diode has the input of the 4th switching tube;
The output of described the first switching tube links to each other with the output of the 4th switching tube;
The output of described second switch pipe links to each other with the output of the 3rd switching tube;
The 5th switching tube that output links to each other with the end that described the first electric capacity does not link to each other with the second electric capacity, the input of described the 5th switching tube is connected with the output of the 6th switching tube, and the input of described the 6th switching tube links to each other with the negative pole of the second DC source;
The 7th switching tube that output links to each other with the output of the 5th switching tube, the input of described the 7th switching tube links to each other with the output of described the 3rd switching tube;
The 8th switching tube that input links to each other with the negative pole of the second DC source, the output of described the 8th switching tube links to each other with the output of described four switching tubes;
The 5th diode that negative electrode links to each other with described the 5th switching tube output, the anode of described the 5th diode links to each other with the output of described the 4th switching tube;
The 6th diode that anode links to each other with the negative pole of the second DC source, the negative electrode of described the 6th diode links to each other with the output of described the 3rd switching tube.
Need to prove, the switching tube in these single-phase seven level inverse conversion unit can be MOS (metal-oxide-semiconductor) transistor or technotron or insulated gate bipolar transistor;
When described switching tube was MOS (metal-oxide-semiconductor) transistor pipe or technotron, the input of described switching tube was source electrode, and described output is drain electrode, and the control end of the described pipe that opens the light is grid;
When described switching tube was insulated gate bipolar transistor, the input of described switching tube was collector electrode, and the output of the described pipe that opens the light is emitter, and described control end is base stage.Be understandable that above eight switching tubes also can select the switching tube of other types.
Need to prove, the diode in these single-phase seven level inverse conversion unit is silicon carbide diode or fast recovery diode or supper-fast recovery diode.Be understandable that, described diode also can be selected the diode of other types.
Need to prove, in other embodiments of the invention, filtering and net unit that single-phase seven level inverse conversion unit comprise comprise: the first inductance, the second inductance and filter capacitor, wherein:
The filter capacitor first end links to each other with the 5th switching tube input;
The first inductance and the second inductance are in series;
The common port of the first inductance and the second inductance links to each other with the second end of filter capacitor, and the end that the first inductance does not link to each other with the second inductance links to each other with the output of the 3rd switching tube; The end that the second inductance does not link to each other with the first inductance links to each other with the output of the 4th switching tube.
Need to prove, in other embodiment of the present invention seven level inverse conversion unit, filtering and the net unit of described single-phase seven level inverse conversion unit comprise: the first inductance, the second inductance, filter capacitor and isolating transformer, wherein:
The first end of isolating transformer primary coil links to each other with the 5th switching tube input;
The first inductance and the second inductance are in series;
The common port of the first inductance and the second inductance links to each other with the second end of isolating transformer primary coil, and the end that the first inductance does not link to each other with the second inductance links to each other with the output of the 3rd switching tube; The end that the second inductance does not link to each other with the first inductance links to each other with the output of the 4th switching tube;
Two terminals of filter capacitor link to each other with two terminals of isolating transformer secondary coil respectively.
Be understandable that, when high frequency switches, can produce the common mode leakage problem in order to prevent the present invention, described filtering and net unit also can comprise the RC circuit of connecting with filter capacitor.
Need to prove that described single-phase seven level inverse conversion unit also comprise:
Input is connected in parallel on the booster circuit at the first DC source two ends;
The first output of described booster circuit links to each other with the common port of described the second electric capacity and the 3rd electric capacity; The second output of booster circuit is not connected the second electric capacity with the first electric capacity a end links to each other.
As can be seen from the above embodiments, compare with diode clamping type five Level Technology of prior art, level number of the present invention is more, the voltage change ratio of switching tube and inductance is less, and described single-phase seven electrical level inverters have at most the simultaneously conducting of two switching tubes at different modalities, switching loss and magnetic element loss are less, and, because increasing of level number, the current ripples of single-phase seven electrical level inverters output of the present invention reduces, the grid current harmonic content reduces, so that the body volume of the filter in the inverter obviously reduces the cost of inverter.And increased the Boost booster circuit among the present invention, so that the scope of input voltage is wider, suitable input is the occasion of high pressure more.
Each embodiment adopts the mode of going forward one by one to describe in this specification, and what each embodiment stressed is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can be in the situation that do not break away from the spirit or scope of the present invention, in other embodiments realization.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. single-phase seven electrical level inverters is characterized in that, comprising:
The first DC source and second DC source of series connection;
Input is connected in parallel on the booster circuit at the first DC source two ends;
The first electric capacity, the second electric capacity and the 3rd electric capacity of connecting successively; The common port of described the second electric capacity and the 3rd electric capacity links to each other with the first output of described booster circuit and the negative pole of the first DC source respectively; The end that described the first electric capacity does not connect the second electric capacity links to each other with the second output of described booster circuit; The common port of described the first electric capacity and the second electric capacity links to each other with the positive pole of the first DC source;
The first diode that negative electrode links to each other with the common port of described the first electric capacity and the second electric capacity, the anodic bonding of described the first diode has the input of the first switching tube;
The second diode that anode links to each other with the common port of described the first electric capacity and the second electric capacity, the negative electrode of described the second diode is connected with the input of second switch pipe;
The 3rd diode that anode links to each other with the common port of described the second electric capacity and the 3rd electric capacity, the negative electrode of described the 3rd diode is connected with the input of the 3rd switching tube;
The 4th diode that negative electrode links to each other with the common port of described the second electric capacity and the 3rd electric capacity, the anodic bonding of described the 4th diode has the input of the 4th switching tube;
The output of described the first switching tube links to each other with the output of the 4th switching tube;
The output of described second switch pipe links to each other with the output of the 3rd switching tube;
The 5th switching tube that output links to each other with the second output of described booster circuit, the input of described the 5th switching tube is connected with the output of the 6th switching tube, and the input of described the 6th switching tube links to each other with the negative pole of the second DC source;
The 7th switching tube that output links to each other with the output of the 5th switching tube, the input of described the 7th switching tube links to each other with the output of described the 3rd switching tube;
The 8th switching tube that input links to each other with the negative pole of the second DC source, the output of described the 8th switching tube links to each other with the output of described four switching tubes;
The 5th diode that negative electrode links to each other with the second output of described booster circuit, the anode of described the 5th diode links to each other with the output of described the 4th switching tube;
The 6th diode that anode links to each other with the negative pole of the second DC source, the negative electrode of described the 6th diode links to each other with the output of described the 3rd switching tube.
2. single-phase seven electrical level inverters according to claim 1 is characterized in that, described diode is silicon carbide diode or fast recovery diode or supper-fast recovery diode.
3. single-phase seven electrical level inverters according to claim 1 is characterized in that, filtering and the net unit of single-phase seven electrical level inverters comprise: the first inductance, the second inductance and filter capacitor, wherein:
The filter capacitor first end links to each other with the 5th switching tube input;
The first inductance and the second inductance are in series;
The common port of the first inductance and the second inductance links to each other with the second end of filter capacitor, and the end that the first inductance does not link to each other with the second inductance links to each other with the output of the 3rd switching tube; The end that the second inductance does not link to each other with the first inductance links to each other with the output of the 4th switching tube.
4. described single-phase seven electrical level inverters of any one according to claim 1-3, it is characterized in that, the control end of described the first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube and the 8th switching tube is connected with control chip, and described control chip is controlled described single-phase seven electrical level inverters and realized eight kinds of meritorious operation modes:
When being in first mode, described control chip is controlled described the 7th switching tube and the 6th switching tube conducting, and the rest switch pipe is cut-off;
When being in second mode, described control chip is controlled described second switch pipe and the 6th switching tube conducting, and the rest switch pipe is cut-off;
When being in the 3rd mode, described control chip is controlled described the 3rd switching tube and the 6th switching tube conducting, and the rest switch pipe is cut-off;
When being in the 4th mode, described control chip is controlled described the 6th switching tube conducting, and the rest switch pipe is cut-off;
When being in the 5th mode, described control chip is controlled described the 8th switching tube and the 5th switching tube conducting, and the rest switch pipe is cut-off;
When being in the 6th mode, described control chip is controlled described the 4th switching tube and the 5th switching tube conducting, and the rest switch pipe is cut-off;
When being in the 7th mode, described control chip is controlled described the first switching tube and the 5th switching tube conducting, and the rest switch pipe is cut-off;
When being in the 8th mode, described control chip is controlled described the 5th switching tube conducting, and the rest switch pipe is cut-off.
5. single-phase seven electrical level inverters according to claim 4 is characterized in that, described control chip is controlled described single-phase seven electrical level inverters and realized eight kinds of idle operation modes:
When being in the 9th mode, described control chip is controlled described the 8th switching tube and the 6th switching tube conducting, and the rest switch pipe is cut-off;
When being in the tenth mode, described control chip is controlled described the 4th switching tube and the 6th switching tube conducting, and the rest switch pipe is cut-off;
When being in 11 mode, described control chip is controlled described the first switching tube and the 6th switching tube conducting, and the rest switch pipe is cut-off;
When being in 12 mode, described control chip is controlled described the 6th switching tube conducting, and the rest switch pipe is cut-off;
When being in 13 mode, described control chip is controlled described the 7th switching tube and the 5th switching tube conducting, and the rest switch pipe is cut-off;
When being in 14 mode, described control chip is controlled described second switch pipe and the 5th switching tube conducting, and the rest switch pipe is cut-off;
When being in 15 mode, described control chip is controlled described the 3rd switching tube and the 5th switching tube conducting, and the rest switch pipe is cut-off;
When being in 16 mode, described control chip is controlled described the 5th switching tube conducting, and the rest switch pipe is cut-off.
6. single-phase seven electrical level inverters according to claim 1 is characterized in that, filtering and the net unit of single-phase seven electrical level inverters comprise: the first inductance, the second inductance, filter capacitor and isolating transformer, wherein:
The first end of isolating transformer primary coil links to each other with the 5th switching tube input;
The first inductance and the second inductance are in series;
The common port of the first inductance and the second inductance links to each other with the second end of isolating transformer primary coil, and the end that the first inductance does not link to each other with the second inductance links to each other with the output of the 3rd switching tube; The end that the second inductance does not link to each other with the first inductance links to each other with the output of the 4th switching tube;
Two terminals of filter capacitor link to each other with two terminals of isolating transformer secondary coil respectively.
7. single-phase seven level inverse conversion unit is characterized in that, are applied to single-phase seven electrical level inverters, comprising:
The first electric capacity, the second electric capacity and the 3rd electric capacity of connecting successively; The common port of described the second electric capacity and the 3rd electric capacity links to each other with the negative pole of described the first DC source and the positive pole of the second DC source respectively; The common port of described the first electric capacity and the second electric capacity links to each other with the positive pole of the first DC source;
The first diode that negative electrode links to each other with the common port of described the first electric capacity and the second electric capacity, the anodic bonding of described the first diode has the input of the first switching tube;
The second diode that anode links to each other with the common port of described the first electric capacity and the second electric capacity, the negative electrode of described the second diode is connected with the input of second switch pipe;
The 3rd diode that anode links to each other with the common port of described the second electric capacity and the 3rd electric capacity, the negative electrode of described the 3rd diode is connected with the input of the 3rd switching tube;
The 4th diode that negative electrode links to each other with the common port of described the second electric capacity and the 3rd electric capacity, the anodic bonding of described the 4th diode has the input of the 4th switching tube;
The output of described the first switching tube links to each other with the output of the 4th switching tube;
The output of described second switch pipe links to each other with the output of the 3rd switching tube;
The 5th switching tube that output links to each other with the end that described the first electric capacity does not link to each other with the second electric capacity, the input of described the 5th switching tube is connected with the output of the 6th switching tube, and the input of described the 6th switching tube links to each other with the negative pole of the second DC source;
The 7th switching tube that output links to each other with the output of the 5th switching tube, the input of described the 7th switching tube links to each other with the output of described the 3rd switching tube;
The 8th switching tube that input links to each other with the negative pole of the second DC source, the output of described the 8th switching tube links to each other with the output of described four switching tubes;
The 5th diode that negative electrode links to each other with described the 5th switching tube output, the anode of described the 5th diode links to each other with the output of described the 4th switching tube;
The 6th diode that anode links to each other with the negative pole of the second DC source, the negative electrode of described the 6th diode links to each other with the output of described the 3rd switching tube.
8. single-phase seven level inverse conversion unit according to claim 7 is characterized in that, filtering and the net unit of single-phase seven level inverse conversion unit comprise: the first inductance, the second inductance and filter capacitor, wherein:
The filter capacitor first end links to each other with the 5th switching tube input;
The first inductance and the second inductance are in series;
The common port of the first inductance and the second inductance links to each other with the second end of filter capacitor, and the end that the first inductance does not link to each other with the second inductance links to each other with the output of the 3rd switching tube; The end that the second inductance does not link to each other with the first inductance links to each other with the output of the 4th switching tube.
9. single-phase seven level inverse conversion unit according to claim 7 is characterized in that, filtering and the net unit of single-phase seven level inverse conversion unit comprise: the first inductance, the second inductance, filter capacitor and isolating transformer, wherein:
The first end of isolating transformer primary coil links to each other with the 5th switching tube input;
The first inductance and the second inductance are in series;
The common port of the first inductance and the second inductance links to each other with the second end of filter isolating transformer primary coil, and the end that the first inductance does not link to each other with the second inductance links to each other with the output of the 3rd switching tube; The end that the second inductance does not link to each other with the first inductance links to each other with the output of the 4th switching tube;
Two terminals of filter capacitor link to each other with two terminals of isolating transformer secondary coil respectively.
10. single-phase seven level inverse conversion unit according to claim 7 is characterized in that, single-phase seven level inverse conversion unit also comprise:
Input is connected in parallel on the booster circuit at the first DC source two ends;
The first output of described booster circuit links to each other with the common port of described the second electric capacity and the 3rd electric capacity;
The second output of booster circuit is not connected the second electric capacity with the first electric capacity a end links to each other.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104212058A CN102882412A (en) | 2012-10-29 | 2012-10-29 | Single-phase seven-level inverter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104212058A CN102882412A (en) | 2012-10-29 | 2012-10-29 | Single-phase seven-level inverter |
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| CN103633867A (en) * | 2013-10-17 | 2014-03-12 | 宁波绿凯节能科技有限公司 | Seven-level single-phase inverter circuit |
| CN103684015A (en) * | 2013-12-30 | 2014-03-26 | 阳光电源股份有限公司 | Seven-level inverter |
| CN108616224A (en) * | 2018-05-25 | 2018-10-02 | 西安理工大学 | A kind of single-phase seven electrical level inverter of booster type |
| CN111224574A (en) * | 2020-02-13 | 2020-06-02 | 广东工业大学 | Multi-level conversion system |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103633867A (en) * | 2013-10-17 | 2014-03-12 | 宁波绿凯节能科技有限公司 | Seven-level single-phase inverter circuit |
| CN103684015A (en) * | 2013-12-30 | 2014-03-26 | 阳光电源股份有限公司 | Seven-level inverter |
| CN103684015B (en) * | 2013-12-30 | 2016-03-30 | 阳光电源股份有限公司 | A kind of seven electrical level inverters |
| CN108616224A (en) * | 2018-05-25 | 2018-10-02 | 西安理工大学 | A kind of single-phase seven electrical level inverter of booster type |
| CN108616224B (en) * | 2018-05-25 | 2020-06-26 | 西安理工大学 | Boost type single-phase seven-level inverter |
| CN111224574A (en) * | 2020-02-13 | 2020-06-02 | 广东工业大学 | Multi-level conversion system |
| CN111224574B (en) * | 2020-02-13 | 2021-08-03 | 广东工业大学 | Multi-level conversion system |
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