CN102843128A - Digital phase-locked loop operated based on fraction input and output phases - Google Patents
Digital phase-locked loop operated based on fraction input and output phases Download PDFInfo
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Abstract
The invention relates to a digital phase-locked loop operated based on fraction input and output phases. On one hand, the digital phase locked loop (DPLL) is operated based on fractional parts of the input and output phases, the DPLL accumulates at least one input signal to obtain an input phase, the DPLL (for instance) uses a time / digital converter (TDC) to determine a fractional part of an output phase based on the phase difference between an oscillator signal from an oscillator and a reference signal, the DPLL determines phase error based on the fractional part of the input phase and the fractional part of the output phase, and then the DPLL generates a control signal used for the oscillator based on the phase error. On the other hand, the DPLL comprises a synthetic accumulator, and the synthetic accumulator is used to determine a rough output phase based on the reference signal by tracking the number of cycles of the oscillator signal.
Description
The relevant information of dividing an application
This case is to divide an application.Female case of this division be that January 12, application number in 2009 are 200880118247.6 the applying date, denomination of invention is the application for a patent for invention case of " digital phase-locked loop of operating based on mark input and output phase place ".
Technical field
The present invention relates generally to electronic component, and more particularly, relates to digital phase-locked loop.
Background technology
Phase-locked loop (PLL) is even more important for the integral part of many electronic circuits and in telecommunication circuit.For instance, digital circuit uses clock signal to come trigger synchronous circuits (for example, trigger).Reflector and receiver are respectively applied for frequency up-converted and frequency down-converts with local oscillator (LO) signal.The wireless device (for example, cellular phone) that is used for wireless communication system is used for clock signal digital circuit and the LO signal is used for reflector and receiver usually.Come clocking and LO signal with oscillator, and the frequency of coming control clock signal and LO signal with PLL usually.
PLL generally includes in order to adjustment from the frequency of the oscillator signal of oscillator and/or the various circuit blocks of phase place.These circuit blocks may consume a large amount of relatively power, and this maybe be for unacceptable for the mancarried device of for example cellular phone.Therefore, need under the situation of any sacrifice in performance not, reduce the technology of the power consumption of PLL in this technology.
Summary of the invention
Digital PLL (DPLL) with superperformance and lower power consumption is described among this paper.DPLL has the circuit block of implementing with digital form but not PLL with analog circuit.Numeral enforcement can provide some advantages, for example lower cost, less circuit area etc.
In one aspect, DPLL can operate based on the fractional part of input and output phase place.DPLL can add up at least one input signal that can comprise modulation signal to obtain input phase.DPLL can (for example) service time/digital quantizer (TDC) based on the fractional part of confirming output phase from the oscillator signal and the phase difference between the reference signal of oscillator.DPLL then can confirm phase error based on the fractional part of said input phase and the fractional part of said output phase.Fractional part can have the scope of the one-period of said oscillator signal.In a kind of design, DPLL can confirm the phase difference between the fractional part of fractional part and said input phase of said output phase.DPLL then can be with predetermined value (for example; A cycle oscillator) adds said phase difference or deduct said predetermined value (if desired) to from said phase difference; So that gained phase error (1/2nd cycle oscillators for example, bearing are to 1/2nd positive cycle oscillators) in preset range.DPLL can produce the control signal that is used for said oscillator based on said phase error.
In another aspect, DPLL can comprise synthetic accumulator (synthesized accumulator) and TDC.Said synthetic accumulator can be through following the trail of oscillator signal the number in cycle confirm rough output phase.Can upgrade said synthetic accumulator based on reference signal with frequency lower than the frequency of said oscillator signal.Said TDC can confirm meticulous output phase based on the phase difference between said oscillator signal and the said reference signal.DPLL can produce the control signal that is used for oscillator based on said rough output phase, said meticulous output phase and said input phase.
Various aspects of the present invention and characteristic are below described in more detail.
Description of drawings
Fig. 1 shows the block diagram of DPLL.
Fig. 2 shows the chart of the output of TDC to input.
Fig. 3 shows the block diagram of the DPLL that operates based on mark input and output phase place.
Fig. 4 shows the operation of synthetic accumulator.
Fig. 5 shows the block diagram of the DPLL with synthetic accumulator.
Fig. 6 shows the block diagram of the phase detectors with synthetic accumulator.
Fig. 7 shows the sketch map of TDC.
Fig. 8 shows the block diagram of another DPLL with synthetic accumulator.
Fig. 9 shows the block diagram of communicator.
Figure 10 shows the process that is used for control generator.
Figure 11 shows another process that is used for control generator.
Embodiment
Fig. 1 shows the block diagram of the design of DPLL 100.In DPLL 100, summer 110 receives modulation signal M (t) and to its summation, said modulation signal M (t) has quiescent value for the centre frequency of the channel that is used to communicate by letter.The input accumulator 112 add up summer 110 output and input phase P is provided (t).Said adding up becomes phase place with frequency inverted in essence.Trigger input accumulator 112 through reference signal, said reference signal can have fixed frequency f
RefAlso upgrade various circuit blocks and signal in the DPLL 100, and t is the index of said reference signal with said reference signal.
Radio frequency (RF) accumulator 122 increases progressively one to each cycle oscillator, and cycle oscillator is the one-period from the oscillator signal of controlled oscillator 118.Latch 124 latchs the output of RF accumulator 122 and rough/integer output phase A (t) is provided when being triggered by said reference signal.TDC 130 receives said oscillator signal and said reference signal; When triggering, confirm the phase place of said oscillator signal by said reference signal; And TDC output F (t) is provided, and the meticulous/fractional phase between TDC output F (t) said oscillator signal of indication and the said reference signal is poor.TDC 130 implements to be used for the fractional phase transducer of DPLL 100.Summer 126 receives that rough output phase A (t) export F (t) with TDC and to its summation, and feedback phase Z is provided (t), and feedback phase Z (t) is the estimation to output phase B (t).
Can cycle oscillator be that unit provides input phase P (t), output phase B (t) and feedback phase Z (t).In the design shown in Fig. 1, the feedback path of DPLL 100 comprises: (i) the RF accumulator 122, and it is in order to measure the rough output phase that provides with the integer number of cycle oscillator; And (ii) TDC 130, the meticulous output phase that it provides in order to the part of measuring by a cycle oscillator.The total output phase B of measurement in a closed series (t) of RF accumulator 122 and TDC 130, total output phase B (t) comprise from rough/integer part of RF accumulator 122 with from meticulous/fractional part of TDC 130.In the description in this article, term " meticulous " exchanges with " mark " and uses, and term " roughly " also exchanges use with " integer ".Deduct feedback phase Z (t) (it is the estimation to output phase) to obtain to be used for the phase error of ring wave filter 116 from said input phase.
Can operate all square frames except that RF accumulator 122 among the DPLL 100 based on said reference signal.RF accumulator 122 is operated much higher times of the comparable said reference signal of the frequency of oscillator signal based on oscillator signal.Therefore, RF accumulator 122 can account for the major part (for example, about 50%) of the total power consumption of DPLL 100.Therefore, can under the situation that RF accumulator 122 cuts out, operate DPLL 100 so that save the power of battery.
In a reference cycle (it is the one-period of reference signal), can be with total output phase θ
TotalBe given:
θ
Total=2 π f
Osc/ f
RefRadian.Equality (1)
Can cycle oscillator be that unit provides total output phase and can be divided into integer part θ
IntWith fractional part θ
FracThe integer number that can cycle oscillator or the integral multiple of 2 π radians provide integer part θ
IntCan or in the scope of 0 to 2 π radian, provide fractional part θ by the part of a cycle oscillator
FracCan provide integer part θ as follows
IntWith fractional part θ
Frac:
θ
Frac=θ
Total-θ
Int, equality (3)
Wherein rounding operation accords with (floor operator) under
expression.
Fig. 2 shows the chart of the output of TDC 130 to input.Trunnion axis is showed output phase B (t), and it is the input to TDC 130.Vertical axis is showed TDC output F (t).For trunnion axis and vertical axis, a cycle oscillator equals 2 π.As shown in Figure 2, TDC 130 has discontinuous output to input.TDC output F (t) equals output phase B (t) at 0 to 2 π, then when B (t)=2 π, raps around to 0, then increases linearly with B (t) to 4 π at 2 π, then when B (t)=4 π, raps around to 0, by that analogy.
For DPLL is suitably operated, should solve the discontinuity of TDC output.A mode that solves these discontinuities is to use RF accumulator 122 to follow the trail of the number of times that output phase B (t) surpasses 2 π.Then can add the output (being the integral multiple of 2 π) of RF accumulator 122 to TDC output, so that opereating specification is limited to 0 to 2 π, thus the discontinuity of avoiding.Yet RF accumulator 122 can consume a lot of electric currents because of its high frequency of operation.
As shown in Figure 2, TDC output is whenever jumped at a distance from 2 π, but is continuous in the 2 π scopes between phase step in succession.If the rate of change of output phase is limited, then the phase step of TDC output can be identified when it occurs and considered and reach.For instance, can not modulate DPLL 100, so that M (t)=0, and P (t) does not have fractional part for all t.Initial condition can be F (0)=0 and A (0)=P (0), so that E (0)=0.Because DPLL is through locking, so control signal S (t) can have steady state value.If input phase has increase (for example, having increased by 0.1 radian) slightly, then TDC 130 will measure this phase place and the signal that affords redress (for example, E (t)=-0.1 radian).Yet if output phase B (t) slightly reduces (for example, having reduced-0.1 radian), TDC 130 will export big value (for example, 2 π-0.1 radian).So the cycle period that will make the phase error difference, this possibly influence the performance of DPLL unfriendly.
Yet, if the rate of change of output phase is limited, can be with any big variation of TDC output in a reference cycle owing to phase step.Then can a cycle oscillator be added to TDC output or deduct a cycle oscillator to obtain correct phase value from TDC output.In above instance, can with TDC output be the big value of 2 π-0.1 radian owing to phase step, can from then on be worth and deduct 2 π, and can provide-0.1 radian as correct TDC output valve.
On the one hand, under the situation of not using the RF accumulator, based on operating DPLL from the mark output phase of TDC and the fractional part of input phase.In each reference cycle, can deduct said TDC output from the fractional part of input phase, as follows:
D (t)=P
f(t)-and F (t), equality (4)
P wherein
f(t) be the fractional part of input phase and in the scope of 0 to 2 π, and
D (t) is poor between fractional part and the TDC output of input phase, and TDC is output as the fractional part of output phase.
The rate of change of rate of change and output phase that can suppose input phase is limited, and can suppose phase error in each reference cycle at-π in the scope of π.So can confirm phase error as follows:
Equality (5) is showed D (t) and threshold value+π and-design that π compares.Also can D (t) be compared with other threshold value.
Such as in the equality (5) displaying, if phase difference supposes then that greater than π or less than-π phase step takes place.In the case, can 2 π be added to said phase difference or deduct 2 π from said phase difference, so that the gained phase error approaches zero.
Fig. 3 only shows the block diagram of the design of the DPLL 300 that operates based on the fractional part of input phase and output phase.In DPLL 300, summer 310 is operated as 112 descriptions of summer 110 and input accumulator of Fig. 1 like preceding text with input accumulator 312, and input phase P is provided (t).Unit 313 receives said input phase and fractional part P is provided
f(t).Oscillator signal and reference signal that TDC 330 receives from controlled oscillator 318, and TDC output F (t) is provided, the meticulous/fractional phase between TDC output F (t) said oscillator signal of indication and the said reference signal is poor.Summer 314 is from mark input phase P
f(t) deduct TDC output F (t), and phase difference D is provided (t).Unit 315 receives said phase difference, and definite phase error E (t) (for example, shown in equality (5)).316 pairs of said phase error filtering of ring wave filter, and be provided for the control signal S (t) of oscillator 318.
In a kind of design, can use the RF accumulator that oscillator 318 is locked onto modulation signal at first.Lock detector (not showing among Fig. 3) can (for example) confirm through the value of observing said phase error whether DPLL 300 is locked.After DPLL 300 has been locked, the RF accumulator of can stopping using, and can only use the fractional part of input phase and output phase to operate said DPLL.
In another aspect, can use synthetic accumulator to confirm roughly/the integer output phase.Synthetic accumulator can be based on said reference signal but not said oscillator signal and operating, and can therefore consume the power of much less than RF accumulator.
Fig. 4 explanation has the operation of the DPLL of synthetic accumulator.In the instance shown in Fig. 4, the frequency of oscillator signal is 3.25 times of frequency of reference signal, and can provide 3.25 frequency control word (FCW) as the channel frequency among Fig. 1.For the sake of simplicity, suppose that the rising edge based on oscillator signal and reference signal locks and trigger said DPLL.
Oscillator signal is showed among first row at place, Fig. 4 top, and reference signal is showed among second row.The output of RF accumulator is showed among the 3rd row.The RF accumulator increases progressively one at each rising edge place of oscillator signal, and therefore when cycle oscillator occurs, follows the trail of cycle oscillator.Latch the output of RF accumulator at each rising edge place of reference signal, and each latched value is showed in the 3rd row's the circle.Number round down through with cycle oscillator obtains each latched value to immediate integer value.For instance, in Fig. 4, have 3.25 cycle oscillators between first rising edge of reference signal and second rising edge, and the RF accumulator is output as 3, it equals through 3.25 of round down.In instance shown in Figure 4, there are 3.25 cycle oscillators in per reference cycle, and latched value is 0,3,6,9,13 etc.
The output of desirable TDC is showed among the 4th row.Said TDC measures the fractional part of the output phase of being ignored by the round down function.Said fractional part equals poor between the immediate rising edge in front of rising edge and oscillator signal of reference signal.For each rising edge of reference signal, said TDC is provided at the fractional value between 0 and 1.0.As shown in Figure 4, TDC is output as periodically.Can be through obtaining feedback phase in the Calais mutually with rough/integer part from meticulous/fractional part of TDC from the RF accumulator.
Being showed among the 5th row of the cycle oscillator in per reference cycle through the number that rounds off (it also is known as integer increments N (t)).For each rising edge of reference signal, N (t) equals poor between current latched value and the previous latched value.In the instance shown in Fig. 4, N (t) is 3,3,3,4,3,3,3,4,3 etc. sequence.N (t) has mean value 3.25 and exports in the same manner for periodic with TDC.In addition, after DPLL was locked, N (t) only had two possible integer values, and it is 3 and 4 in the instance shown in Fig. 4.Even during the DPLL that under the situation of narrow band frequency modulation, uses, it still is what set up that this between two integer values switches.For between three integer values, switching, frequency modulation(FM) need be greater than reference frequency f
Ref, so that an extra full cycle oscillator can be engaged in the reference cycle.Usually, the peak value modulating frequency is the part of reference frequency.For instance, the peak value modulating frequency can be several MHz, and reference frequency can be tens MHz.In the case, N (t) only has two possible integer values.
If N (t) can only adopt two possible integer values, then can not use at oscillator frequency f
OscConfirm N (t) under the situation of the RF accumulator of following operation.Even, can realize this through utilizing the fact that still only there is a small amount of variation in per reference cycle of phase error when modulating at DPLL.For instance; Crest frequency modulation can be about 3MHz and is four minutes in DPLL output place for the low strap EDGE with 4GHz oscillator; Said reference frequency can be about 57MHz, and the variation of the maximum of per reference cycle input phase can be about 0.3 radian or is about 5% of the reference cycle.Therefore, 2 π phase steps are not covered in said modulation, and the operation of DPLL does not change in essence.
Can under the situation of not using the RF accumulator, confirm N (t) as follows.For each reference cycle or update time interval t, can confirm the right value of N (t) through two hypothesis of assessment N (t).First hypothesis a is to be two smallers' in the value situation for N (t), and said smaller is expressed as N
LAnd for the instance shown in Fig. 4, equal 3.Second hypothesis b is to be the situation of two the greater in the value for N (t), and said the greater is expressed as N
HAnd for the instance shown in Fig. 4, equal 4.Can select to provide the hypothesis of less phase error value, and be used for the N of correct hypothesis
LOr N
HCan be used to the register of updated stored to the operation counting of the number of cycle oscillator.The rough output phase C (t) that this register provides the integer number with cycle oscillator to provide.
Can assess said two hypothesis a and b as follows.After DPLL is locked, can (for example) come the said register of initialization based on the integer part of input phase P (t).In the instance shown in Fig. 4, initialization of register is arrived zero.At second rising edge place of reference signal, suppose that a has the output phase Z of hypothesis
a(1)=and 3+0+0.25=3.25, wherein 3 for being used to suppose the N of a
LValue, 0 is the rough output phase C (1) from said register, and 0.25 is the TDC output valve.Suppose that b has the output phase Z of hypothesis
b(1)=and 4+0+0.25=4.25, wherein 4 for being used to suppose the N of b
HValue.The output phase Z that will be used for the said hypothesis of said two hypothesis
a(1) and Z
b(1) compares with input phase P (1)=3.25.Because Z
a(1) compares Z
b(1) more approaches P (1), so hypothesis a is correct hypothesis.Then (it is the N that is used for correct hypothesis a by 3
LValue) upgrade register, and said register-stored is 3 rough output phase.
At the 3rd rising edge place of reference signal, suppose that a has the output phase Z of hypothesis
a(2)=and 3+3+0.5=6.5, wherein first is 3 for being used to suppose the N of a
LValue, second 3 is the rough output phase C (2) from said register, and 0.5 is the TDC output valve.Suppose that b has the output phase Z of hypothesis
b(2)=and 4+3+0.5=7.5, wherein 4 for being used to suppose the N of b
HValue.The output phase Z that will be used for the said hypothesis of said two hypothesis
a(2) and Z
b(2) compare with input phase P (2)=6.5.Because Z
a(2) compare Z
b(2) more approach P (2), so hypothesis a is correct hypothesis.Then (it is the N that is used for correct hypothesis a by 3
LValue) upgrade said register, and said register-stored is 6 rough output phase.Can repeat identical processing to each subsequent reference cycle.
In general, can confirm to be used for two the possible integer values of N (t) as follows:
N wherein
LBe the smaller in two possible integer values of N (t),
N
HBe the greater in two possible integer values of N (t), and
Rounding operation symbol in
expression.
Can confirm to be used to suppose the output phase of the hypothesis of a and b as follows:
Z
a(t)=N
L+ C (t)+F (t), and equality (7)
Z
b(t)=N
H+ C (t)+F (t), equality (8)
Wherein C (t) is the rough output phase in reference cycle t,
Z
a(t) be the output phase of being used in reference cycle t supposing the hypothesis of a, and
Z
b(t) be the output phase of being used in reference cycle t supposing the hypothesis of b.
Can confirm to be used to suppose the phase error of the hypothesis of a and b as follows:
E
a(t)=P (t)-Z
aAnd equality (9) (t),
E
b(t)=P (t)-Z
b(t), equality (10)
E wherein
a(t) be the phase error of being used in reference cycle t supposing the hypothesis of a, and
E
b(t) be the phase error of being used in reference cycle t supposing the hypothesis of b.
Can upgrade rough output phase as follows:
Can confirm the phase error E (t) in reference cycle t as follows:
Can the phase error from equality (12) be provided to the ring wave filter among the DPLL.
, select between two possible integer values for the N in the given reference cycle (t) to shown in (12) like equality (6), can assess said two hypothesis a and b.The hypothesis that can select to have the output phase of the hypothesis that more approaches input phase or have less phase error value equivalently.
Fig. 5 shows the block diagram of the design of the DPLL 500 with synthetic accumulator.In DPLL 500, summer 510 is operated as 112 descriptions of summer 110 and input accumulator of Fig. 1 like preceding text with input accumulator 512, and input phase P is provided (t).
Oscillator signal and reference signal that TDC 530 receives from controlled oscillator 518, and TDC output F (t), the phase difference between TDC output F (t) said oscillator signal of indication and the said reference signal are provided.Phase detectors 520 receive said oscillator signal, said TDC output and said input phase and produce the first phase error E
1(t).Phase detectors 520 comprise RF accumulator 522, latch 524 and summer 526, and it is operated as RF accumulator 122, latch 124 and summer 114 among Fig. 1 and 126 descriptions like preceding text.Can launch or inactive phase detectors 520 through mode signal.Phase detectors 540 receive channel frequencies, said reference signal, said TDC output and said input phase, and produce the second phase error E
2(t).Phase detectors 540 comprise synthetic accumulator and can be as mentioned below as implement.Can launch or inactive phase detectors 540 through mode signal.Can launch phase detectors 520 or 540 at any given time, and another phase detectors of can stopping using are to save the power of battery.
Multiplexer (Mux) 514 receives respectively two phase error E from phase detectors 520 and 540
1(t) and E
2And phase error E is provided (t) (t) and mode signal.Multiplexer 514 provides the first phase error E when launching phase detectors 520
1(t), and the second phase error E is provided when launching phase detectors 540 as phase error E (t)
2(t) as phase error E (t).516 pairs of phase error E (t) filtering of ring wave filter and be provided for the control signal S (t) of oscillator 518.
In a kind of design, can launch phase detectors 520 at first and it is used for oscillator 518 is locked onto modulation signal.After DPLL 500 has been locked, the phase detectors 520 of can stopping using, and can launch phase detectors 540.The first phase error E that lock detector 550 receives from phase detectors 520
1(t) and definite DPLL 500 whether be locked.Can be through the observation first phase error E
1(t) value is realized this and is confirmed the first phase error E
1(t) value the time can be big at first without locking and can be during through locking little at DPLL 500 at DPLL 500.Lock detector 550 provides lock indicator, and lock indicator the time can be set to a logical value (for example, ' 1') or be set to another logical value (for example, ' 0') during without locking at DPLL through locking at DPLL.Mode selector 552 receives said lock indicator and possibly receive other input of not showing among Fig. 5, and the signal that supplies a pattern.For instance, mode selector 552 can be at DPLL once locking, or in time after a while, just launches phase detectors 540 and inactive phase detectors 520.Can launch phase detectors 520 and 540 simultaneously in regular period before cutting off RF accumulator 522.When detecting locking loss (for example, owing to the serious interference to DPLL 500), or because of any other reason, mode selector 552 just also can reactivate phase detectors 520.Lock detector 550 and mode selector 552 also can be used among Fig. 3 DPLL 300 with DPLL during without locking the output with RF accumulator (displaying among Fig. 3) produce phase error.
The block diagram of the design of the phase detectors 540 in Fig. 6 exploded view 5.In this design, phase detectors 540 comprise synthetic accumulator 610, hypothesis evaluation unit 620 and the unit 630 that rounds off.But two possible integer values of round off unit 630 receive channel frequencies and definite N (t), it is N
LAnd N
HPerhaps, unit 630 can receive the rough output phase A (t) from the latch among Fig. 5 524.When phase detectors 520 through launching and DPLL 500 during through locking, rough output phase A (t) should be at N
LWith N
HBetween switch.Therefore, after DPLL 500 had been locked, N can be confirmed based on the value of rough output phase A (t) in unit 630
LAnd N
H
Synthetic accumulator 610 is followed the trail of the number of cycle oscillators, but based on reference signal but not oscillator signal operate, this can significantly reduce the power consumption of DPLL 500.Synthetic accumulator 610 comprises register 612, summer 614 and multiplexer 616.Register 612 is stored current rough output phase C (t) with the integer number of cycle oscillator.Multiplexer 616 receives N
LAnd N
HAnd the selection signal of indicating the hypothesis which is assumed to be correctly/wins.In each reference cycle, multiplexer 616 provides N when being correct hypothesis at hypothesis a
LAnd N is provided when being correct hypothesis at hypothesis b
H614 couples of current rough output phase C (t) from register 612 of summer sue for peace with the output of multiplexer 616 and the rough output phase C (t+1) through upgrading are provided, and rough output phase C (t+1) is stored in the register 612.Register 612, summer 614 and multiplexer 616 are implemented equality (11).
Unit 620 is assessed two hypothesis a and b and phase error E is provided in each reference cycle
2(t) and the selection signal of the hypothesis of indicating correct.In unit 620, summer 622a receives rough output phase C (t), TDC output F (t) and the N from register 612
LAnd, and be provided for supposing the output phase Z of the hypothesis of a to its summation
a(t) (shown in equality (7)).Summer 624a deducts the output phase Z of hypothesis from input phase P (t)
a(t) and be provided for supposing the phase error E of the hypothesis of a
a(t) (shown in equality (9)).Similarly, summer 622b receives rough output phase C (t), TDC output F (t) and N
HAnd, and be provided for supposing the output phase Z of the hypothesis of b to its summation
b(t) (shown in equality (8)).Summer 624b deducts the output phase Z of hypothesis from input phase P (t)
b(t) and be provided for supposing the phase error E of the hypothesis of b
b(t) (shown in equality (10)).
Selector 626 receives the phase error E of the hypothesis that is used for said two hypothesis
a(t) and E
b(t) and confirm the less value in the phase error of said two hypothesis.Selector 626 provides the phase error of the hypothesis with less value as the phase error E from phase detectors 540
2(t) (shown in equality (12)).Selector 626 also provides the selection signal, and the indication of said selection signal produces the correct hypothesis of the phase error value of said less hypothesis.
Fig. 4 and Fig. 6 show the design with RF accumulator output round down (for example, from 3.25 round downs to 3, from 6.5 round downs to 6 etc.).In the case, for each hypothesis, TDC is exported F (t) add rough output phase C (t) to.In another design, with RF accumulator output round-up (for example, from 3.25 round-ups to 4, from 6.5 round-ups to 7 etc.).In the case, for each hypothesis, deduct TDC output F (t) (not showing Fig. 4 or Fig. 6) from rough output phase C (t).In general, can assess said hypothesis with the consistent mode of mode of upgrading said synthetic accumulator.
Fig. 6 shows for during the normal running of DPLL 500, having two integer value N
LAnd N
HSituation, the example design of synthetic accumulator 610 and hypothesis evaluation unit 620.N (t) can have plural possible integer value, for example, and for wide-band modulation or when DPLL 500 powers up for the first time.Can compensate owing to the big difference on the frequency of wide-band modulation through the rough output phase that correction factor is applied to from said synthetic accumulator.In general, can be directed against hypothesis of each possible integer value assessment of N (t).Can select to have the hypothesis of minimum phase error, and can upgrade said synthetic accumulator based on N (t) value of selected hypothesis.
In a kind of design, the synthetic accumulator (for example, as shown in Figure 5) that DPLL is included in the RF accumulator of operating under the oscillator frequency and under reference frequency, operates.To descriptions of Fig. 5 institute, can when the operation beginning, use the RF accumulator like preceding text, and can be locked back use between error-free running period at DPLL and synthesize accumulator.
In another design, DPLL only is included in the synthetic accumulator of operating under the reference frequency.In when beginning operation, that the more possible values that can be directed against N (t) is assessed is more (for example, three, four or maybe be more) supposes.After DPLL is locked, can suppose to less possible N (t) value assessment less (for example, two).Perhaps, operating the hypothesis (for example, two hypothesis) that beginning when and during normal running, can assess similar number.Can select endless belt wide, to realize the desired performance of obtaining with a limited number of possible N (t) value.
The sketch map of the design of the TDC 530 in Fig. 7 exploded view 5.TDC 530 compares the phase place of oscillator signal and the phase place of reference signal, and the detected phase difference of the resolution with a plurality of (B) position is provided.
D type flip flop 712a makes its D input be coupled to the output of delay element 710a to 710z respectively to 712z, and its clock input receives reference signal.712 pairs of each d type flip flops are provided to transducer 714 from the output signal sampling of the delay element that is associated 710 and with the output of being taken a sample.The number of d type flip flop that is in logic high is to the number indication oscillator signal of the d type flip flop that is in logic low and the phase difference between the reference signal.This phase difference has 1/2
BThe resolution of cycle oscillator.Transducer 714 receives from d type flip flop 712a to 2 of 712z
BIndividual output, with these 2
BIndividual output converts B position binary value to, and provides said B position binary value as meticulous/mark output phase.
In general, the resolution of available any number position designs TDC 530.For instance, look desired delay resolution, in integrated circuit (IC) technology available minimum delay etc. and deciding, B can be 8 or bigger.Desired delay resolution is decided by the application of using DPLL 500.
DPLL can be used for various application.For instance, DPLL can be used for frequency synthesizer with produce the oscillator signal under the frequency of being wanted.In the case, can omit modulation signal M (t) or to be set be zero.DPLL also can be used for polarity modulator (polar modulator), quadrature modulator (quadrature modulator), phase-modulator, frequency modulator, demodulator etc.For modulator, the bandwidth of modulation signal can be greater than the closed-loop bandwidth of DPLL.Can design DPLL to adapt to the wide bandwidth of modulation signal.
Fig. 8 shows the block diagram of the design of the DPLL 302 that supports wide-band modulation.DPLL 302 comprises all square frames among the DPLL300 among Fig. 3.DPLL 302 further comprises unit for scaling (scaling unit) 320 and summer 317.
The bandwidth of modulation signal can by use DPLL 302 should be used for confirm and the closed-loop bandwidth of comparable DPLL wide.But the bandwidth of the low pass modulation path among the DPLL 302 be by ring wave filter 316 confirm and relative narrower (for example, less than 100KHz) so that realize desired noise filtering and the gyration attitude.Through coming application of modulation signal M (t) via independent high pass and low pass modulation path, DPLL 302 can the signal bandwidth wideer than the closed-loop bandwidth of DPLL come modulating oscillator 318.
For the sake of simplicity, Fig. 3, Fig. 5 and Fig. 8 show the function square frame of DPLL 300,500 and 502 respectively.For clarity sake, omitted specific detail.For instance, can be inserted in the appropriate position in DPLL 300,302 and 500, so that make suitably time alignment of the interior various signals of these DPLL with postponing.
Fig. 3, Fig. 5 and Fig. 8 show some example design of modulating DPLL.Also available other designs implements to modulate DPLL; In the said design some are described in the 6th of being entitled as of on June 21st, 2005 issue " have forward gain and adjust the phase-locked loop of module (PHASE LOCKED LOOP HAVING A FORWARD GAIN ADAPTATION MODULE) "; In 909, No. 331 United States Patent (USP)s.As the 6th, 909, described in No. 331 United States Patent (USP)s, can confirm to be used for the gain g (t) of high pass modulation path.
For corresponding D PLL among Fig. 3, Fig. 5 and Fig. 8 300,500 and 302, may upset the continuity of output phase to the interference of oscillator.This interference can be derived from the wink property sent out fluctuation in the power supply, from puppet coupling of other ring etc.In general, if the value of the peak value output phase shift in per reference cycle less than 1/2nd reference cycles, then disturbs do not bother, it will be normal conditions.Therefore, these DPLL can provide sane performance.
Fig. 9 shows the block diagram of the design of the communicator 900 that adopts DPLL described herein.Device 900 can be used in radio communication device, cellular phone, PDA(Personal Digital Assistant), handheld apparatus, radio modem, cordless telephone, wireless station, bluetooth (Bluetooth) device etc.Device 900 for example also can be used in code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, quadrature FDMA (OFDMA) system, the WLAN various wireless communication systems such as (WLAN).Device 900 can be supported for example cdma2000, wideband CDMA cdma wireless power technologies such as (W-CDMA).Device 900 also can be supported the for example TDMA radiotechnics of global system for mobile communications (GSM).These various systems and radiotechnics are that institute is known in this technology.
In device 900, data processor 910 can be handled (for example, coding and modulation) data to obtain symbol.Processor 910 also can come said symbol is carried out other processing (for example, spread spectrum, scramble etc.) to obtain the stowed value sample according to the radiotechnics that is used to communicate by letter.Processor 910 can provide the in-phase data signal I (t) of the real part that comprises each stowed value sample and comprise the orthogonal data signal Q (t) of the imaginary part of each stowed value sample.Quadrature/polarity switch (quadrature-to-polar converter) 920 can receive I (t) and Q (t) data-signal; With each stowed value sample from Descartes (Cartesian) Coordinate Conversion to polar coordinates, and envelope signal Y (t) and phase signal θ (t) are provided.
In envelope depth, multiplier 922 can multiply each other envelope signal and gain G, to obtain desired output power levels.Delay cell 924 can programmable amount of delay be provided so that said envelope signal and said phase signal time alignment.The filter response that filter 926 can suit comes delayed envelope signal filtering.D/A (DAC) 928 can be transformed into the envelope signal through filtering simulation and the output envelope signal is provided.The gain that can change power amplifier (PA) 954 through said output envelope signal is to realize Modulation and Amplitude Modulation.
In phase path, differentiator 930 can carry out differential and modulation signal M is provided (t) phase signal θ (t), and modulation signal M (t) can contain the frequency component of I (t) and Q (t) data-signal.DPLL 940 can receive modulation signal M (t) and produce the control signal S (t) that is used for DCO 950.DPLL 300 among available Fig. 3, the DPLL 500 among Fig. 5 or the DPLL 302 among Fig. 8 implement DPLL 940.DCO 950 can produce the signal through phase modulated by said modulation signal modulation.Amplifier (Amp) 952 scalable said signals through phase modulated.PA 954 can further amplify the output of amplifier 952 based on the envelope signal of output and provide through phase modulated and through amplitude-modulated RF output signal.
The data processor 910 in controller/processor 960 controllable devices 900 and the operation of other square frame.Memory 962 can be stored data and the program code that is used for controller/processor 960 and/or other square frame.
Can come the various square frames in the device for carrying out said 900 by digital form.For instance, available one or more digital signal processors (DSP), Reduced Instruction Set Computer (RISC) processor, CPU (CPU) wait and implement processor 910 to filter 926, differentiator 930, DPLL 940 and controller/processor 960.Said digital square frame may be implemented on one or more application-specific integrated circuit (ASIC)s (ASIC) and/or other integrated circuit (IC).Available analog circuit comes the residue square frame in the device for carrying out said 900.The part of DCO 950, amplifier 952 and/or PA 954 may be implemented on one or more RF IC (RFIC), analog IC, the mixed-signal IC etc.
Figure 10 shows the design of the process 1000 that is used for control generator (for example, DCO, VCO etc.).Can add up at least one input signal that can comprise modulation signal to obtain input phase (square frame 1012).Can confirm that the phase difference (for example, using TDC) between oscillator signal and the reference signal is used for the fractional part (square frame 1014) of the output phase of said oscillator signal with acquisition.
Can only confirm phase error (square frame 1016) based on the fractional part of input phase and the said fractional part of said output phase.Said fractional part can have the scope of the one-period of said oscillator signal.For square frame 1016, can confirm the phase difference between the fractional part of fractional part and said input phase of said output phase.If said phase difference then can add said phase difference to predetermined value (for example, cycle oscillator) less than first value (for example, 1/2nd negative cycle oscillators).If said phase difference then can deduct predetermined value from said phase difference greater than second value (for example, 1/2nd positive cycle oscillators).Can be provided at and add or deduct phase difference (if any) after the said predetermined value with as phase error.Can produce the control signal (square frame 1018) that is used for oscillator based on said phase error.
The number (for example, using the RF accumulator) that can pass through the cycle of tracking oscillator signal is confirmed the integer part of said output phase.Without locking the time, can confirm said phase error based on the integer of input phase and the integer and the fractional part of fractional part and output phase.Through locking the time, can only confirm said phase error based on the fractional part of input phase and the fractional part of output phase.
Figure 11 shows the design of the process 1100 that is used for control generator (for example, DCO, VCO etc.).Can confirm rough output phase C (t) (for example, with synthetic accumulator) through tracking from the number in the cycle of the oscillator signal of oscillator based on reference signal, said reference signal has the frequency lower than the frequency of said oscillator signal (square frame 1112).Can confirm meticulous output phase F (t) (for example, using TDC) (square frame 1114) based on the phase difference between said oscillator signal and the said reference signal.Can confirm phase error E (t) (square frame 1116) based on said rough output phase, said meticulous output phase and input phase P (t).Can produce the control signal S (t) (square frame 1118) that is used for oscillator based on said phase error.
For square frame 1112, can be by the first integer value N in each interval update time (for example, each reference cycle)
LOr the second integer value N
HUpgrade rough output phase.Said first integer value and said second integer value can be the continuous integral number value of confirming (for example, shown in equality (6)) based on the frequency of the frequency of oscillator signal and reference signal.Can come to said first integer value and two hypothesis of said second integer value assessment based on said first integer value and said second integer value, rough output phase, meticulous output phase and input phase in the interval in each update time.Can upgrade rough output phase by said first integer value or said second integer value based on result to the assessment of said two hypothesis.For instance, can confirm the output phase Z of first hypothesis based on said first integer value, rough output phase and meticulous output phase
a(t).Can confirm the output phase Z of second hypothesis based on said second integer value, rough output phase and meticulous output phase
b(t).Can (i) more approach under the situation of input phase by said first integer value than the output phase of said second hypothesis or (ii) otherwise upgrade said rough output phase by said second integer value at the output phase of said first hypothesis.
(for example, when operation begins) confirmed rough output phase A (t) based on oscillator signal through the number in the cycle of tracking oscillator signal in first duration.In second duration, (for example, realizing the locking back) and confirming rough output phase C (t) through the number in the cycle of tracking oscillator signal based on reference signal.
Can implement DPLL described herein through various means.For instance, said DPLL may be implemented in hardware, firmware, software or its combination.For the hardware embodiment; Available one or more DSP, digital signal processing device (DSPD), programmable logic device (PLD), field programmable gate array (FPGA), processor, controller, microcontroller, microprocessor, electronic installation, through design with other electronic unit of carrying out function described herein or digital circuit, computer, or it makes up the square frame of implementing in the said DPLL.
Said DPLL also may be implemented on IC, analog IC, digital IC, RFIC, mixed-signal IC, ASIC, printed circuit board (PCB) (PCB), the electronic installation etc.Also available various IC technology is made said DPLL, for example complementary metal oxide semiconductors (CMOS) (CMOS), N-channel MOS (N-MOS), P channel MOS (P-MOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), SiGe (SiGe), GaAs (GaAs) etc.
For firmware and/or software implementation scheme, the code of the function that available execution is described herein (for example, program, function, module, instruction etc.) is implemented the square frame in the DPLL.In general, any computer/processor-readable medium that visibly comprise firmware and/or software code can be used for implementing technology described herein.For instance, firmware and/or software code can be stored in the memory (for example, the memory among Fig. 9 962) and by processor (for example, processor 960) and carry out.Memory may be implemented in the processor or processor outside.Firmware and/or software code also can be stored in the computer/processor-readable medium, for example random-access memory (ram), read-only memory (ROM), nonvolatile RAM (NVRAM), programmable read-only memory (prom), electric erasable PROM (EEPROM), flash memory, floppy disk, compact disk (CD), digital versatile disc (DVD), magnetic or optical data storage device etc.Said code can and can cause said computer/processor to carry out functional particular aspects described herein by one or more computer/processor execution.
The equipment of implementing DPLL described herein can be self-contained unit or can be the part than bigger device.Device can be: (i) independent IC; The (ii) set of one or more IC, it can comprise the memory IC that is used to store data and/or instruction; (iii) for example RF receiver (RFR) or RF emitter/receiver RFIC such as (RTR); (iv) travelling carriage modulator-demodulator ASIC such as (MSM) for example; (v) can be embedded in the module in other device; (vi) receiver, cellular phone, wireless device, hand-held set or mobile unit; (vii) wait.
The those skilled in the art previous description of the present invention is provided so that can make or use the present invention.The those skilled in the art will understand various modifications of the present invention easily, and without departing from the scope of the invention, the General Principle that defines among this paper can be applicable to other variation.Therefore, do not hope that the present invention is limited to instance described herein and design, and will give its widest scope consistent with principle disclosed herein and novel feature.
Claims (10)
1. equipment, it comprises:
Oscillator, it is through being configured to produce oscillator signal; And
Digital phase-locked loop (DPLL); It is through being configured to receive the control signal that is used for said oscillator from the said oscillator signal of said oscillator and reference signal and generation; Said DPLL comprises the synthetic accumulator of confirming rough output phase through the number that is configured to the cycle through writing down said oscillator signal, and said synthetic accumulator is based on the said reference signal with frequency lower than the frequency of said oscillator signal and is updated.
2. equipment according to claim 1; Wherein said synthetic accumulator was upgraded by first integer value or second integer value in the interval in each update time, and said first and second integer values are continuous integral number values of being confirmed by the said frequency of the said frequency of said oscillator signal and said reference signal.
3. equipment according to claim 2; Wherein said DPLL further comprises assessment unit; Said assessment unit through be configured to each update time at interval in assessment said first and second integer-valued two hypothesis, and provide upgrading the indication of said synthetic accumulator by said first or second integer value at interval in each update time based on result to the said assessment of said two hypothesis.
4. equipment according to claim 3; Wherein said DPLL further comprises time/digital quantizer (TDC); Said TDC is through being configured to confirm meticulous output phase based on the phase difference between said oscillator signal and the said reference signal, and wherein said assessment unit is through being configured to assess said two hypothesis based on said first and second integer values, said rough output phase, said meticulous output phase and input phase.
5. equipment according to claim 4; Wherein said assessment unit is through being configured to confirm based on said first integer value, said rough output phase and said meticulous output phase the output phase of first hypothesis; Confirm the output phase of second hypothesis based on said second integer value, said rough output phase and said meticulous output phase, and provide more approaching under the situation of said input phase to upgrade said synthetic accumulator or otherwise to upgrade the indication of said synthetic accumulator by said second integer value than the output phase of said second hypothesis by said first integer value at the output phase of said first hypothesis.
6. equipment according to claim 4; Wherein said assessment unit is through being configured to confirm based on said first integer value, said rough output phase, said meticulous output phase and said input phase the phase error of first hypothesis; Confirm the phase error of second hypothesis based on said second integer value, said rough output phase, said meticulous output phase and said input phase, and provide upgrading said synthetic accumulator or otherwise upgrade the indication of said synthetic accumulator by said second integer value by said first integer value under less than the situation of value of the phase error of said second hypothesis at the value of the phase error of said first hypothesis.
7. equipment according to claim 1, wherein said DPLL further comprises:
Radio frequency (RF) accumulator, it confirms said rough output phase through the number that is configured to the cycle through writing down said oscillator signal, said RF accumulator is based on said oscillator signal and operates.
8. equipment according to claim 7, wherein said RF accumulator was activated in first duration, and in second duration, was deactivated, and wherein said synthetic accumulator was activated in said second duration.
9. equipment according to claim 7; Wherein said DPLL further comprises lock detector; Said lock detector is through being configured to confirm that whether said DPLL is through locking; And wherein the time launch said RF accumulator without locking, and after said DPLL has locked, launch said synthetic accumulator at said DPLL.
10. method, it comprises:
Based on reference signal; Confirm rough output phase through record from the number in the cycle of the oscillator signal of oscillator; Said reference signal has the frequency lower than the frequency of said oscillator signal, and wherein, said rough output phase is confirmed by synthetic accumulator;
Confirm phase error based on said rough output phase and input phase; And
Produce the control signal that is used for said oscillator based on said phase error.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104734700A (en) * | 2013-12-18 | 2015-06-24 | 英特尔Ip公司 | Circuit, a method and a synthesizer for generating a synthesized signal with a selectable frequency |
| CN107852163A (en) * | 2015-03-24 | 2018-03-27 | 盈诺飞公司 | Directly adjust in 2 points of pouring-in broadbands of digital phase-locked loop |
| CN110673822A (en) * | 2019-09-29 | 2020-01-10 | 杭州万高科技股份有限公司 | Electric energy metering microprocessor, inner core thereof, energy accumulation circuit and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060038710A1 (en) * | 2004-08-12 | 2006-02-23 | Texas Instruments Incorporated | Hybrid polar/cartesian digital modulator |
| CN1960164A (en) * | 2006-10-27 | 2007-05-09 | 清华大学 | CMOS of chip digital controlled complementary type LC oscillator in low noise |
| US7279988B1 (en) * | 2005-03-17 | 2007-10-09 | Rf Micro Devices, Inc. | Digital frequency locked loop and phase locked loop frequency synthesizer |
-
2009
- 2009-01-12 CN CN201210266806.6A patent/CN102843128B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060038710A1 (en) * | 2004-08-12 | 2006-02-23 | Texas Instruments Incorporated | Hybrid polar/cartesian digital modulator |
| US7279988B1 (en) * | 2005-03-17 | 2007-10-09 | Rf Micro Devices, Inc. | Digital frequency locked loop and phase locked loop frequency synthesizer |
| CN1960164A (en) * | 2006-10-27 | 2007-05-09 | 清华大学 | CMOS of chip digital controlled complementary type LC oscillator in low noise |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104734700A (en) * | 2013-12-18 | 2015-06-24 | 英特尔Ip公司 | Circuit, a method and a synthesizer for generating a synthesized signal with a selectable frequency |
| CN104734700B (en) * | 2013-12-18 | 2019-01-01 | 英特尔Ip公司 | For generate have can selected frequency composite signal circuit, method and synthesizer |
| CN107852163A (en) * | 2015-03-24 | 2018-03-27 | 盈诺飞公司 | Directly adjust in 2 points of pouring-in broadbands of digital phase-locked loop |
| CN107852163B (en) * | 2015-03-24 | 2021-04-16 | 盈诺飞公司 | Two-point injection type broadband direct modulation of digital phase-locked loop |
| CN110673822A (en) * | 2019-09-29 | 2020-01-10 | 杭州万高科技股份有限公司 | Electric energy metering microprocessor, inner core thereof, energy accumulation circuit and method |
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