CN102820254B - The manufacture method of semiconductor integrated circuit - Google Patents
The manufacture method of semiconductor integrated circuit Download PDFInfo
- Publication number
- CN102820254B CN102820254B CN201110150356.XA CN201110150356A CN102820254B CN 102820254 B CN102820254 B CN 102820254B CN 201110150356 A CN201110150356 A CN 201110150356A CN 102820254 B CN102820254 B CN 102820254B
- Authority
- CN
- China
- Prior art keywords
- hard mask
- metal hard
- manufacture method
- layer
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention discloses a kind of manufacture method of semiconductor integrated circuit, provides first and is formed with least one metal hard mask in substrate, and this substrate.Next patterning step is carried out to this metal hard mask, pattern this metal hard mask to form pattern metal hard mask, subsequently water plasmas process is carried out to this pattern metal hard mask.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor integrated circuit, adopt metal hard mask particularly to one kind
The manufacture method of the semiconductor integrated circuit of (metal hard mask).
Background technology
In current semi-conductor industry, embedding technique has been multi-metal intra-connection in semiconductor integrated circuit
The major technique of (multi-level interconnects).Embedding technique can be sketched as etching first in dielectric materials layer
Go out circuit pattern, then insert conductive material such as copper in this circuit pattern, and planarized, and then complete metal interconnecting
Making.Distinguishing, embedding technique can be sub-divided into groove-priority to mode according to etched pattern in dielectric materials layer
(trench-first) technique, dielectric cavity priority (via-first), part dielectric cavity priority (partial-via-first) work
Skill and voluntarily be aligned (self-aligned) technique etc..
Dielectric layer structure and metal hard mask is sequentially formed in the substrate including conductive layer, subsequently in known embedding technique
Pattern metal hard mask forms opening, then is etched technique, etches dielectric layer structure by Open Side Down and is formed and inlay
The channel patterns of wire or interlayer hole pattern.It should be noted that forming opening or often dropping in the etch process
The pollutant such as microgranule produce.The microgranule that drops is because Van der Waals force (the Van der by producing between itself and metal hard mask
Waals force) attract, and be attached on metal hard mask, or be attracted around metal hard mask.Dropping of being attracted is micro-
Grain also cannot will fall off microgranule easily even with cleaning and remove, and the presence of the microgranule that drops hinders subsequent etch work
The carrying out of skill, or even the groove opening pattern after causing to etch is the problems such as reduce or be imperfect.More lead to be subsequently formed in groove
There is the defects such as broken string in the metal in opening, reduce the reliability of metal interconnecting.
Content of the invention
Therefore, the present invention provides a kind of manufacture method of semiconductor integrated circuit in this, is attached to gold in order to solve microgranule
Belong to hard mask and then lead to the problems such as etch incomplete.
According to claim provided by the present invention, provide a kind of manufacture method of semiconductor integrated circuit.This making side
Method provides substrate first, and is formed with least one metal hard mask in this substrate.Next pattern is carried out to this metal hard mask
Change step, pattern this metal hard mask to form pattern metal hard mask.Subsequently this pattern metal hard mask is carried out
Water plasmas (H2O plasma) process.
According to the manufacture method of semiconductor integrated circuit provided by the present invention, after forming the first opening, by water
Corona treatment removes the positive charge that this pattern metal hard mask obtains in patterning step.Therefore in patterning step
The microgranule that drops of middle generation is less susceptible to be attached in pattern metal hard mask by the attraction of Van der Waals force, and is easy to by clear
Wash technique to be removed.Therefore, in the etch process subsequently carrying out, no longer because the presence of the microgranule that drops has influence on etching result,
And reduce the possibility that the metal level being subsequently stuffed into occurs broken string.Briefly, semiconductor integrated circuit provided by the present invention
Manufacture method, can effectively improve the reliability of semiconductor integrated circuit.
Brief description
The schematic diagram of the preferred embodiment of the manufacture method for semiconductor integrated circuit provided by the present invention for the Fig. 1 to Fig. 6.
Description of reference numerals
100 substrate 102 conductive layer
104 bottom 106 dielectric layer
108 cover layer 110 metal hard mask
112 pattern metal hard mask 120 anti-reflecting layer
122 patterning photoresist 124 openings
126 openings 128 drop microgranule
130 water plasmas process 140 anti-reflecting layers
142 patterning photoresist 144 openings
146 opening 150 groove opening
152 interlayer hole openings
Specific embodiment
Refer to Fig. 1 to Fig. 6, Fig. 1 to Fig. 6 is preferred for the manufacture method of semiconductor integrated circuit provided by the present invention
The schematic diagram of embodiment.As shown in figure 1, this preferred embodiment provides substrate 100 first, such as silicon base, cover containing silicon base or silicon
Insulation (silicon-on-insulator, SOI) substrate etc., and include conductive layer 102 in substrate 100 and cover conductive layer
102 bottom 104.In the preferred embodiment, conductive layer 102 includes metal material, and bottom 104 then includes N doping carbonization
Silicon (nitrogen-doped silicon carbide).In addition, substrate 100 also includes dielectric layer 106, and as shown in figure 1, it is situated between
Electric layer 106 covers bottom 104.Dielectric layer 106 may include low-k (dielectric constant, k) material (dielectric
Constant value be less than 3.9), ultralow dielectric (ultra low-k, hereinafter referred to as ULK) material or the ultralow dielectric of porous normal
Number (porous ULK) material, because advanced low-k materials, ULK material and porous ULK material are all less fine and close and tie
The relatively low material of structure intensity, therefore, this preferred embodiment optionally re-forms the cover layer of densification on dielectric layer 106 surface
108.Cover layer 108 can be illustrated in figure 1 including silicon oxide (silicon oxide, SiO), silicon oxynitride (silicon
Oxynitride, SiON) or tetraethyl oxosilane (tetraethylorthosilicate, TEOS) single layer structure, but also not
It is limited to composite film structure.
Please continue to refer to Fig. 1.Next, being in substrate 100, especially on cover layer 108, form metal hard mask
110.Metal hard mask 110 can be single layer structure or composite film structure, and is selected from titanium (titanium, Ti), titanium nitride
(titanium nitride, TiN), tantalum (tantalum, Ta) and tantalum nitride (tantalum nitride, TaN) are formed
Group.For example, the provided metal hard mask of this preferred embodiment 110 may include the composite film of Ti/TiN or Ta/TaN,
But not limited to this.It is otherwise noted that because metal hard mask 110 has the stress with respect to dielectric layer 106, therefore originally
In preferred embodiment, cover layer 108 is alternatively arranged as the buffering between metal hard mask 110 and dielectric layer 106, it is to avoid dielectric layer
106 are directly affected by the stress of metal hard mask 110.As shown in figure 1, this preferred embodiment is also in metal hard mask 110
Upper formation anti-reflecting layer (anti-reflective coating, ARC) 120, anti-reflecting layer 120 may include dielectric material such as nitrogen
Silicon oxide (SiON) or tetraethyl oxosilane (TEOS), but not limited to this.
Additionally, in the change type of this preferred embodiment, conductive layer 102 may include other conductive materials such as nitride metal
Thing, metal silicide or doped silicon, cover layer 108 then may include silicon nitride (silicon nitride, SiN), silicon oxide
(SiO) or silicon oxynitride (SiON), and metal hard mask 110 is then directly formed on cover layer 108.
Please continue to refer to Fig. 1.Next, patterning photoresist 122 is formed on anti-reflecting layer 120, pattern light
Resist 122 is caused to include an at least opening 124, in order to define the channel patterns inlaying wire.
Refer to Fig. 2.After forming patterning photoresist 122, metal hard mask 110 is carried out with patterning step
Suddenly, through the opening 124 etching anti-reflecting layer 120 of patterning photoresist 122, metal hard mask 110 and part of covering layer
108, form the pattern metal hard mask 112 including at least one opening 126 with pattern metal hard mask 110.Merit attention
, after a patterning steps, pattern metal hard mask 112 carries electric charge, and usually positive charge.Therefore, in pattern
Changing the microgranule 128 that drops producing in step is subject to the attraction of Van der Waals force to be easily attached to pattern metal hard mask 112
Around opening 126.
Refer to Fig. 3.After forming pattern metal hard mask 112, carry out water plasmas (H2Oplasma) process
130, in order to same position remove patterning photoresist 122, anti-reflecting layer 120 and pattern metal hard mask 112 these
Positive charge.In the preferred embodiment, it is to be passed through vapor (H first2O vapor) to carry out water plasmas process 130, and
The gas flow of this vapor is 2000～3000 standard milliliters (standard cubic centimeter per per minute
Minute, sccm).Next conversion (transform) vapor becomes the water plasmas with reactivity, in order to remove figure
Case photoresist 122, anti-reflecting layer 120 and positive charge.In the preferred embodiment, water plasmas process 130 work
The skill time between 15 seconds and 60 seconds, its operation pressure is between its technique of 3000 milli-torrs (mTorr) and 9000 milli-torrs
Temperature is between 25 DEG C～350 DEG C.It is the positive charge removing pattern metal hard mask 112 because water plasmas process 130,
The opening 126 that the microgranule that therefore drops 128 is no longer influenced by the attraction of Van der Waals force and is attached to pattern metal hard mask 112 is attached
Closely, and easily removed by the cleaning subsequently carrying out.Furthermore it should be noted that water plasmas process 130 and after
In continuous cleaning step, dielectric layer 106 is still protected by comparatively dense cover layer 108.
In addition, in the preferred embodiment, it is also not limited to, before water plasmas process 130, first carry out oxygen plasma
Body (O2Plasma) process, to guarantee that patterning photoresist 122 can be removed completely with anti-reflecting layer 120.In addition, in order to have
Remove to effect the positive charge of pattern metal hard mask 112, the water plasmas that this preferred embodiment is provided also are processed in 130
May include negative charge.If in addition, pattern metal hard mask 112 carries negative charge, this preferred embodiment institute after the etch process
The water plasmas providing process in 130 and also may include positive charge.
Refer to Fig. 4.After water plasmas process 130, carry out aforesaid cleaning (not shown), will fall off
Microgranule 128 etc. removes, with re-forming anti-reflecting layer 140 and patterning photoresist in pattern metal hard mask 112
142.As shown in figure 4, anti-reflecting layer 140 fills up opening 126, and pattern photoresist 142 and then have corresponding to opening 126
The opening 144 of position, is arranged in the range of opening 126, in order to define the interlayer hole pattern inlaying wire.
Refer to Fig. 5.Next by the use of patterning photoresist 142 as etching mask, photic anti-through patterning
The opening 144 of erosion agent 142 etches downwards anti-reflecting layer 140, cover layer 108 and part of dielectric layer 106, and in dielectric layer 106
The first half forms another opening 146, and opening 146 corresponds to opening 126, in order to as a part of interlayer hole.Opening 146 to be formed
Afterwards, the mode such as available oxygen plasma removes patterning photoresist 142 and anti-reflecting layer 140.
Refer to Fig. 6.Next, being etched technique again, downward etching is not patterned metal hard mask 112 and covers
Cover layer 108 and dielectric layer 106, opening 126 and opening 146 are transferred in dielectric layer 106, and in dielectric layer 106
Groove opening 150 and the interlayer hole opening 152 of wire is inlayed in interior formation.And as shown in fig. 6, bottom 104 exposes interlayer hole opening
152 bottom.
After completing the making that groove opening 150 is with interlayer hole opening 152, interlayer can be removed by the etch process being suitable for
The bottom 104 of wide open mouth 152 bottom, and expose conductive layer 102.Subsequently, in groove opening 150 with interlayer hole opening 152
Form barrier layer (not shown) and the conductive layer (not shown) filling up groove opening 150 and interlayer hole opening 152, finally by flat
Smoothization step removes unnecessary conductive layer and patterned metal layer 112, completes to inlay the making of wire.Because above-mentioned steps are this
Known to skilled person, therefore repeat no more in the preferred embodiment.Significantly, since the microgranule that drops
128 attractions being no longer influenced by Van der Waals force and remove completely in cleaning, therefore etch process can smoothly and intactly will
Opening 126 and opening 146 are transferred in dielectric layer 106, and form groove opening 150 and interlayer hole opening 152.And subsequently in ditch
When channel opening 150 and interlayer hole opening 152 insert conductive layer, conductive material can intactly insert groove opening 150 and interlayer hole
In opening 152, can be prevented effectively from because inserting disconnection problem that is imperfect and causing therefore in known technology.
In sum, the manufacture method of semiconductor integrated circuit provided by the present invention, in formation in order to define groove position
After the opening put, processed by water plasmas and remove the positive electricity that this pattern metal hard mask obtains in patterning step
Lotus.The microgranule that drops producing therefore in patterning step is less susceptible to by the attraction of Van der Waals force and is attached to pattern metal
In hard mask, and it is easy to be removed by cleaning.Therefore, in the etch process subsequently carrying out, no longer because dropping microgranule
Exist and have influence on etching result, and reduce the possibility that the metal level being subsequently stuffed into occurs broken string.Briefly, provided by the present invention
Semiconductor integrated circuit manufacture method, the reliability of semiconductor integrated circuit can be effectively improved.
The foregoing is only the preferred embodiments of the present invention, all equivalent variations done according to the claims in the present invention with repair
Decorations, all should belong to the covering scope of the present invention.
Claims (13)
1. a kind of manufacture method of semiconductor integrated circuit, including：
Substrate is provided, comprises a conductive layer and a dielectric layer is located on this conductive layer；
At least one metal hard mask is formed with this dielectric layer, one first patterning photoresist and be located at this
The first anti-reflecting layer between one patterning photoresist and this metal hard mask；
Carry out patterning step, this metal hard mask is etched by this first patterning photoresist and forms pattern metal
Hard mask, wherein this pattern metal hard mask include multiple electric charges and hard in this pattern metal by the plurality of charge adsorption
The microgranule that drops of mask；And
Carry out water plasmas process, in order to same position remove this first patterning photoresist, this first anti-reflecting layer with
And this pattern metal hard mask the plurality of electric charge and by the plurality of charge adsorption dropping in pattern metal hard mask
Microgranule；
This dielectric layer is etched by this pattern metal hard mask, exposes this conductive layer.
2. manufacture method as claimed in claim 1, wherein this metal hard mask are selected from titanium, titanium nitride, tantalum and tantalum nitride institute group
The group becoming.
3. manufacture method as claimed in claim 1, wherein this pattern metal hard mask include positive charge.
4. manufacture method as claimed in claim 3, wherein this water plasmas also include negative charge in processing.
5. manufacture method as claimed in claim 1, also includes oxygen plasma and processes, be carried out at this water plasmas and process it
Before.
6. the process time that manufacture method as claimed in claim 1, wherein this water plasmas are processed was between 15 seconds and 60 seconds
Between.
7. manufacture method as claimed in claim 1, wherein this water plasmas process also to include being passed through vapor and carry out this water
Corona treatment, and the gas flow of this vapor is 2000～3000 standard milliliters per minute.
8. the operation pressure that manufacture method as claimed in claim 1, wherein this water plasmas are processed is between 3000 milli-torrs
With 9000 milli-torrs.
9. the technological temperature that manufacture method as claimed in claim 1, wherein this water plasmas are processed is between 25 DEG C～350
℃.
10. also include conductive layer and bottom in manufacture method as claimed in claim 1, wherein this substrate, and this bottom covers
This conductive layer.
Sequentially dielectric layer and cover layer is also included in 11. manufacture methods as claimed in claim 10, wherein this substrate, and this Jie
Electric layer covers this bottom.
12. manufacture methods as claimed in claim 11, wherein this pattern metal hard mask also include at least one first opening,
And this cover layer is exposed to the bottom of this first opening.
13. manufacture methods as claimed in claim 12, further comprising the steps of, after being carried out at the process of this water plasmas：
Second anti-reflecting layer and the second patterning photoresist are sequentially formed on this pattern metal hard mask；And
Through this second patterning photoresist etch this second anti-reflecting layer, this cover layer and this dielectric layer, and formed to
Few one second opening, and this second opening corresponds to this first opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110150356.XA CN102820254B (en) | 2011-06-07 | 2011-06-07 | The manufacture method of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110150356.XA CN102820254B (en) | 2011-06-07 | 2011-06-07 | The manufacture method of semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102820254A CN102820254A (en) | 2012-12-12 |
| CN102820254B true CN102820254B (en) | 2017-03-01 |
Family
ID=47304288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110150356.XA Active CN102820254B (en) | 2011-06-07 | 2011-06-07 | The manufacture method of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102820254B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8735301B2 (en) * | 2011-05-24 | 2014-05-27 | United Microelectronics Corp. | Method for manufacturing semiconductor integrated circuit |
| CN104576512B (en) * | 2013-10-28 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of processing method for avoiding via metal that electrochemical corrosion occurs |
| CN106952863B (en) * | 2016-01-06 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| US20210082696A1 (en) * | 2018-03-01 | 2021-03-18 | Applied Materials, Inc. | Systems and methods of formation of a metal hardmask in device fabrication |
| CN114141631A (en) * | 2020-09-03 | 2022-03-04 | 长鑫存储技术有限公司 | Method for preparing metal connecting wire |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1901156A (en) * | 2005-07-19 | 2007-01-24 | 联华电子股份有限公司 | Method for producing double embedded structure |
| CN1941279A (en) * | 2005-05-27 | 2007-04-04 | 台湾积体电路制造股份有限公司 | H20 plasma and h20 vapor methods for releasing charges and use thereof |
| CN1956164A (en) * | 2005-10-24 | 2007-05-02 | 富士通株式会社 | Semiconductor device fabrication method |
| CN101106101A (en) * | 2006-07-10 | 2008-01-16 | 联华电子股份有限公司 | Single inlay structure and dual inlay structure and their open hole forming method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100605942B1 (en) * | 2004-07-16 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Method for post-treating metal interconnects of semiconductor devices |
-
2011
- 2011-06-07 CN CN201110150356.XA patent/CN102820254B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1941279A (en) * | 2005-05-27 | 2007-04-04 | 台湾积体电路制造股份有限公司 | H20 plasma and h20 vapor methods for releasing charges and use thereof |
| CN1901156A (en) * | 2005-07-19 | 2007-01-24 | 联华电子股份有限公司 | Method for producing double embedded structure |
| CN1956164A (en) * | 2005-10-24 | 2007-05-02 | 富士通株式会社 | Semiconductor device fabrication method |
| CN101106101A (en) * | 2006-07-10 | 2008-01-16 | 联华电子股份有限公司 | Single inlay structure and dual inlay structure and their open hole forming method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102820254A (en) | 2012-12-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9349687B1 (en) | Advanced manganese/manganese nitride cap/etch mask for air gap formation scheme in nanocopper low-K interconnect | |
| TWI316739B (en) | Methods of forming dual-damascene metal wiring patterns for integrated circuit devices and wiring patterns formed thereby | |
| TWI645506B (en) | Methods for forming semiconductor device having air gap | |
| TWI442512B (en) | An interconnect structure with dielectric air gaps | |
| KR100600689B1 (en) | Manufacturing method of semiconductor device | |
| CN106898595B (en) | Interconnection line structure and manufacturing method thereof | |
| US7615494B2 (en) | Method for fabricating semiconductor device including plug | |
| KR20100122701A (en) | Method of manufacturing semiconductor device | |
| TW201712803A (en) | Method of forming metal interconnection | |
| JP2008205458A (en) | Interconnect structure with bi-layer metal cap and method of fabricating the same | |
| CN102820254B (en) | The manufacture method of semiconductor integrated circuit | |
| CN109804463B (en) | Method for forming dual damascene interconnect structure | |
| CN100511601C (en) | Method for forming aperture on low dielectric permittivity dielectric layer | |
| US8735301B2 (en) | Method for manufacturing semiconductor integrated circuit | |
| CN102222640B (en) | Through hole forming method | |
| US20170148735A1 (en) | Interconnect Structure for Semiconductor Devices | |
| CN112490180B (en) | Semiconductor structure and forming method thereof | |
| CN109755175B (en) | Interconnect structure and method of forming the same | |
| JP2000114364A (en) | Metal element isolation method | |
| KR100778869B1 (en) | Method for forming contact of semiconductor device | |
| TWI524377B (en) | Method for manufacturing semiconductor integrated circuit | |
| US11081478B2 (en) | Interconnect structure having a fluorocarbon layer | |
| JP4338748B2 (en) | Manufacturing method of semiconductor device | |
| KR100500936B1 (en) | Method for forming contact hole | |
| KR100721620B1 (en) | Method for manufacturing a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |