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CN102810520A - Thermally enhanced integrated circuit package - Google Patents

Thermally enhanced integrated circuit package Download PDF

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Publication number
CN102810520A
CN102810520A CN2012100848327A CN201210084832A CN102810520A CN 102810520 A CN102810520 A CN 102810520A CN 2012100848327 A CN2012100848327 A CN 2012100848327A CN 201210084832 A CN201210084832 A CN 201210084832A CN 102810520 A CN102810520 A CN 102810520A
Authority
CN
China
Prior art keywords
chip
moulding compound
thermal element
active face
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2012100848327A
Other languages
Chinese (zh)
Inventor
曹佩华
张国钦
普翰屏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102810520A publication Critical patent/CN102810520A/en
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

According to an embodiment, an integrated circuit package comprises a chip, a thermal component, and a molding compound. The chip comprises an active surface and a backside surface opposite the active surface. The thermal component is physically coupled to the backside surface of the chip. The molding compound encapsulates the chip, and an exposed surface of the thermal component is exposed through the molding compound. Another embodiment is a method to form an integrated circuit package.

Description

The ic package that heat is improved
Technical field
The present invention relates to a kind of ic package, the ic package of especially hot improvement.
Background technology
Because development of integrated circuits is constantly improved the sustained and rapid development that integration density caused of various electronic components (that is, transistor, diode, resistor, capacitor etc.) so semicon industry has experienced.To a great extent, the improvement of this integration density comes from and reduces the minimal parts size repeatedly, and this permission is integrated in more element in the given area.Correspondingly, the density of increase allows littler IC chip.
As the result of the density that increases IC chip, the dynamic solution that needs encapsulation to be realizing more multi-link with the element of chip exterior, and littler chip size is provided.A kind of encapsulation technology is commonly referred to as embedded wafer scale BGA (eWLB) packaging part.EWLB satisfies the needs that these extra outsides connect usually, and littler chip size is provided and has other advantages.
Chip in the eWLB packaging part overheats when having, and this possibly cause the infringement to chip.Attempt to prevent that overheated a kind of existing method from being to increase external heat sink.Because the parts that the eWLB packaging part is inherent, this method does not obtain immense success.Another kind method is in the product that uses the eWLB packaging part, to use the heat radiation external member, for example, and fan.Yet this method possibly not be suitable for the hand-held product of high-performance in the space that is not used in the heat radiation external member.
Therefore, the hot property that needs the improvement of eWLB packaging part in this area.
Summary of the invention
In order to solve the problem that exists in the prior art, according to an aspect of the present invention, a kind of ic package is provided, comprising: chip, comprise active face and with said active face opposing backside surface; Thermal element, the said back side of physical connection to said chip; And moulding compound, encapsulating said chip, the exposure of said thermal element comes out through said moulding compound.
In this ic package, further comprise: bonding film, between said chip and said thermal element, said bonding film is with the said back side of said thermal element physical connection to said chip.
In this ic package, wherein, said thermal element comprises metal.
In this ic package, wherein, said thermal element comprises that metal and said metal are selected from by copper, nickel, aluminium and the group formed thereof.
In this ic package, wherein, said thermal element comprises semiconductor chip.
In this ic package, wherein, said thermal element comprises that semiconductor chip and said semiconductor chip comprise the material identical materials included with said chip.
In this ic package, wherein, said thermal element comprises that semiconductor chip and said semiconductor chip are pseudo-chip.
In this ic package, further comprise: distributed component again, be positioned on the said active face of said chip with said moulding compound on.
In this ic package, further comprise: distributed component again, be positioned on the said active face of said chip with said moulding compound on; BGA is electrically connected to the bond pad of the said active face of said chip through said distributed component again.
According to a further aspect in the invention, a kind of ic package is provided, has comprised: chip, have first surface and second surface, said first surface comprises bond pad, said second surface is relative with said first surface; Heat dissipation element is positioned on the said second surface of said chip; And moulding compound, being positioned on the lateral margin of said chip, the said lateral margin of said chip extends to said second surface from the said first surface of said chip, and said moulding compound has outer surface, exposes the exposure of said heat dissipation element through said outer surface.
In this ic package, wherein, the said outer surface copline of the said exposure of said heat dissipation element and said moulding compound.
In this ic package, wherein, encapsulate the lateral margin of said heat dissipation element through said moulding compound.
In this ic package, wherein, said heat dissipation element comprise be selected from basically by metal, semiconductor, with and the material of the group formed of combination.
In this ic package, further comprise: distributed component again is positioned on the said moulding compound on the said first surface with said chip; And BGA, comprise solder ball, through said distributed component more said solder ball is electrically connected to said bond pad.
According to another aspect of the invention, a kind of method that is used to form ic package is provided, said method comprises: thermal element is arranged on the back side of chip; Encapsulate said chip through moulding compound, the surface of said thermal element is not covered by said moulding compound; And forming redistributing layer on the active face of said chip He on the said moulding compound.
In said method, further comprise: the said active face of said chip is adhered to carrier substrates; And before forming said redistributing layer, remove said carrier substrates from the said active face of said chip.
In said method, wherein, use said moulding compound to encapsulate said chip and comprise the use compression moulding.
In said method, further comprise: form the BGA that is electrically connected to said redistributing layer, said redistributing layer is electrically connected to the bond pad on the said active face that is positioned at said chip.
In said method, wherein, said thermal element is adhered to the said back side of said chip.
In said method, wherein, said thermal element comprises metal, pseudo-chip or its combination.
Description of drawings
In order to understand present embodiment and advantage thereof better, will combine following description that accompanying drawing carries out as a reference now, wherein:
Fig. 1-9 is for making the technology of ic package according to embodiment; And
Figure 10 is the ic package according to embodiment.
Embodiment
Below, go through the manufacturing and the use of present embodiment.Yet, should be appreciated that, the invention provides many applicable inventive concepts that can in various concrete environment, realize.The specific embodiment of being discussed only illustrates the concrete mode of making and using disclosed theme, and is not used in the scope of the different embodiment of restriction.
Below in conjunction with concrete context-descriptive embodiment, promptly embedded wafer scale BGA (eWLB) packaging part and the method for making the eWLB packaging part.Yet, can also other embodiment be applied to other ic packages and method for packing.
In Fig. 1, carrier substrates 2 is provided with the laminated foil 4 on the top surface that is positioned at carrier substrates 2.Laminated foil 4 can be any acceptable adhesive tape, and can use lamination instrument to place on the carrier substrates 2.More specifically, laminated foil 4 can be any acceptable adhesive tape, and this adhesive tape makes carrier substrates 2 handle substrate from moulding compound and chip unsticking through for example heat or ultraviolet ray (UV) subsequently.Exemplary carrier substrate 2 comprises: glass substrate, silicon, quartz etc., perhaps its combination.Exemplary laminated foil 4 comprises epoxy resin, resin etc., perhaps its combination.
With reference to Fig. 2, known good chip 6 is placed on laminated foil 4 and the carrier substrates 2.Laminated foil 4 adheres to carrier substrates 2 with chip 6.Usually, chip 6 is processed by another wafer (not shown) through forming bond pad 8 above that.Then, cutting and test chip 6.Subsequently, use for example acceptable fetching tool that known good chip 6 is placed on the laminated foil 4, wherein the active face of each chip (this active face comprises bond pad 8) all adheres to laminated foil 4.The placement of chip 6 on carrier substrate 2 can reconfigure chip 6 from the wafer of preliminary working, thereby makes to have more zone to can be used for forming BGA subsequently, like hereinafter with discussed in detail.In addition, through Known good chip 6 after the use test, can avoid the encapsulation failure chip, thereby reduce production costs.During element in mentioning accompanying drawing, the subsequent drawings among this paper can be used singular references; Yet, even use singular references, also can be with these step application in a plurality of elements such as all chips 6.
Continuation is gone up formation bonding film 10 with reference to Fig. 2 at the back side (for example, the surface of the chip 6 relative with the active face that comprises bond pad 8) of chip 6.Bonding film 10 can be epoxy resin, resin etc., perhaps its combination.Thickness at the bonding film on the direction vertical with the back side 10 can be between about 25 microns and about 100 microns.Though embodiment is not limited to specific thicknesses, this thickness can not be thick in stoping heat radiation.Then, through bonding film 10 thermal element 12 is adhered to chip 6.Thermal element 12 can be metallic plate or pseudo-semiconductor chip.The exemplary materials that is used for metallic plate is copper, nickel-clad copper, aluminium etc., perhaps its combination.The material of exemplary pseudo-semiconductor chip can be identical or different with the wafer that is processed to form chip 6, such as silicon, germanium chip, SiGe chip, quartz etc., perhaps its combination.Thermal element 12 possibly have good thermal conductivity usually and/or have the thermal coefficient of expansion (CTE) suitable with the CTE of chip 6.Thermal element 12 dispels the heat usually in the packaging part of accomplishing.
In one embodiment, on the back side of chip 6, form bonding film 10 through on chip 6, depositing bonding film 10 with suitable dispensing amount and pattern.Can be through rete press deposition bonding film.Can place thermal element 12 through fetching tool.
In another embodiment, on thermal element 12, form bonding film 10 in advance, such as being cut apart (singulated) before at each thermal element 12.Then through thermal element 12 and bonding film 10 being placed on the back of chip 6 such as fetching tool.Can expect to use preformed bonding film 10 to control the thickness of bonding film 10 better.
With reference to Fig. 3, moulding compound 14 is applied to this structure.In an embodiment, moulding compound is and thermal element 12 material different.The method of use such as pressing mold applies moulding compound 14 with packaged chip 6.Then, the curing mold material 14.The back side of resulting structures is moulding compound 14, the exposure copline of this back side and thermal element 12.The thickness of moulding compound 14 is usually corresponding to the thickness of the combination of a chip 6, one deck bonding film 10 and a thermal element 12, thereby makes from the back of laminated foil 4 to moulding compound 14 and/or the thickness of the exposure of thermal element 12 is uniform.
In addition; It should be noted that; Stretch but be in the inner lateral margin of lateral margin of chip 6 though in this embodiment thermal element 12 is described as having not with the lateral margin of chip 6 is coextensive, the trend limit vertical for example with the back side of chip 6, other embodiment are not limited to this configuration.In certain embodiments, the lateral margin of thermal element 12 can perhaps can be positioned at the outside of the lateral margin of this chip with the common extension of the lateral margin of chip 6.In addition, some lateral margins of thermal element 12 can extend the outside that perhaps is positioned at the respective lateral edge of this chip with the respective lateral edge of chip 6 is common, and other lateral margins of thermal element 12 are positioned at the inside of the lateral margin of chip 6.
In Fig. 4, carrier substrates 2 and the wafer scale structure unsticking of laminated foil 4 from reconfiguring, the wafer scale structure that this reconfigures comprises: chip 6, thermal element 12, bonding film 10 and film plastics 14.Can be through heat treatment, UV processing, unsticking instrument etc., perhaps it makes up and implements unsticking.
Fig. 5 to Fig. 9 shows the formation of the spheroid of redistributing layer (RDL) and BGA.In order to describe easily, only show the part of the wafer scale structure that reconfigures with clear.Those skilled in the art will recognize, can following steps be applied to the whole wafer scale structure that reconfigures.
In Fig. 5, the surface of the wafer scale structure that dielectric layer 16 is applied to reconfigure, the said wafer scale structure that reconfigures comprises the active face of chip 6.Opening 18 in the formation dielectric layer 16 is to expose the bond pad 8 of chip 6.Dielectric layer 16 can be polyimides, polybenzoxazoles (PBO) etc., perhaps its combination.Can use spin coating technique or other deposition processs to form dielectric layer 16.Can use acceptable photoetching technique and etching to form opening 18.
Fig. 6 shows the using and constitute of deposition and resist plating 24 of barrier layer 20 and Seed Layer 22.Barrier layer 20 is the thin conformal film on the sidewall that is formed on dielectric layer 16 tops and opening 18.The barrier layer can be titanium nitride, tantalum nitride, tungsten nitride, titanium oxynitrides, nitrogen tantalum oxide, nitrogen tungsten oxide, titanium etc., perhaps its combination.Can use such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), low pressure chemical vapor deposition (LPCVD), PVD (PVD), ald (ALD), sputter or other acceptable methods and come deposited barrier layer 20.Similarly, Seed Layer 22 is the thin conforma layer that is formed on the top on barrier layer 20.Seed Layer 22 can be for being used to form the material of distribution interconnect, such as copper, aluminium, tungsten etc., perhaps its combination again.Can form Seed Layer 22 through PVD, ALD, CVD or other acceptable methods.Can form resist plating 24 through spin coating, the lamination that is used for dry film or other acceptable methods.Can use acceptable photoetching technique or other acceptable methods to constitute resist plating 24.
About Fig. 7, form again distribution interconnect 28.Distribution interconnect 28 can be copper, aluminium, tungsten, nickel etc. again, perhaps its combination, and can use plating or other receivable methods to form this distribution interconnect again.Remove resist plating 24 through for example peeling off, and remove unnecessary Seed Layer 22 and barrier layer 20 through for example using again distribution interconnect to carry out etching as mask.
In Fig. 8, use and constitute solder mask (solder stop) 30.Solder mask 30 can be polyimides, polybenzoxazoles (PBO), solder resist material etc., perhaps its combination.Can use spin coating technique or other deposition processs to form solder mask 30.The structure that solder mask 30 is formed have opening 32 is to expose distribution interconnect 28 again.Can use acceptable photoetching process and etching to form opening 32.
With reference to Fig. 9, in the opening that is connected to again distribution interconnect 28 32, form solder ball 34.Solder ball 34 can also be projection, cylinder, pillars etc., perhaps its combination, and this solder ball can be copper, tin, tin silver etc., perhaps its combination.Can use reflux technique or other acceptable methods to form solder ball 34.As shown in Figure 9, use the RDL structure, consider the output of BGA, solder ball 34 can be formed on the outside of the lateral margin of chip, compares with the active face of this chip, and the output of this BGA lets this array obtain bigger area.Then, be single individual packages part with the wafer scale structure cuts that reconfigures.
Figure 10 shows the ic package 100 according to embodiment.Can be according to making ic package 100 about the described embodiment of Fig. 1 to Fig. 9.Packaging part 100 comprises: chip 102; Bonding film 104 is positioned on the back of chip 102; Thermal element 106 adheres to chip 102 through bonding film 104; Moulding compound 108 encapsulates this chip, but exposes the surface of thermal element 106; Redistributing layer (RDL) 110, be positioned on the active face of chip 102 and be positioned at moulding compound 108 on; And the spheroid 112 of BGA, be connected to RDL.The material of these elements can be identical, perhaps with similar about respective element that Fig. 1 to Fig. 9 discussed.RDL 110 allows the output of BGA, thereby makes the area of this array greater than the area of the active face of chip 102.The thickness of moulding compound 108 is usually corresponding to the thickness of the combination of chip 102, bonding film 104 and thermal element 106.Therefore, expose the surface of thermal element 106, thereby improve the heat dissipation of the heat of chip 102 generations.
In addition, though it should be noted that at this embodiment thermal element 106 is described as having not and the coextensive lateral margin of stretching of the lateral margin of chip 102, for example, move towards the limit vertical with the back side of chip 102, other embodiment are not limited to this configuration.In certain embodiments, the lateral margin of thermal element 106 can perhaps surpass the lateral margin of chip 102 with the common extension of the lateral margin of chip 102.In addition, some lateral margins of thermal element 106 can extend the respective lateral edge that perhaps surpasses chip with the respective lateral edge of chip 102 is common, and other lateral margins of thermal element 106 are positioned at the inside of the lateral margin of chip 102.
Because thermal element can improve the dissipation of the heat of chip generation, so disclosed ic package can comprise the hot property of improvement.Therefore, can significantly improve the radiating efficiency of packaging part, and can be through add the radiating efficiency that external heat sink improves packaging part biglyyer.Therefore, can embodiment be applied in the disabled purposes of the external member of wherein dispelling the heat, such as being applied in the hand-held product of high-performance.
According to embodiment, ic package comprises: chip, thermal element, moulding compound.This chip comprise active face and with this active face opposing backside surface.The back side of thermal element physical connection to chip.The moulding compound packaged chip, and expose the exposure of thermal element through moulding compound.
According to another embodiment, ic package comprises: chip, heat dissipation element and moulding compound.Chip has first surface and second surface.First surface comprises bond pad, and second surface is relative with first surface.Heat dissipation element is positioned on the second surface of chip.Moulding compound is positioned on the lateral margin of chip, and the lateral margin of chip extends to second surface from the first surface of chip.In addition, moulding compound also has outer surface, exposes the exposed surface of heat dissipation element through this outer surface.
Additional embodiments is the method that is used to form ic package.This method comprises: thermal element is arranged on the back side of chip; Through the moulding compound packaged chip, the surface of thermal element is not covered by moulding compound; And forming redistributing layer on the active face of chip He on the moulding compound.
Although described present embodiment and advantage thereof in detail, should be appreciated that, can under the situation of purport of the present invention that does not deviate from the accompanying claims qualification and scope, make various change, replacement and change.For example, even preceding text are only described an embodiment in detail, those of skill in the art also understand easily, can in RDL, use the interconnection layer of varying number, and keep within the scope of the invention.In addition, though specifically do not indicate among this paper, can use the different materials and the technology that are used for different elements and step.In addition, can implement the method step of manufacturing and encapsulation part with any logical order, and embodiment is not limited only to the order that this paper narrates.
And the application's scope is not limited in the specific embodiment of technology, machine, manufacturing, material component, device, method and the step described in this specification.Should understand as those of ordinary skills; Through the present invention; Being used to carry out with the essentially identical function of corresponding embodiment as herein described or obtaining basic identical result's technology, machine, manufacturing of existing or exploitation from now on, material component, device, method or step can be used according to the present invention.Therefore, accompanying claims should be included in the scope of such technology, machine, manufacturing, material component, device, method or step.

Claims (10)

1. ic package comprises:
Chip, comprise active face and with said active face opposing backside surface;
Thermal element, the said back side of physical connection to said chip; And
Moulding compound encapsulates said chip, and the exposure of said thermal element comes out through said moulding compound.
2. ic package according to claim 1 further comprises: bonding film, between said chip and said thermal element, said bonding film is with the said back side of said thermal element physical connection to said chip.
3. ic package according to claim 1, wherein, said thermal element comprises metal or semiconductor chip.
4. ic package according to claim 3; Wherein, Said metal is selected from by copper, nickel, aluminium and the group formed thereof, said semiconductor chip comprise with included material identical materials or the said semiconductor chip of said chip be pseudo-chip.
5. ic package according to claim 1 further comprises: distributed component again, be positioned on the said active face of said chip with said moulding compound on.
6. ic package according to claim 5 further comprises: BGA is electrically connected to the bond pad of the said active face of said chip through said distributed component again.
7. ic package comprises:
Chip has first surface and second surface, and said first surface comprises bond pad, and said second surface is relative with said first surface;
Heat dissipation element is positioned on the said second surface of said chip; And
Moulding compound is positioned on the lateral margin of said chip, and the said lateral margin of said chip extends to said second surface from the said first surface of said chip, and said moulding compound has outer surface, exposes the exposure of said heat dissipation element through said outer surface.
8. ic package according to claim 7; Wherein, The said outer surface copline of the said exposure of said heat dissipation element and said moulding compound; And said heat dissipation element comprise be selected from basically by metal, semiconductor, with and the material of the group formed of combination, and encapsulate the lateral margin of said heat dissipation element through said moulding compound; Perhaps said ic package further comprises: distributed component again; Be positioned on the said moulding compound on the said first surface with said chip and BGA; Said BGA comprises solder ball, through said distributed component more said solder ball is electrically connected to said bond pad.
9. method that is used to form ic package, said method comprises:
Thermal element is arranged on the back side of chip;
Encapsulate said chip through moulding compound, the surface of said thermal element is not covered by said moulding compound; And
Forming redistributing layer on the active face of said chip He on the said moulding compound.
10. method according to claim 9; Comprise further that said active face with said chip adheres to carrier substrates and before forming said redistributing layer; Remove said carrier substrates from the said active face of said chip; In said method, use said moulding compound to encapsulate said chip and comprise the use compression moulding, and wherein said thermal element is adhered to the said back side of said chip, said thermal element comprises metal, pseudo-chip or its combination; Perhaps said method comprises further forming the BGA that is electrically connected to said redistributing layer that said redistributing layer is electrically connected to the bond pad on the said active face that is positioned at said chip.
CN2012100848327A 2011-06-02 2012-03-27 Thermally enhanced integrated circuit package Pending CN102810520A (en)

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