CN102769036A - Semiconductor structure and manufacturing method and operating method thereof - Google Patents

Abstract

The invention discloses a semiconductor structure and a manufacturing method and an operating method thereof. The semiconductor structure comprises a first doped region, a second doped region, a third doped region, a fourth doped region and a dielectric structure. The second doped region and the third doped region form a doped coding layer. The doped coding layer is located in the first doped region and the fourth doped region. The dielectric structure is located on the first doped region. The edge of the doped coding layer is between the edge of the adjacent fourth doped region and the edge of the dielectric structure. The semiconductor structure of the embodiments of the invention has low leakage current.

Description

Semiconductor structures and methods of manufacturing and operating the same

technical field

The present invention relates to semiconductor structures and their manufacturing and operating methods, in particular to metal oxide semiconductors and their manufacturing and operating methods.

Background technique

In recent decades, the semiconductor industry has continued to shrink the size of semiconductor structures while simultaneously improving speed, performance, density, and unit cost of integrated circuits. A general semiconductor structure such as an Enhanced Metal Oxide Semiconductor Transistor (EDMOS) is fabricated by doping all the substrate exposed by the active region definition structure to form a coding layer. The opposite edges of the encoding layer are aligned with the edges of the active region defining structure. However, this semiconductor structure has a problem of large leakage current.

Contents of the invention

The invention relates to a semiconductor structure and its manufacturing method and operation method. Compared with general semiconductor structures, the leakage current of the semiconductor structures of the embodiments of the present invention is small.

The present invention provides a semiconductor structure. The semiconductor structure includes a first doped region, a second doped region, a third doped region, a fourth doped region and a dielectric structure. The second doped region and the third doped region form a doped coding layer. The doped coding layer is located in the first doped region and the fourth doped region. The dielectric structure is located on the first doped region. The edge of the doped coding layer is between the edge of the adjacent fourth doped region and the edge of the dielectric structure.

The invention also provides a manufacturing method of the semiconductor structure. The manufacturing method includes the following steps. A first doped region is formed. A second doped region is formed. A third doped region is formed. The second doped region and the third doped region form a doped coding layer. A fourth doped region is formed. The doped coding layer is located in the first doped region and the fourth doped region. A dielectric structure is formed on the first doped region. The edge of the doped coding layer is between the edge of the adjacent fourth doped region and the edge of the dielectric structure.

The invention also provides a method of operating a semiconductor structure. The semiconductor structure includes a first doped region, a second doped region, a third doped region, a fourth doped region, a dielectric structure and a gate structure. The second doped region and the third doped region form a doped coding layer. The doped coding layer is located in the first doped region and the fourth doped region. The dielectric structure is located on the first doped region. The edge of the doped coding layer is between the edge of the adjacent fourth doped region and the edge of the dielectric structure. The gate structure is located on the doped coding layer and the first doped region. The operation method includes the following steps. A bias voltage is provided between the first electrode electrically connected to the first doped region and the second electrode electrically connected to the third doped region. The voltage of the third electrode electrically connected to the gate structure is adjusted to control the turn-on current of the semiconductor structure or turn off the semiconductor structure.

The semiconductor structures of the various embodiments of the present invention have low leakage current. The preferred embodiments are specifically cited below, and in conjunction with the attached drawings, the detailed description is as follows:

Description of drawings

FIG. 1 illustrates a cross-sectional view of a semiconductor structure according to an embodiment.

FIG. 2 shows the drain current-gate voltage (Id-Vg) curves of the general semiconductor structure and the semiconductor structure of the embodiment.

3 to 5 illustrate a method of manufacturing a semiconductor structure in an embodiment.

FIG. 6 illustrates a cross-sectional view of a semiconductor structure according to an embodiment.

[Description of main component symbols]

2, 102, 202: Substrate

4, 104, 204: the first doped region

5. 105: Active area definition structure

6, 106, 206: the second doped region

7, 107, 207: doping coding layer

8, 108, 208: three doped regions

10, 110, 210: the fourth doped region

12, 112, 212: the fifth doped region

14, 114, 214: the sixth doped region

16, 116, 216: the seventh doped region

18, 118: Part 1

20, 120: Part Two

22, 122, 222: Dielectric structure

24: Gate structure

26, 28, 30: electrodes

31, 33, 35, 37, 39, 131, 133, 135, 231, 233, 235: Edge

125: gate dielectric layer

127: Gate electrode layer

D1, D2: distance

Detailed ways

FIG. 1 illustrates a cross-sectional view of a semiconductor structure according to an embodiment. Referring to FIG. 1 , the semiconductor structure includes a substrate 2 . The first doped region 4 is located in the substrate 2 . The second doped region 6 is located between the first doped region 4 and the third doped region 8 . The fourth doped region 10 is located in the first doped region 4 . The third doped region 8 is located in the fourth doped region 10 . The fifth doped region 12 is located in the first doped region 4 . The sixth doped region 14 is located in the third doped region 8 . The seventh doped region 16 may be located between the fourth doped region 10 and the third doped region 8 . The dielectric structure 22 is located on the first doped region 4 . The gate structure 24 is located on the first doped region 4 , the second doped region 6 and the third doped region 8 . The gate structure 24 may also extend onto the dielectric structure 22 .

1, in one embodiment, the first doped region 4, the second doped region 6, the third doped region 8, the fifth doped region 12 and the sixth doped region 14 have the first conductivity type . The substrate 2 , the fourth doped region 10 and the seventh doped region 16 have a second conductivity type opposite to the first conductivity type. For example, the first conductivity type is N type, and the second conductivity type is P type. The impurity concentration of the fifth doped region 12 may be greater than the impurity concentration of the first doped region 4 . The impurity concentration of the sixth doped region 14 may be greater than the impurity concentration of the third doped region 8 . The fifth doped region 12 and the sixth doped region 14 may be heavily doped. The seventh doped region 16 may include a first portion 18 and a second portion 20 . The impurity concentration of the first portion 18 may be greater than the impurity concentration of the second portion 20 . The semiconductor structure can be a metal oxide semiconductor such as LDMOS or EDMOS, such as LDNMOS, LDPMOS, EDNMOS or EDPMOS. For example, the fifth doped region 12 can be used as a drain. The sixth doped region 14 can be used as a source.

Referring to FIG. 1 , in an embodiment, the impurity concentration of the first doped region 4 is smaller than the impurity concentration of the second doped region 6 . The impurity concentration of the third doped region 8 is also smaller than the impurity concentration of the second doped region 6 . The second doped region 6 is separated from the dielectric structure 22 by the first doped region 1 . The second doped region 6 and the third doped region 8 form a doped encoding layer 7 . The edge 31 of the doped coding layer 7 is located between the adjacent edge 33 of the fourth doped region 10 and the edge 35 of the dielectric structure 22 . In one embodiment, the distance D1 between (the edge 31 of) the doped coding layer 7 and (the edge 35 of) the dielectric structure 22 is about 0.4 um. The distance D2 between (the edge 37 of) the doped coding layer 7 and (the edge 39 of) the active area defining structure 5 is about 0.4 um. The semiconductor structure of the embodiments has low leakage current.

In an embodiment, the method of operating the semiconductor structure includes applying a bias voltage between the electrode 26 electrically connected to the first doped region 4 and the electrode 28 electrically connected to the third doped region 8 . In addition, the voltage of the electrode 30 electrically connected to the gate structure 24 can be adjusted to control the turn-on current of the semiconductor structure or turn off the semiconductor structure. The semiconductor structure of the embodiments has low leakage current.

FIG. 2 shows the drain current-gate voltage (Id-Vg) curves of the general semiconductor structure and the semiconductor structure of the embodiment. A positive voltage is applied to the drain. Source ground. Please refer to FIG. 2 , when a negative voltage is applied to the gate, the current value of the semiconductor structure of the embodiment is smaller than that of the general semiconductor structure. Therefore, the off-state leakage current of the semiconductor structure of the embodiment is smaller than that of the general semiconductor structure.

3 to 5 illustrate a method of manufacturing a semiconductor structure in an embodiment. Referring to FIG. 3 , a first doped region 104 is formed in the substrate 102 . A fourth doped region 110 is formed in the first doped region 104 . Active region defining structures 105 are formed on the substrate 102 . The active region defining structure 105 may comprise an insulating or dielectric material. For example, the active area definition structure 105 may include an oxide such as silicon oxide. The active area definition structure 105 can be field oxide (FOX) or shallow trench isolation (STI). Referring to FIG. 4 , a dielectric structure 122 is formed on the first doped region 104 . The dielectric structure 122 is not limited to field oxide as shown in FIG. 4 , and may also include shallow trench isolation.

Referring to FIG. 4 , a doping step is performed to form a doped coding layer 107 in the fourth doped region 110 . The doping step of forming the doped coding layer 107 can also be performed on the first doped region 104 . The edge 131 of the doped coding layer 107 is located between the edge 133 of the adjacent fourth doped region 110 and the edge 135 of the dielectric structure 122 . The portion of the edge doped coding layer 107 located in the fourth doped region 110 is the third doped region 108 . The portion of the doped coding layer 107 whose edge extends beyond the edge 133 is the second doped region 106 . In one embodiment, the doped coding layer 107 including the second doped region 106 and the third doped region 108 is formed simultaneously by a doping process, and the second doped region 106 is formed on the second doped region 108 having the same conductivity type. In a doped region 104, the third doped region 108 is formed in the fourth doped region 110 having the opposite conductivity type, so the impurity concentration of the third doped region 108 (for example, the net impurity concentration of the first conductivity type) is less than The impurity concentration of the second doped region 106 (for example, the net impurity concentration of the first conductivity type). In addition, the impurity concentration of the first doped region 104 (eg, the net impurity concentration of the first conductivity type) is also lower than the impurity concentration of the second doped region 106 (eg, the net impurity concentration of the first conductivity type).

Referring to FIG. 5 , a gate structure 124 is formed. The forming method of the gate structure 124 includes forming a gate dielectric layer 125 on the first doped region 104 , the second doped region 106 and the third doped region 108 . The gate electrode layer 127 may also extend onto the dielectric structure 122 . The gate electrode layer 127 may include metal, polysilicon, or metal silicide.

Referring to FIG. 5 , a fifth doped region 112 and a sixth doped region 114 are formed in the first doped region 104 and the third doped region 108 respectively. In one embodiment, the fifth doped region 112 and the sixth doped region 114 are formed in a heavily doped manner. The seventh doped region 116 may be formed in a heavily doped manner. The seventh doped region 116 is formed in the first part 118 of the fourth doped region 110 with the same conductivity type. The impurity concentration of the second portion 120 in the region 108 (eg, the net impurity concentration of the second conductivity type).

FIG. 6 illustrates a cross-sectional view of a semiconductor structure according to an embodiment. The difference between the semiconductor structure shown in FIG. 6 and the semiconductor structure shown in FIG. 1 is that the first doped region 204 is formed in the fourth doped region 210 . The edge 231 of the doped coding layer 207 is located between the edge 233 of the adjacent fourth doped region 210 and the edge 235 of the dielectric structure 222 . The fourth doped region 210 and the seventh doped region 216 have the first conductivity type. The substrate 202, the doped coding layer 207 (including the second doped region 206 and the third doped region 208), the first doped region 204, the fifth doped region 212 and the sixth doped region 214 have the second conductivity type. For example, the first conductivity type is N type, and the second conductivity type is P type. In an embodiment, the impurity concentration of the first doped region 204 and the impurity concentration of the third doped region 208 are respectively smaller than the impurity concentration of the second doped region 206 . The semiconductor structure of an embodiment may have low leakage current.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some local changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention should be defined by the claims.

Claims (10)

1. a semiconductor structure is characterized in that, comprising:

One first doped region;

One second doped region;

One the 3rd doped region, wherein this second doped region and the 3rd doped region form a doping encoding layer;

One the 4th doped region wherein should the doping encoding layer be arranged in this first doped region and the 4th doped region; And

One dielectric structure is positioned on this first doped region, and one edge that wherein should the doping encoding layer is between the one edge of the one edge of the 4th adjoining doped region and this dielectric structure.

2. semiconductor structure according to claim 1; It is characterized in that; This second doped region is in abutting connection with the 3rd doped region, and this second doped region is between the 3rd doped region and this first doped region, and the impurity concentration of this second doped region is greater than the impurity concentration of the 3rd doped region.

3. semiconductor structure according to claim 1 is characterized in that, also comprises a grid structure, is positioned on this first doped region and this doping encoding layer.

4. semiconductor structure according to claim 1 is characterized in that, this first doped region, this second doped region have identical conductivity type with the 3rd doped region.

5. semiconductor structure according to claim 4 is characterized in that, the impurity concentration of the impurity concentration of this first doped region and the 3rd doped region is different from the impurity concentration of this second doped region respectively.

6. semiconductor structure according to claim 5 is characterized in that, the impurity concentration of the impurity concentration of this first doped region and the 3rd doped region is respectively less than the impurity concentration of this second doped region.

7. the manufacturing approach of a semiconductor structure is characterized in that, comprising:

Form one first doped region;

Form one second doped region;

Form one the 3rd doped region, wherein this second doped region and the 3rd doped region form a doping encoding layer;

Form one the 4th doped region, wherein should the doping encoding layer be arranged in this first doped region and the 4th doped region; And

Form a dielectric structure on this first doped region, one edge that wherein should the doping encoding layer is between the one edge of the one edge of the 4th adjoining doped region and this dielectric structure.

8. the manufacturing approach of semiconductor structure according to claim 7 is characterized in that, this first doped region, this second doped region have identical conductivity type with the 3rd doped region.

9. the manufacturing approach of semiconductor structure according to claim 8 is characterized in that, the impurity concentration of the impurity concentration of this first doped region and the 3rd doped region is respectively less than the impurity concentration of this second doped region.

10. the method for operation of a semiconductor structure is characterized in that, this semiconductor structure comprises:

One first doped region;

One second doped region;

One the 3rd doped region, wherein this second doped region and the 3rd doped region form a doping encoding layer;

One the 4th doped region wherein should the doping encoding layer be arranged in this first doped region and the 4th doped region;

One dielectric structure is positioned on this first doped region, and one edge that wherein should the doping encoding layer is between the one edge of the one edge of the 4th adjoining doped region and this dielectric structure; And

One grid structure is positioned on this doping encoding layer and this first doped region,

Wherein this method of operation comprises:

Make one first electrode that is electrically connected to this first doped region and be electrically connected between one second electrode of the 3rd doped region and have a bias voltage; And

Adjustment is electrically connected to the voltage of a third electrode of this grid structure, with the firing current of controlling this semiconductor structure or close this semiconductor structure.

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