CN102751197A

CN102751197A - Method for manufacturing NMOS (N-channel metal oxide semiconductor) device

Info

Publication number: CN102751197A
Application number: CN2012102090484A
Authority: CN
Inventors: 徐强
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2012-06-21
Filing date: 2012-06-21
Publication date: 2012-10-24
Anticipated expiration: 2032-06-21
Also published as: CN102751197B

Abstract

The invention relates to a method for manufacturing an NMOS (N-channel metal oxide semiconductor) device, which comprises the following steps of: providing an NMOS-containing substrate; allowing a silicon nitride layer with high tensile stress to be deposited on the substrate; classifying NMOSs non-covered with silicon nitride layers before deposition in accordance with the lengths of NMOS channels, retaining the silicon nitride layer corresponding to the NMOS with a maximum channel length, removing the silicon nitride layers corresponding to the rest NMOSs by remote plasma etching, and re-depositing the silicon nitride layers; and repeatedly performing the step until the NMOSs non-covered with silicon nitride layers before deposition can not be classified in accordance with the lengths of NMOS channels, continuing to perform the follow-up universal semiconductor process flow so as to form an NMOS transistor. According to the method for manufacturing the NMOS device, in accordance with the length of the channel of the NMOS device, by a depositing-remote plasma etching-re-deposition method, the thickness of the silicon nitride layer is proportional to the channel length, and the consistency of performance adjustment of the NMOS device is realized.

Description

The nmos device manufacture method

Technical field

The present invention relates to semiconductor fabrication process, and be particularly related to the nmos device manufacture method.

Background technology

Along with the development of semiconductor fabrication process technology, the characteristic line breadth of IC chip is more and more littler, and in order to improve the performance of semiconductor device, the stress engineering technology is widely used in the semiconductor technology, in order to improve the electromobility of charge carrier.Wherein, more common, for example in the manufacturing process of nmos device, adopt via etch to stop layer (Contact Etch Stop Layer, CESL) stress engineering technology.

Via etch stops the ply stress engineering, is to stop in the layer film deposition process in via etch, and is heavily stressed in the inner generation of film through the adjustment sedimentary condition, this stress is transmitted in the device channel, thereby the mobility of charge carrier rate is exerted an influence.For example,, can stop the ply stress engineering, form via etch and stop layer film, produce compression in film inside, and this stress is conducted in the raceway groove of NMOS, raceway groove is formed tensile stress through via etch for nmos device.Because the tensile stress of channel direction helps to improve the electron mobility of nmos device, thereby can help to improve the performance of nmos device.In the practice, had experiment to prove, through deposition high tensile stress silicon nitride film, the performance that can improve NMOS reaches more than 10%.

Yet the inventor is through finding that in practice the method that adopts conventional via etch to stop the ply stress engineering promotes the performance of NMOS, and for the NMOS of different channel lengths, it promotes effect is inconsistent.With reference to figure 1, along with the increase of channel length, the effect that promotes performance diminishes.

At present; In production reality; In order to address this problem, when layout design, just to consider the influence of channel length usually, thereby adopt the transistor design of special construction; And the domain that is designed constantly tested and revise, this method has increased the research and development production cycle and the cost of product undoubtedly greatly.

Summary of the invention

The invention provides a kind of nmos device manufacture method; According to the length of channel length successively to the pairing silicon nitride layer of the NMOS with different channel lengths deposit-the remote plasma etching removes-deposition once more; Make silicon nitride layer thickness be directly proportional, thereby realize consistency the adjustment of nmos device performance with channel length.

In order to realize above-mentioned technical purpose, the present invention proposes a kind of nmos device manufacture method, comprising: the substrate that contains NMOS is provided; Deposition has the silicon nitride layer of high tensile stress in said substrate; The said NMOS that no silicon nitride layer before the deposition is covered classifies according to the length order of NMOS channel length; Keep and have the pairing silicon nitride layer of NMOS of long channel length among the above-mentioned NMOS; The remote plasma etching is to remove all the other pairing silicon nitride layer, deposited silicon nitride layer once more among the above-mentioned NMOS; Repeat above-mentioned steps, the said NMOS that no silicon nitride layer covers before deposition can't classify according to the length order of NMOS channel length, continues follow-up general semiconductor process flow, to form nmos pass transistor.

Optional; The NMOS that no silicon nitride layer covers before said will the deposition classifies according to the length order of NMOS channel length; Keep and have the pairing silicon nitride layer of NMOS of long channel length among the above-mentioned NMOS; The remote plasma etching is to remove all the other pairing silicon nitride layers among the above-mentioned NMOS; Deposited silicon nitride layer comprises once more: said NMOS is divided three classes according to the length order of NMOS channel length, and for the shortest and inferior short NMOS of channel length, the remote plasma etching is removed its corresponding silicon nitride layer; Deposit second silicon nitride layer; The remote plasma etching is removed NMOS corresponding second silicon nitride layer the shortest with channel length; Deposit the 3rd silicon nitride layer.

Optional, using plasma strengthens chemical vapour deposition technique and deposits said silicon nitride layer.

Optional, the thickness of each said silicon nitride layer that deposits is 100 dust to 300 dusts.

Optional, said silicon nitride layer has high tensile stress, and said high tensile stress is the lucky handkerchief of 0.7 lucky handkerchief to 2.0.

Optional, said silicon nitride layer is carried out the etching gas that the remote plasma etching adopts is the remote plasma that contains hydrogen and/or gas of nitrogen trifluoride.

Optional, the follow-up general semiconductor process flow of said continuation comprises the preceding dielectric substance layer of plated metal.

Compared to prior art; Nmos device manufacture method of the present invention has taken into full account the high tensile stress of silicon nitride layer of different-thickness to the Different Effects of channel carrier; Length according to the nmos device channel length; Method through deposition-remote plasma etching is removed-deposited once more makes the thickness of said silicon nitride layer be directly proportional with channel length, thereby can realize the consistency to the adjustment of nmos device performance.

Description of drawings

Fig. 1 is the sketch map of channel length with its corresponding performance of nmos device;

Fig. 2 is the schematic flow sheet of a kind of execution mode of nmos device manufacture method of the present invention;

Fig. 3 is the generalized section when having different length NMOS raceway groove in the substrate of nmos device manufacture method of the present invention;

Fig. 4 is the schematic flow sheet of an embodiment of nmos device manufacture method of the present invention;

Fig. 5-Fig. 9 is the generalized section according to the formed nmos device of a kind of embodiment of nmos device manufacture method of the present invention.

Embodiment

Nmos device manufacture method provided by the present invention is through after common high tensile stress silicon nitride layer deposition is accomplished; Said silicon nitride layer is taked deposit according to the length of nmos device channel length-removal of remote plasma etching-processing of deposition once more; Make that the raceway groove of nmos device is long more; Its corresponding said silicon nitride layer is thick more, thereby can realize the consistency to the adjustment of nmos device performance.

To combine specific embodiment and accompanying drawing below, nmos pass transistor manufacture method of the present invention will be set forth in detail.

With reference to figure 2, nmos device manufacture method of the present invention comprises:

Step S100 provides the substrate that contains NMOS;

Step S200, deposition has the silicon nitride layer of high tensile stress in said substrate;

Step S300; The said NMOS that no silicon nitride layer before the deposition is covered classifies according to the length order of NMOS channel length; Keep and have the pairing silicon nitride layer of NMOS of long channel length among the above-mentioned NMOS; The remote plasma etching is to remove all the other pairing silicon nitride layer, deposited silicon nitride layer once more among the above-mentioned NMOS;

Repeated execution of steps S300, the said NMOS that no silicon nitride layer covers before deposition can't classify according to the length order of NMOS channel length, and execution in step S400 continues follow-up general semiconductor process flow, to form nmos pass transistor.

With reference to figure 3, in one embodiment, the NMOS in the substrate 100 has three kinds of raceway grooves that length is different respectively, and the order that wherein increases progressively according to channel length is followed successively by NMOS101, NMOS102 and NMOS103.Accordingly, with reference to figure 4, nmos device manufacture method of the present invention comprises:

Step S1 provides the substrate that contains NMOS;

Step S2, deposition first silicon nitride layer in said substrate;

Step S3, for the shortest and inferior short NMOS of channel length, the remote plasma etching is removed its first corresponding silicon nitride layer;

Step S4 deposits second silicon nitride layer;

Step S5, the remote plasma etching is removed NMOS corresponding second silicon nitride layer the shortest with channel length;

Step S6 deposits the 3rd silicon nitride layer;

Step S7 continues follow-up general semiconductor process flow, to form nmos pass transistor.

Specifically, with reference to figure 5, deposition first silicon nitride layer 110 in the substrate with NMOS 100.

With reference to figure 6, earlier first silicon nitride layer 110 that is deposited on time short NMOS102 of the shortest NMOS101 of channel length and channel length is made public and the remote plasma etching, remove the first corresponding silicon nitride layer 110.Then, with reference to figure 7, deposition forms second silicon nitride layer 120 once more.

Then,, again second silicon nitride layer 120 that is deposited on the shortest NMOS101 of channel length is made public and the remote plasma etching, remove the second corresponding silicon nitride layer 120 with reference to figure 8.Then, with reference to figure 9, deposition forms the 3rd silicon nitride layer 130 once more.

The thickness of any can be 100 dust to 300 dusts in above-mentioned first silicon nitride layer 110, second silicon nitride layer 120 and the 3rd silicon nitride layer 130, but and using plasma strengthen chemical vapour deposition technique and deposit.Said first silicon nitride layer 110, second silicon nitride layer 120 and the 3rd silicon nitride layer 130 all have high tensile stress, and the range of stress is that 0.7 lucky handkerchief (GPa) is to 2.0 lucky handkerchiefs.

Be not difficult to find; After forming the 3rd silicon nitride layer 130; First silicon nitride layer 110, second silicon nitride layer 120 and the 3rd silicon nitride layer 130 have been deposited on the longest NMOS103 of channel length; Deposit second silicon nitride layer 120 and the 3rd silicon nitride layer 130 on channel length vice-minister's the NMOS102, and deposited the 3rd silicon nitride layer 130 on the shortest NMOS101 of channel length.That is to say; Remove-mode of deposition once more through above-mentioned deposition-remote plasma etching, make the thickness of the silicon nitride layer that deposited on the NMOS be directly proportional with the length of its channel length, channel length is long; The silicon nitride layer thicker that is then deposited; Otherwise channel length is short, the silicon nitride layer thin thickness that is then deposited.

Because the silicon nitride layer that is deposited has high tensile stress; And this stress can conduct in the raceway groove, and with raising mobility of charge carrier speed, and silicon nitride layer is thick more; The charge carrier quantity that its stress can influence is many more, thereby can adjust the performance of NMOS with long raceway groove.Therefore, the silicon nitride layer that is directly proportional with channel length can be realized the consistency to the adjustment of nmos device performance.

Wherein, the etching gas that adopts during above-mentioned remote plasma etching can adopt the for example SiCoNi processing procedure of company of Applied Materials for containing the remote plasma of hydrogen (H2), Nitrogen trifluoride gases such as (NF3).

In a kind of embodiment, step S7 also can comprise the preceding dielectric substance layer of plated metal.

In other execution mode of nmos device manufacture method of the present invention, the NMOS in the substrate also can have the raceway groove that surpasses three kinds of different lengths respectively, and the kind of its channel length does not cause restriction to the invention thinking of nmos device manufacture method of the present invention.

Compared to prior art; The thickness that nmos device manufacture method of the present invention has taken into full account silicon nitride layer makes high tensile stress that it had to Different Effects that channel carrier caused; According to the length of nmos device channel length, NMOS is classified, and gradation carries out that the remote plasma etching is removed and deposition once more; Make the thickness of said silicon nitride layer be directly proportional, thereby can realize consistency the adjustment of nmos device performance with channel length.

Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.

Claims

1. a nmos device manufacture method is characterized in that, comprising:

The substrate that contains NMOS is provided;

Deposition has the silicon nitride layer of high tensile stress in said substrate;

The said NMOS that no silicon nitride layer before the deposition is covered classifies according to the length order of NMOS channel length; Keep and have the pairing silicon nitride layer of NMOS of long channel length among the above-mentioned NMOS; The remote plasma etching is to remove all the other pairing silicon nitride layer, deposited silicon nitride layer once more among the above-mentioned NMOS;

Repeat above-mentioned steps, the said NMOS that no silicon nitride layer covers before deposition can't classify according to the length order of NMOS channel length, continues follow-up general semiconductor process flow, to form nmos pass transistor.

2. nmos device manufacture method as claimed in claim 1; It is characterized in that; The NMOS that no silicon nitride layer covers before said will the deposition classifies according to the length order of NMOS channel length; Keep and have the pairing silicon nitride layer of NMOS of long channel length among the above-mentioned NMOS, the remote plasma etching is to remove all the other pairing silicon nitride layers among the above-mentioned NMOS, and deposited silicon nitride layer comprises once more:

Said NMOS is divided three classes according to the length order of NMOS channel length, and for the shortest and inferior short NMOS of channel length, the remote plasma etching is removed its corresponding silicon nitride layer;

Deposit second silicon nitride layer;

The remote plasma etching is removed NMOS corresponding second silicon nitride layer the shortest with channel length;

Deposit the 3rd silicon nitride layer.

3. nmos device manufacture method as claimed in claim 1 is characterized in that, using plasma strengthens chemical vapour deposition technique and deposits said silicon nitride layer.

4. nmos device manufacture method as claimed in claim 1 is characterized in that, the thickness of said silicon nitride layer is 100 dust to 300 dusts.

5. nmos device manufacture method as claimed in claim 1 is characterized in that said silicon nitride layer has high tensile stress, and said high tensile stress is the lucky handkerchief of 0.7 lucky handkerchief to 2.0.

6. nmos device manufacture method as claimed in claim 1 is characterized in that, said silicon nitride layer is carried out the etching gas that the remote plasma etching adopts is the remote plasma that contains hydrogen and/or gas of nitrogen trifluoride.

7. nmos device manufacture method as claimed in claim 1 is characterized in that, the follow-up general semiconductor process flow of said continuation comprises the preceding dielectric substance layer of plated metal.