CN102724382A - Circuit for processing picture signal - Google Patents
Circuit for processing picture signal Download PDFInfo
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- CN102724382A CN102724382A CN2011100772925A CN201110077292A CN102724382A CN 102724382 A CN102724382 A CN 102724382A CN 2011100772925 A CN2011100772925 A CN 2011100772925A CN 201110077292 A CN201110077292 A CN 201110077292A CN 102724382 A CN102724382 A CN 102724382A
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Abstract
Provided is a circuit for processing a picture signal. The circuit comprises: a plurality of sampling storage circuits for sampling and storing charges of the picture signal; a plurality of time-sharing switch pairs which are one by one corresponding to the plurality of sampling storage circuits and are used for controlling the plurality of sampling storage circuits to output a sampling signal; a buffer electrically connected to the plurality of sampling storage circuits by the plurality of time-sharing switch pairs for buffering the signal output by the plurality of time-sharing switch pairs; and a switched capacitor amplifier for amplifying a sampling signal output by the buffer. The plurality of sampling storage circuits are connected to the same buffer through the plurality of time-sharing switch pairs, so that the occupied area is reduced and a fixed pattern noise of a column readout circuit is reduced when each column is corresponding to one buffer.
Description
Technical field
The present invention relates to field of image sensors, be specifically related to a kind of imaging signal processing circuit.
Background technology
Existing imaging signal processing circuit is as shown in Figure 1, comprising: sampling memory circuit 10, DDS (delta difference sampling method, difference sampling) switch, buffer 11, row K switch 3 and switched capacitor amplifier 12; The corresponding sampling memory circuit 10 of each row image; Each sampling memory circuit 10 corresponding buffer; Reset signal and picture signal that memory circuit 10 samplings of sampling like this obtain are stored in respectively among capacitor C 1 and the C2; Give buffer 11 through the DDS switch then, the 3 timesharing conductings of row K switch carry out processing and amplifying for switched capacitor amplifier 12 image signal transmission of each row.
Fig. 2 is the oscillogram of the imaging signal processing circuit of Fig. 1; When reset switch K_reset is closed, reset signal level by stable storage in 1 li of the pairing capacitor C of reset switch, when signaling switch K_signal is closed, optical signalling level by stable storage in the pairing electric capacity of signal level; Be stored in inside each self-corresponding electric capacity through reset switch K_reset and signaling switch K_signal control reset signal and picture signal like this; Like the oscillogram on capacitor C among Fig. 21 and the C2, the signal waveform of process buffer 11 outputs is shown in signal A1 and A2; When row K switch 3 closures, begin to export the signal of every row; The signal of handling through buffer begins to export to 12 processing of follow-up switched capacitor amplifier, is a certain level in case the DDS switch closure signals is converged, in interval later half the breaking of row K switch 3 closures; The DDS switch begins closure; Its main effect is the level deviation on the erasure signal circuit, and what as much as possible guarantee row reading circuit output is the difference of reset level and signal level, shown in A3 and A4; And the picture signal of this moment just is converted into the difference signal of A3 and A4 and be stored in inside sampling capacitance C3 and the C5 of switched capacitor amplifier 12.When K switch 4 was closed with K5, switched capacitor amplifier 12 was in common-mode state, and signal A3 and A4 are stored in sampling capacitance C3 and C5 the inside respectively; In case K switch 4 is broken off with K5, the signal that is stored in capacitor C 3 and C5 is transferred to capacitor C 4 and C6 the inside, thereby causes the variation of output voltage; Switched capacitor amplifier 12 promptly amplifies the difference signal of A3 and A4; Multiplication factor is C3/C4, (C3=C5 wherein, C4=C6).In whole process, the charge signal of the capacitance stores that row are read is converted into voltage signal through row the inside buffer separately and amplifies through switched capacitor amplifier 12.
Because what the row reading circuit of this imaging signal processing circuit was corresponding is each row of signal; So its width and number are receiving the decision of the deration of signal and number; And all corresponding buffer of each row, along with increasing of signal number, area required on the domain can be bigger; Also have signal through the decay that buffer caused, the gain mismatches on the buffer, error etc. also can strengthen the fixed pattern noise of row reading circuit.
Summary of the invention
The present invention is for solving all corresponding buffer of each row image in the prior art imaging signal processing circuit, makes the problem that chip area increases, thereby a kind of imaging signal processing circuit that reduces chip area is provided.
For solving the problems of the technologies described above, the present invention provides following technical scheme:
A kind of imaging signal processing circuit comprises: a plurality of sampling memory circuits are used for the storage of sampling of the electric charge of picture signal; A plurality of time-shared switchs are right, and are corresponding one by one with said a plurality of sampling memory circuits, and control a plurality of sampling memory circuit output sampled signals; Buffer pair is electrically connected with said a plurality of sampling memory circuits through a plurality of time-shared switchs, is used for a plurality of time-shared switchs are cushioned the signal of exporting; Switched capacitor amplifier amplifies the sampled signal of said buffer output.
Compared with prior art; The present invention has following beneficial effect: a kind of imaging signal processing circuit provided by the invention; A plurality of sampling memory circuits pair are connected with same buffer through a plurality of time-shared switchs; Reduced chip area, and the fixed pattern noise of row reading circuit when having reduced all corresponding buffer of each row.
Description of drawings
Fig. 1 is the schematic diagram of prior art imaging signal processing circuit.
Fig. 2 is the oscillogram of imaging signal processing circuit among Fig. 1.
Fig. 3 is the schematic diagram of embodiment of the invention imaging signal processing circuit.
Fig. 4 is the oscillogram of imaging signal processing circuit among Fig. 3.
Embodiment
Clearer for technical problem, technical scheme and beneficial effect that the present invention is solved, below in conjunction with accompanying drawing and embodiment, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
Fig. 3 is the schematic diagram of embodiment of the invention imaging signal processing circuit; A kind of imaging signal processing circuit comprises: a plurality of sampling memory circuits 20 are used for the storage of sampling of the electric charge of picture signal; A plurality of time-shared switchs are to 21, and are corresponding one by one with said a plurality of sampling memory circuits 20, and control a plurality of sampling memory circuit output sampled signals; Buffer 22 pair is electrically connected with said a plurality of sampling memory circuits 20 through a plurality of time-shared switchs, is used for a plurality of time-shared switchs are cushioned 21 signals exported; Switched capacitor amplifier 23 amplifies the sampled signal of said buffer 22 outputs.A plurality of sampling memory circuits pair are connected with same buffer through a plurality of time-shared switchs, have reduced chip area, and the fixed pattern noise of row reading circuit when having reduced buffer of the equal correspondence of each row.
Sampling memory circuit 20 comprises in the present embodiment: reset switch K_reset, signaling switch K_singal, reset capacitance C1, signal capacitor C 2; Said reset switch K_reset is connected to earth signal through reset capacitance C1; Signaling switch K_singal is connected to earth signal through signal capacitor C 2; The equal connection layout image signal of reset switch K_reset and signaling switch K_singal is as the input of said sampling memory circuit 20; The node of reset switch K_reset and reset capacitance C1 is first output of said sampling memory circuit 20, and the node of signaling switch K_singal and signal capacitor C 2 is second outputs of said sampling memory circuit 20; First output of said sampling memory circuit 20 and second output are connected time-shared switch respectively to two inputs of 21.
Switched capacitor amplifier 23 comprises in the present embodiment: the second fully differential amplifier U3, the 3rd capacitor C 13, the 4th capacitor C 14, the 5th capacitor C 15, the 6th capacitor C 16, the 3rd K switch 13 and the 4th K switch 14; Said the 3rd capacitor C 13 and the 4th capacitor C 14 are connected the first input end and second input of the said second fully differential amplifier U3 respectively; The 5th capacitor C 15 is connected the first input end and first output of the second fully differential amplifier U3 with the 3rd K switch 13 parallel connection backs, the 6th capacitor C 16 is connected second input and second output of the second fully differential amplifier U3 with the 4th K switch 14 parallel connection backs.The 3rd capacitor C 13 and the 4th capacitor C 14 equate in the present embodiment, and the 5th capacitor C 15 and the 6th capacitor C 16 equate.And first input end is a positive input terminal, and second input is a negative input end, and first output is a negative output terminal, and second output is a positive output end.
Fig. 4 is the oscillogram of imaging signal processing circuit among Fig. 3, specifies operation principle below in conjunction with Fig. 4:
When reset switch K_reset is closed; Reset signal electric charge by stable storage in 1 li of pairing first capacitor C of reset switch; When signaling switch K_signal is closed, optical signalling electric charge by stable storage in 2 li of pairing second capacitor C of signal level; Be stored in each self-corresponding electric capacity the inside through reset switch K_reset and signaling switch K_signal control reset signal and picture signal like this, like the oscillogram on capacitor C among Fig. 41 and the C2.When time-shared switch is closed to K3, begin the signal that every row are exported in timesharing; The signal of handling through buffer 22 begins to export to 23 processing of follow-up switched capacitor amplifier; When in case first K switch 11 is in the low level disconnection with second switch K12; This moment, time-shared switch was closed to K3, and the charge stored of electric capacity the inside just is transferred in electric capacity first capacitor C 11 and second capacitor C 12 of buffer 22 in the sampling memory circuit 20, and concrete signal waveform and sequential are as shown in Figure 4.When the 3rd K switch 13 and the 4th K switch 14 closures; Switched capacitor amplifier 23 is in common-mode state; The signal B1 and the B2 of buffer 22 outputs are stored in the 3rd capacitor C 13 and the 4th capacitor C 14 the insides respectively; In case the 3rd K switch 13 and the 4th K switch 14 are broken off, the signal that is stored in the 3rd capacitor C 13 and the 4th capacitor C 14 is transferred to the 5th capacitor C 15 and the 6th capacitor C 16 the insides, thereby causes the variation of output voltage; Switched capacitor amplifier 23 promptly amplifies the difference signal of buffer 22 output signal B1 and B2, is output as B3 and B4 after the amplification.Wherein the difference of B3 and B4 be B2 and B1 difference C13/C15 doubly, (C13=C14 wherein, C15=C16).The embodiment of the invention is only added a buffer structure in the back of entire image signal processing circuit; Reduced the required chip area of imaging signal processing circuit greatly; Because the power consumption of a plurality of buffers is far longer than a needed power consumption of buffer, has promptly eliminated existing imbalance of each column buffer and error.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. an imaging signal processing circuit is characterized in that, comprising:
A plurality of sampling memory circuits are used for the picture signal storage of sampling;
A plurality of time-shared switchs are right, and are corresponding one by one with said a plurality of sampling memory circuits, and control a plurality of sampling memory circuit output sampled signals;
Buffer pair is electrically connected with said a plurality of sampling memory circuits through a plurality of time-shared switchs, is used for a plurality of time-shared switchs are cushioned the signal of exporting;
Switched capacitor amplifier amplifies the sampled signal of said buffer output.
2. imaging signal processing circuit according to claim 1; It is characterized in that; Said sampling memory circuit comprises: reset switch, signaling switch, reset capacitance, signal electric capacity; Said reset switch is connected to earth signal through reset capacitance, and signaling switch is connected to earth signal through signal electric capacity, and the equal connection layout image signal of reset switch and signaling switch is as the input of said sampling memory circuit; The node of reset switch and reset capacitance is first output of said sampling memory circuit, and the node of signaling switch and signal electric capacity is second output of said sampling memory circuit; First output of said sampling memory circuit is connected two right inputs of time-shared switch respectively with second output.
3. imaging signal processing circuit according to claim 1; It is characterized in that; Said buffer comprises: the first fully differential amplifier, first electric capacity, second electric capacity, first switch and second switch; The first input end of the said first fully differential amplifier is connected two right outputs of time-shared switch respectively with second input; Second input and second output that are connected the first fully differential amplifier behind the first input end and first output that are connected the first fully differential amplifier after first electric capacity and first switch in parallel, second electric capacity and second switch parallel connection.
4. imaging signal processing circuit according to claim 3 is characterized in that, said first electric capacity and second electric capacity equate.
5. imaging signal processing circuit according to claim 3 is characterized in that said first input end is a positive input terminal, and second input is a negative input end.
6. imaging signal processing circuit according to claim 3 is characterized in that, said first output is a negative output terminal, and second output is a positive output end.
7. imaging signal processing circuit according to claim 1; It is characterized in that; Said switched capacitor amplifier comprises: the second fully differential amplifier, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, the 3rd switch and the 4th switch; Said the 3rd electric capacity and the 4th electric capacity are connected the first input end and second input of the said second fully differential amplifier respectively; Second input and second output that are connected the second fully differential amplifier behind the first input end and first output that are connected the second fully differential amplifier after the 5th electric capacity and the 3rd switch in parallel, the 6th electric capacity and the 4th switch in parallel.
8. imaging signal processing circuit according to claim 7 is characterized in that, said the 3rd electric capacity and the 4th electric capacity equate that said the 5th electric capacity and the 6th electric capacity equate.
9. imaging signal processing circuit according to claim 7 is characterized in that said first input end is a positive input terminal, and second input is a negative input end.
10. imaging signal processing circuit according to claim 7 is characterized in that, said first output is a negative output terminal, and second output is a positive output end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100772925A CN102724382A (en) | 2011-03-30 | 2011-03-30 | Circuit for processing picture signal |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100772925A CN102724382A (en) | 2011-03-30 | 2011-03-30 | Circuit for processing picture signal |
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| CN102724382A true CN102724382A (en) | 2012-10-10 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016101550A1 (en) * | 2014-12-25 | 2016-06-30 | 深圳市中兴微电子技术有限公司 | Operational amplifier circuit and method, temperature sensor and storage medium |
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| EP1119202A2 (en) * | 2000-01-12 | 2001-07-25 | General Instrument Corporation | Logo insertion on an HDTV encoder |
| JP2004349812A (en) * | 2003-05-20 | 2004-12-09 | Sony Corp | Image decoding apparatus and image decoding method |
| CN1828715A (en) * | 2005-02-28 | 2006-09-06 | 恩益禧电子股份有限公司 | Drive circuit chip and display device |
| US20090147114A1 (en) * | 2006-12-07 | 2009-06-11 | Byd Company Limited | Circuits and Methods for Image Signal Sampling |
| CN101895696A (en) * | 2009-05-19 | 2010-11-24 | 佳能株式会社 | Solid-state imaging apparatus |
| CN101938598A (en) * | 2009-06-30 | 2011-01-05 | 佳能株式会社 | Image pickup apparatus, image pickup system, and control method thereof |
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2011
- 2011-03-30 CN CN2011100772925A patent/CN102724382A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1119202A2 (en) * | 2000-01-12 | 2001-07-25 | General Instrument Corporation | Logo insertion on an HDTV encoder |
| JP2004349812A (en) * | 2003-05-20 | 2004-12-09 | Sony Corp | Image decoding apparatus and image decoding method |
| CN1828715A (en) * | 2005-02-28 | 2006-09-06 | 恩益禧电子股份有限公司 | Drive circuit chip and display device |
| US20090147114A1 (en) * | 2006-12-07 | 2009-06-11 | Byd Company Limited | Circuits and Methods for Image Signal Sampling |
| CN101895696A (en) * | 2009-05-19 | 2010-11-24 | 佳能株式会社 | Solid-state imaging apparatus |
| CN101938598A (en) * | 2009-06-30 | 2011-01-05 | 佳能株式会社 | Image pickup apparatus, image pickup system, and control method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016101550A1 (en) * | 2014-12-25 | 2016-06-30 | 深圳市中兴微电子技术有限公司 | Operational amplifier circuit and method, temperature sensor and storage medium |
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Application publication date: 20121010 |