CN102709315A - BE-SONOS (Band-gap Engineering SONOS (Silicon Oxide Nitride Oxide Semiconductor)) structure device with tapered energy band - Google Patents
BE-SONOS (Band-gap Engineering SONOS (Silicon Oxide Nitride Oxide Semiconductor)) structure device with tapered energy band Download PDFInfo
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- 229910052814 silicon oxide Inorganic materials 0.000 title claims abstract description 30
- -1 Silicon Oxide Nitride Chemical class 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 56
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 55
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims abstract description 15
- 230000008859 change Effects 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 11
- 238000010276 construction Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 238000005036 potential barrier Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 238000007667 floating Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 229920006395 saturated elastomer Polymers 0.000 description 4
- 230000005641 tunneling Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000005264 electron capture Effects 0.000 description 1
- 238000013213 extrapolation Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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Abstract
The invention provides a BE-SONOS (Band-gap Engineering SONOS (Silicon Oxide Nitride Oxide Semiconductor)) structure device with a tapered energy band. A silicon substrate is provided with a grid electrode with a multi-layer structure, wherein the grid electrode comprises a silicon oxide layer (31), a gradually-changed silicon nitride layer (32), a silicon oxide layer (33), a silicon nitride layer (34), a barrier oxidizing layer (35) and a control grid (36) from bottom to top, and the silicon oxide layer is contacted with the silicon substrate.
Description
Technical field
The present invention relates to microelectronics technology, relate in particular to a kind of have BE-SONOS (Band-gap Engineering SONSO) structure devices that taper can be with and the method that forms this device.
Background technology
Flash memory is a kind of of nonvolatile storage spare, and traditional flash memory utilizes floating boom extremely to store data, because polysilicon is a conductor, floating boom utmost point charge stored is a continuous distribution.In the time of a leakage path, whole floating boom is extremely gone up charge stored and all can be lost through this leakage path.Therefore the biggest obstacle that limits the scaled ability of flash memory is that its tunnel oxide layer thickness can not continue to reduce.Because under thin tunnel oxide situation, the effects such as leakage current that direct Tunneling and stress cause all can propose great challenge to the electric leakage control of memory.The SONOS structure of latest developments replaces original polysilicon stored charge layer with the silicon nitride layer with charge trap ability, because it uses the trapped charge stored charge, so charge stored is a discrete distribution.Such leakage path can not cause big leakage current, so reliability improves greatly.
Typical SONOS structure is made up of silicon substrate (S)-tunnel oxide (O)-charge storage layer silicon nitride (N)-barrier oxide layer (O)-polysilicon gate (S).This structure utilizes the tunnelling of electronics to compile, and wiping of data carried out in the injection in hole.For the speed that makes compiling and wipe improves, need thin tunnel oxide (about 3nm).Yet so thin thickness can reduce the hold facility of electric charge and the durability in compiling/erase process.But the tunnel oxide thicker as if employing compiles and the meeting of wiping needs bigger electric field.Big electric field when wiping can make the electronics of grid arrive the silicon nitride accumulation layer through barrier oxide layer.These injected electrons with reach dynamic balance from the substrate injected holes, cause the saturated of erase state, if bigger voltage can make and wipe and can not carry out, influence the performance of device.How in the operation of low electric field, promote the usefulness of tunnel dielectric layer, realize fast erasing with hold facility and when promoting endurance realization be a new challenge.
People such as Lue (" Non-Volatile Memory Cells, Memory Arrays Including the Same and Method of Operation Cells and Arrays ") in U.S. Pat 2006/0198189A1 disclose a kind of tunnel dielectric layer of BE-SONOS structure of energy band engineering.The technical papers about BE-SONOS that people such as Lue deliver (" BE-SONOS:A Bandgap Engineered SONOS with Excellent Performance and Reliability ". IEEE 2005; " A BE-SONOS (Bandgap Engineered SONOS) NAND for Post-Floating Gate Era Flash Memory " IEEE 2007) performance of this structure is discussed.The BE-SONOS technology has been proved the usefulness that can provide, can realize erasing speed, promotes in the time of hold facility and endurance.
Hang-Ting Lue utilizes silica and silicon nitride to make up U type band structure, replaces the structure of bottom oxidization layer with the ONO layer of the thin silicon nitride of two layers of thin oxide layer folder one deck.Ultra-thin O1/N1/O2 is as a tunneling medium layer that does not have charge trap, and this is that electronics also is not able to do in time limited because catch the thickness that the mean free path of electric charge is greater than this ONO layer, has just passed this layer.N2 is the layer of stored charge, is used for storing the electric charge of injection.O3 is a barrier oxide layer, and it can prevent the injection of gate charge.Ultra-thin " O1/N1/O2 " provides one " tunneling barrier of being modulated "; This potential barrier can suppress direct Tunneling under low electric field; Tunneled holes increases the efficient of wiping to the silicon nitride layer of stored charge because the skew that can be with has efficiently under High-Field.
People such as Wu K H recently control the silicon nitride layer Si/N content ratio of generation through the flow velocity of control reacting gas; Make near the tunnel oxide layer segment to be rich Si silicon nitride layer; And be rich N silicon nitride layer near barrier oxide layer; Si/N is than gradually changing, and final because Silicon-rich is different with the energy gap of rich nitrogen silicon nitride layer, silicon nitride layer has the band structure of taper.Under the P/E of the best operating voltage; The silicon nitride layer of standard silicon nitride layer, Silicon-rich and the silicon nitride layer of Si/N gradual change are tested; The silicon nitride device that discovery has the taper band structure has bigger threshold voltage shift and bigger memory window (band gap of the silicon nitride of Silicon-rich is 3.69ev, and the band gap of the silicon nitride of rich nitrogen is 5.22ev).Endurance through to new unit is tested, and finds that new unit is in P/E circulation 10
6After inferior, do not observe the degeneration of endurance yet.The electric charge hold facility of device does not improve under the room temperature, but because bigger threshold voltage shift arranged, and the utilization extrapolation infers, through still also having the memory window of 1.3 V after 10 years.But the erasing speed of the band structure of this taper is slower, influences the performance of device.（WU?K?H?,?CHIEN?H?C,?CHAN?C?C,?et?al?.?SONOS?device?with?tapered?band?gap?nitride.?IEEE?Transactions?on?Elect?ron?Devices,?2005,?52?(5)?:?987?-?992.）。
Summary of the invention
The present invention is directed to typical B E-SONOS device and only pass bottom oxidization layer in order to make the hole, intermediate thin silicon nitride layer and top oxide layer must reach certain can be with skew.Making tunneled holes is not to be determined by intermediate layer (thin silicon nitride layer) potential barrier for the hole through the skew of being with of middle dielectric layer (thin silicon nitride) just, and the skew of being with of upper strata oxide layer also can influence hole entering charge storage silicon nitride layer when wiping.Reduce the operating voltage when wiping through improving middle dielectric layer, further reduce the injection of gate electron.Make the erasing speed of device, electric charge hold facility and endurance reach synchronous improvement.The middle dielectric layer that the taper band structure of accumulation layer is used for thin ONO layer.Can be with under the effect at erasing voltage in taper, can reach certain and can be with skew, wipe required voltage thereby reduce, suppress since the electronics of the grid that high erasing voltage causes to inject wiping of causing saturated.
In order to realize above-mentioned purpose; A kind of BE-SONOS structure devices that taper can be with that has is provided; Silicon substrate is provided with the grid of sandwich construction; Said grid comprises from bottom to up: silicon oxide layer (31), gradual change silicon nitride layer (32), silicon oxide layer (33), silicon nitride layer (34), barrier oxide layer (35) and control gate (36), said silicon oxide layer contacts with silicon substrate.
In a preferred embodiment of the present invention, said silicon substrate is a P type silicon substrate.
In a preferred embodiment of the present invention; The thickness of said silicon oxide layer (31) is 1.5nm, and the thickness of gradual change silicon nitride layer (32) is that the thickness of 2.0nm, silicon oxide layer (33) is that the thickness of 2nm, silicon nitride layer (34) is that the thickness of 7nm, barrier oxide layer (35) is 9nm.
Another object of the present invention is to provide and forms above-mentioned method with BE-SONOS structure devices that taper can be with; This method comprises: on silicon substrate, successively prepare silicon oxide layer (31), gradual change silicon nitride layer (32), silicon oxide layer (33), silicon nitride layer (34), barrier oxide layer (35) and control gate (36), back etching is removed redundance and is formed grid.
In a preferred embodiment of the present invention; Silicon oxide layer (31) thickness that forms is 1.5nm, and gradual change silicon nitride layer (32) thickness is that 2.0nm, silicon oxide layer (33) thickness are that 2nm, silicon nitride layer (34) thickness are that 7nm, barrier oxide layer (35) thickness are 9nm.
The BE-SONOS device that provides among the present invention has the O/TN/O layer of the gradual change silicon nitride layer that taper can be with through formation; Be implemented in equal side-play amount and tunneled holes is not had under the situation of influence; Reduce the gate voltage when wiping; Can suppress because the injection of the gate electron that causes of high wiping, and then suppress to wipe saturated.
Description of drawings
Fig. 1 is the structural representation with BE-SONOS structure devices that taper can be with provided by the invention.
Fig. 2 be BE-SONOS device with O1/TN1/O2 layer keep charge state can be with sketch map.
Fig. 3 is the BE-SONOS device compiling attitude energy band diagram with O1/TN1/O2 layer.
Fig. 4 be have the O1/TN1/O2 layer BE-SONOS device erase state can be with sketch map.
Embodiment
The silicon nitride layer that the present invention has a taper band structure through utilization is replaced the erase operation voltage that N1 layer in the ONO structure of the O1/N1/O2 in original BE-SONOS device improves the BE-SONOS device.Can be with under the effect of erasing voltage through taper, can reach certain and can be with skew, wipe required voltage thereby reduce, suppress since the gate electron that high erasing voltage causes to inject wiping of causing saturated.
Below have BE-SONOS structure devices and the formation method that taper can be with and explain further details provided by the invention through embodiment so that better understand the present invention creativity and innovation is provided, but embodiment does not limit protection scope of the present invention.
The process that formation has the BE-SONOS structure devices that taper can be with is following:
Preparation one layer thickness is the thin silicon oxide layer 31 (being designated as O1) of 1.5nm on P type silicon substrate 1 earlier; Preparation one layer thickness is the thin silicon nitride layer 32 (being designated as TN1) that has the gradual change of Si/N content of 2.0nm on this silicon oxide layer 31 then, and going up another layer thickness of preparation at the thin gradual change silicon nitride layer 32 of this layer (TN1) then is the thin silicon oxide layer 33 (being designated as O2) of 2nm.On silicon oxide layer 33, prepare the thick silicon nitride layer with charge storage 34 (being designated as N2) of one deck 7nm then; On this layer charge storage silicon nitride layer, generate the thick barrier oxide layer 35 (being designated as O3) of one deck 9nm, go up preparation polysilicon control grid 36 in barrier oxide layer (O3) at last through thermal oxidation.Through above process, prepare the stacked gate architectures of improving tunnel oxide in the BE-SONOS structure, the BE-SONOS device architecture of formation is as shown in Figure 1.
Fig. 2 is that the BE-SONOS structure devices can be with sketch map under null field.Because big thickness makes the electronics of preservation and the hole of substrate can not pass the O1/TN1/O2 layer after the match low, thereby keeps stored charge hold facility preferably.
Fig. 3 is the BE-SONOS device compiling attitude energy band diagram with O1/TN1/O2 layer.(Fu Le-Nuo Dehan) tunnelling realizes, so middle gradual change silicon nitride layer is to almost not influence of compiling because compiling utilizes FN.And because this layer gradual change silicon nitride 32 is very thin; When electronics passes through this layer silicon nitride 34; The mean free path of its electron capture is bigger than gradual change silicon nitride layer 32; Even electronics can not caught by silicon nitride layer 34, so gradual change silicon nitride 32 can not influence the speed of compiling through this gradual change silicon nitride 32 yet like this.
Fig. 4 be have the O1/TN1/O2 layer BE-SONOS device erase state can be with sketch map.When wiping, the TN1 layer has the band structure of silicon nitride layer of taper band structure under negative voltage, has a skew that makes progress, and makes originally the upwards skew of edge near the valence band of top silicon oxide layer 33 (O2).When the valence band of the broad-band gap valence-band edge that can be with when taper and this level of narrow band gap valence-band edge level and gradual change silicon nitride layer and the valence band level of substrate silicon, gradual change silicon nitride layer 32 (TN1) is to the just not influence of tunnelling in hole.Simultaneously, also not influence of the tunnelling that can be with the skew electronics that also reaches certain of top silicon oxide layer 33 (being designated as O2).Thereby do not need too big voltage just can realize to be with bigger skew.
Compare tangible erasing speed and be because silicon and silicon nitride interface for the potential barrier in hole (< 1.9eV) less than silicon and silicon oxide interface potential barrier (4.6eV) for the hole.Under High-Field, this is for the big potential barrier difference in hole, produces big can be with skew, make the hole only fast a tunnelling cross the O1 layer.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (5)
1. one kind has the BE-SONOS structure devices that taper can be with, and it is characterized in that silicon substrate is provided with the grid of sandwich construction, and said grid comprises from bottom to up:
Silicon oxide layer (31), gradual change silicon nitride layer (32), silicon oxide layer (33), silicon nitride layer (34), barrier oxide layer (35) and control gate (36), said silicon oxide layer contacts with silicon substrate.
2. according to the said BE-SONOS structure devices of claim 1, said silicon substrate is a P type silicon substrate.
3. according to the said BE-SONOS structure devices of claim 1; The thickness of said silicon oxide layer (31) is 1.5nm, and the thickness of gradual change silicon nitride layer (32) is that the thickness of 2.0nm, silicon oxide layer (33) is that the thickness of 2nm, silicon nitride layer (34) is that the thickness of 7nm, barrier oxide layer (35) is 9nm.
4. one kind forms the said method with BE-SONOS structure devices that taper can be with of claim 1; It is characterized in that; On silicon substrate, successively prepare silicon oxide layer (31), gradual change silicon nitride layer (32), silicon oxide layer (33), silicon nitride layer (34), barrier oxide layer (35) and control gate (36), back etching is removed redundance and is formed grid.
5. according to the said method of claim 4; It is characterized in that; Silicon oxide layer (31) thickness that forms is 1.5nm, and gradual change silicon nitride layer (32) thickness is that 2.0nm, silicon oxide layer (33) thickness are that 2nm, silicon nitride layer (34) thickness are that 7nm, barrier oxide layer (35) thickness are 9nm.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1877857A (en) * | 2005-06-10 | 2006-12-13 | 旺宏电子股份有限公司 | Methods of operating P-channel non-volatile memory devices |
| CN101438392A (en) * | 2005-01-26 | 2009-05-20 | 飞思卡尔半导体公司 | Non-volatile nanocrystal memory and method therefor |
| US20090140318A1 (en) * | 2007-12-03 | 2009-06-04 | Zhong Dong | Nonvolatile memories with higher conduction-band edge adjacent to charge-trapping dielectric |
| US20100062595A1 (en) * | 2008-09-05 | 2010-03-11 | Juwan Lim | Nonvolatile memory device and method of forming the same |
| CN101901811A (en) * | 2009-04-21 | 2010-12-01 | 旺宏电子股份有限公司 | Bandgap engineered charge trapping memory in two-transistor NOR architecture |
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- 2012-05-22 CN CN2012101589029A patent/CN102709315A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101438392A (en) * | 2005-01-26 | 2009-05-20 | 飞思卡尔半导体公司 | Non-volatile nanocrystal memory and method therefor |
| CN1877857A (en) * | 2005-06-10 | 2006-12-13 | 旺宏电子股份有限公司 | Methods of operating P-channel non-volatile memory devices |
| US20090140318A1 (en) * | 2007-12-03 | 2009-06-04 | Zhong Dong | Nonvolatile memories with higher conduction-band edge adjacent to charge-trapping dielectric |
| US20100062595A1 (en) * | 2008-09-05 | 2010-03-11 | Juwan Lim | Nonvolatile memory device and method of forming the same |
| CN101901811A (en) * | 2009-04-21 | 2010-12-01 | 旺宏电子股份有限公司 | Bandgap engineered charge trapping memory in two-transistor NOR architecture |
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Application publication date: 20121003 |