CN102709314A - Physically-isolated silicon nanocrystalline double-bit storage structure and preparation method thereof - Google Patents
Physically-isolated silicon nanocrystalline double-bit storage structure and preparation method thereof Download PDFInfo
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- CN102709314A CN102709314A CN2012101587254A CN201210158725A CN102709314A CN 102709314 A CN102709314 A CN 102709314A CN 2012101587254 A CN2012101587254 A CN 2012101587254A CN 201210158725 A CN201210158725 A CN 201210158725A CN 102709314 A CN102709314 A CN 102709314A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 48
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 48
- 239000010703 silicon Substances 0.000 title claims abstract description 48
- 238000003860 storage Methods 0.000 title claims abstract description 37
- 238000002360 preparation method Methods 0.000 title abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 238000002955 isolation Methods 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 239000002159 nanocrystal Substances 0.000 claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 45
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 40
- 230000003647 oxidation Effects 0.000 claims description 26
- 238000007254 oxidation reaction Methods 0.000 claims description 26
- 229920005591 polysilicon Polymers 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 21
- 230000008520 organization Effects 0.000 claims description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000001020 plasma etching Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 3
- PBZHKWVYRQRZQC-UHFFFAOYSA-N [Si+4].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O Chemical compound [Si+4].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O PBZHKWVYRQRZQC-UHFFFAOYSA-N 0.000 abstract 2
- 230000001590 oxidative effect Effects 0.000 abstract 2
- 238000000151 deposition Methods 0.000 description 7
- 238000011065 in-situ storage Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 229910003915 SiCl2H2 Inorganic materials 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 239000008280 blood Substances 0.000 description 1
- 210000004369 blood Anatomy 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 229910021423 nanocrystalline silicon Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000008279 sol Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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Abstract
The invention discloses a physically-isolated silicon nanocrystalline double-bit storage structure and a preparation method of the physically-isolated silicon nanocrystalline double-bit storage structure. The device comprises a grid electrode with a side wall, which is formed on a P-type substrate; substrates at two sides of the grid electrode are respectively provided with a source region and a drain region; the device is characterized in that the grid electrode comprises a physical isolation region and two storage regions, wherein the physical isolation region comprises a bottom face and polycrystalline silicon with the side face covered by an isolating silicon oxide layer; the two storage regions are arranged at the two sides of the physical isolation region; each storage region comprises a bottom silicon oxide layer, a silicon nitrate layer and a barrier oxidizing layer, which are sequentially overlapped in a vertical direction; and the silicon nitrate layer contains silicon nanocrystal and the polycrystalline silicon is deposited on the barrier oxidizing layer. The double-bit storage structure is different from the previous structure and the physical isolation region can improve a crosstalk problem of storage bits.
Description
Technical field
The present invention relates to a kind of semiconductor device, relate in particular to a kind of physically-isolated silicon nanocrystal dibit storage organization and preparation method thereof.
Background technology
Along with the high speed development of traditional cmos vlsi technology, flash memory technology is also towards low-power consumption, and the direction of low-work voltage and high storage density develops.But because floating polysilicon grid charge stored is a continuous distribution; In the time of a leakage path; Whole floating boom is extremely gone up charge stored and all can be lost through this leakage path; Therefore the biggest obstacle that limits the scaled ability of flash memory is that its tunnel oxide layer thickness can not continue to reduce, because under thin tunnel oxide situation, the effects such as leakage current that direct Tunneling and stress cause all can propose great challenge to the electric leakage control of memory.The SONOS structure of latest developments; Silicon nitride layer with having the charge trap ability replaces original polysilicon stored charge layer, because it uses the trapped charge stored charge, so charge stored is a discrete distribution; Like this, a leakage path can not cause big leakage current.Therefore reliability improves greatly, and tunnel oxide can continue attenuate, reduces operating voltage and power consumption.
Another purposes of the mode of this separation of charge storage is exactly to realize the storage of multidigit information, utilizes the information of leaking two bits of silicon nitride layer storage at two ends near the source like NROM.Though this method has improved the density of storage, because charge storage in same layer, is stored in the electric charge at two ends because a horizontal distribution is arranged.So when device size continues to reduce, crosstalk phenomenon takes place easily between the two bits of storage respectively, influence reading of institute's deposit data, storage density therefore is difficult to further improve.In the SONOS device that size is constantly dwindled, the cross direction profiles that needs to suppress stored charge under the high temperature keeps memory window.At present, there has been human in-situ depositing method to be injected into silicon nitride layer to Si2NCs and made the SONOS device.The device of this structure shows the memory window of 6V, good compiling/wipe and charge-retention property.They have also compared the Si that adopts distinct methods preparations such as ion implantation, gel-sol method and direct chemical sedimentation simultaneously
2The merits and demerits of NCs, but all be not so good as the Si that the in-situ depositing method is injected
2The NCs quality is good, density is high, size is all even is easy to control, and the in-situ depositing method is simple, realizes that easily cost is low, and is good with the CMOS compatibility, continuing to dwindle and provide than large space for device size.The somebody utilizes that the in-situ depositing mode makes contains the nanocrystalline silicon nitride layer of Si, can the obtaining easily of multidigit with two bit manipulation modes, and very fast compiling and erasing speed are arranged.Through (60s 90s), finds that optimized structure is the nanocrystalline deposit of Si of 30s for 10s, 30s with different deposition time.This device has maximum memory window, compiles fast and erasing speed, and negligible two effects, almost negligible drain electrode and source electrode disturbance and long data hold time are 10
4Still have the memory window of 3V after the inferior circulation.
Though containing the anti-gate pole of the device of nanocrystalline SONOS structure increases with anti-drain electrode interference performance to some extent; But owing to moving of the horizontal direction that has same layer charge; And nanocrystalline between self close together also can influence the performance of device; The reliability of device is affected, and durability and electric charge hold facility are all relatively poor.
Therefore, provide a kind of physically-isolated silicon nanocrystal dibit storage organization that can effectively improve the SONOS device reliability, improve durability and electric charge hold facility and preparation method thereof just to seem particularly important.
Summary of the invention
The objective of the invention is to suppress effectively the cross talk effects between the dibit storage data among the NROM, improve the reliability of nanocrystalline SONOS device,, be easy to realize and practice thrift cost simultaneously with traditional CMOS process compatible.
The present invention discloses a kind of physically-isolated silicon nanocrystal dibit storage organization, comprises the grid with side wall that is formed on the P type substrate, and the substrate of said grid both sides has source, drain region respectively, and wherein, said grid comprises:
The physical isolation district comprises bottom surface and the side polysilicon by isolation oxidation silicon layer parcel;
Two memory blocks; Be arranged at both sides, said physical isolation district, said memory block comprises by bottom silicon oxide layer folded mutually successively on the vertical direction, silicon nitride layer and barrier oxidation silicon layer; Contain silicon nanocrystal in the said silicon nitride layer, deposition has polysilicon on the said barrier oxidation silicon layer.
Above-mentioned dibit storage organization wherein, accompanies the thin silicon nitride of one deck in the silicon oxide layer of said bottom, form silica-silicon-nitride and silicon oxide structure folded mutually successively on the vertical direction.
Above-mentioned dibit storage organization, wherein, said side wall comprises near the monox lateral wall of said memory block and is positioned at the outer silicon nitride side wall of said monox lateral wall.
According to an aspect of the present invention, also disclose a kind of method for preparing above-mentioned dibit storage organization, wherein, comprise the steps:
Substrate is provided and makes shallow trench isolation and leave;
Generate bottom silicon oxide layer-silicon nitride layer and barrier oxidation silicon layer successively, comprise the silicon nanocrystal layer in the said silicon nitride layer;
On said barrier oxidation silicon layer, cover one deck sacrificial silicon nitride layer.
Carve isolated area, and growth one deck isolation oxidation silicon layer covers said isolated area;
The deposit polysilicon layer is removed unnecessary polysilicon after filling the physics isolated area, terminate in sacrificial silicon nitride layer;
Remove the sacrificial silicon nitride layer of isolated area both sides, then at isolated area two outgrowth polysilicons and carve the grid length that needs,
And be alignment with remaining polysilicon, carve the dibit storage area that needs;
Make side wall and formation source, drain region.
Above-mentioned method, wherein, said bottom silicon oxide layer and barrier oxidation silicon layer generate through thermal oxidation.
Above-mentioned method, wherein, the silicon nanocrystal of said silicon nitride layer is grown according to the original position mode.
Above-mentioned method, wherein, the making in said side wall and source, drain region comprises and utilizes the anisotropic plasma etching; Form the silicon dioxide side wall, and carry out the shallow doping of source-drain area, utilize the anisotropic plasma etching again; Form the silicon nitride side wall, and carry out doping and the annealing that leaks in the source.
Advantage of the present invention is:
Through in forming the SONOS configuration process, the silicon nitride layer of formation silicon nanocrystal is because much more nanocrystalline can providing and darker trap level can realize storing the more ability and better electric charge hold facility of multi-charge;
Utilize sacrificial silicon nitride layer to come the layer that stops, effectively controlling the shape of polysilicon the cmp of polysilicon;
Utilize two polysilicons on the bank bit as the autoregistration that forms required bank bit, can form required bank bit, use photoetching less, practice thrift cost;
By the dibit bank bit that the physical isolation district keeps apart, can suppress to store crosstalking of data, the reliability of device is enhanced.
Description of drawings
Through describing the accompanying drawing of being done with reference to non-limiting example of the present invention, the present invention's understanding that will improve, wherein;
Fig. 1 to Fig. 5 shows according to an embodiment of the invention, prepares the sketch map of the process of physically-isolated silicon nanocrystal dibit storage organization.
Embodiment
The present invention can implement with some forms under the situation that does not deviate from its spirit and substantive characteristics; Should be understood that; Above-mentioned example can't receive the restriction of aforementioned details, except as otherwise noted, should briefly understand its spirit and the defined scope of claim as adding; Therefore, all fall into the set of said claim and the variation and being equal to of distortion or similar set and scope of scope will be comprised by said accessory claim.
Earlier with reference to shown in Figure 5; The physically-isolated silicon nanocrystal dibit storage organization that completes; Particularly, physically-isolated silicon nanocrystal 112 dibit storage organizations of the present invention comprise the grid with side wall that is formed on the P type substrate 100 (among Fig. 5 not label), and the substrate 100 of said grid both sides has source, drain region 200,300 respectively; Wherein, said grid comprises:
Physical isolation district (among Fig. 5 not label) comprises bottom surface and the side polysilicon 106 by isolation oxidation silicon layer 105 parcels;
Two memory blocks (among Fig. 5 not label); Be arranged at both sides, said physical isolation district; Said memory block comprises by bottom silicon oxide layer 101 folded mutually successively on the vertical direction; Silicon nitride layer 102 and barrier oxidation silicon layer 103 contain silicon nanocrystal 112 in the said silicon nitride layer 102, and deposition has polysilicon 106 on the said barrier oxidation silicon layer 103.
In a variant; Bottom silicon oxide layer 101 can be changed to the thin ONO layer that does not have the charge trap ability; For the dibit storage of NROM formula, can carry out the lifting that physical isolation realizes performance equally, particularly; Accompany the thin silicon nitride (not shown among Fig. 5) of one deck in the said bottom silicon oxide layer 101, form silica-silicon-nitride and silicon oxide structure folded mutually successively on the vertical direction.
As shown in Figure 5, wherein, said side wall comprises near the silicon dioxide side wall 107 of said memory block and is positioned at the silicon nitride side wall 108 outside the said silicon dioxide side wall 107.
Further,, also disclose a kind of method for preparing above-mentioned dibit storage organization, wherein, comprise the steps: to provide substrate 100 and make shallow trench isolation from (not shown in figure 1) in conjunction with referring to figs. 1 to Fig. 5;
Generate bottom silicon oxide layer 101-silicon nitride layer 102 and barrier oxidation silicon layer 103 successively, comprise 112 layers of silicon nanocrystals in the said silicon nitride layer 102; On said barrier oxidation silicon layer 103, cover one deck sacrificial silicon nitride layer 104, as shown in Figure 1, wherein; Bottom silicon oxide layer 101 keeps layer as electric charge; Said silicon nitride layer 102 utilizes the nanocrystalline deep energy level that causes as charge storage layer, can store more electric charge; Said barrier oxidation silicon layer 103 keeps layer and the layer that prevents that grid from injecting as electric charge, stops layer when said sacrificial silicon nitride layer 104 is used for as multi crystal silicon chemical mechanical milling;
Carve isolated area in order to isolating two memory locations, and growth one deck isolation oxidation silicon layer 105 covers said isolated area, said isolation oxidation silicon layer 105 is used for suppressing polysilicon to the influence of ONO layer and the leakage of store electrons; The deposit polysilicon is removed unnecessary polysilicon 106 for 106 layers after filling the physics isolated area, terminate in sacrificial silicon nitride layer 104, sees Fig. 2;
Remove the sacrificial silicon nitride layer 104 of isolated area both sides again, then at isolated area two outgrowth polysilicons 106 and carve the grid length that needs, as shown in Figure 3;
And be alignment with remaining polysilicon 106, carve the dibit storage area that needs;
Make side wall and formation source, drain region 200,300.
In a specific embodiment, said bottom silicon oxide layer 101 generates through thermal oxidation with barrier oxidation silicon layer 103.
Further, the silicon nanocrystal 112 of said silicon nitride layer 102 is grown according to the original position mode, and art technology can be with reference to (Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nano-crystals. IEEE TRANSACTIONS ON LECTRON DEVICES; VOL. 57; NO. 8, AUGUST 2010) in method, preparation bottom silicon nitride layer (3nm earlier; NH3 (130sccm) SiCl2H2 (30sccm) LPCVD; 780 degrees centigrade), prepare silicon nanocrystal (SiCl2H2 (10 sccm) 30s) with in-situ method then, be top silicon nitride (4nm then; NH3 (130sccm) SiCl2H2 (30sccm) LPCVD, 780 degrees centigrade).
As shown in Figure 5; The making in said side wall and source, drain region 200,300 comprises and utilizes the anisotropic plasma etching, forms the silicon dioxide side wall, and this side wall is used for the autoregistration of the shallow doping of source-drain area; Carry out the shallow doping 201,301 of source-drain area again; Utilize the anisotropic plasma etching again, form the silicon nitride side wall, and carry out doping and the annealing that leaks in the source.
More than preferred embodiment of the present invention is described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention; Or being revised as the equivalent embodiment of equivalent variations, this does not influence flesh and blood of the present invention.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (7)
1. a physically-isolated silicon nanocrystal dibit storage organization comprises the grid with side wall that is formed on the P type substrate, and the substrate of said grid both sides has source, drain region respectively, it is characterized in that, said grid comprises:
The physical isolation district comprises bottom surface and the side polysilicon by isolation oxidation silicon layer parcel;
Two memory blocks; Be arranged at both sides, said physical isolation district, said memory block comprises by bottom silicon oxide layer folded mutually successively on the vertical direction, silicon nitride layer and barrier oxidation silicon layer; Contain silicon nanocrystal in the said silicon nitride layer, deposition has polysilicon on the said barrier oxidation silicon layer.
2. dibit storage organization according to claim 1 is characterized in that, accompanies the thin silicon nitride of one deck in the silicon oxide layer of said bottom, forms silica-silicon-nitride and silicon oxide structure folded mutually successively on the vertical direction.
3. dibit storage organization according to claim 1 and 2 is characterized in that, said side wall comprises near the silicon dioxide side wall of said memory block and is positioned at the outer silicon nitride side wall of said silicon dioxide side wall.
4. a method for preparing any described dibit storage organization in the claim 1 to 3 is characterized in that, comprises the steps:
Substrate is provided and makes shallow trench isolation and leave;
Generate bottom silicon oxide layer-silicon nitride layer and barrier oxidation silicon layer successively, comprise the silicon nanocrystal layer in the said silicon nitride layer;
On said barrier oxidation silicon layer, cover one deck sacrificial silicon nitride layer;
Carve isolated area, and growth one deck isolation oxidation silicon layer covers said isolated area;
The deposit polysilicon layer is removed unnecessary polysilicon after filling the physics isolated area, terminate in sacrificial silicon nitride layer;
Remove the sacrificial silicon nitride layer of isolated area both sides, then at isolated area two outgrowth polysilicons and carve the grid length that needs,
And be alignment with remaining polysilicon, carve the dibit storage area that needs;
Make side wall and formation source, drain region.
5. method according to claim 4 is characterized in that, said bottom silicon oxide layer and barrier oxidation silicon layer generate through thermal oxidation.
6. method according to claim 4 is characterized in that the silicon nanocrystal of said silicon nitride layer is grown according to the original position mode.
7. method according to claim 4; It is characterized in that the making of said side wall and source-drain area comprises and utilizes the anisotropic plasma etching, forms the silicon dioxide side wall; And carry out the shallow doping of source-drain area; Utilize the anisotropic plasma etching again, form the silicon nitride side wall, and carry out doping and the annealing that leaks in the source.
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- 2012-05-22 CN CN2012101587254A patent/CN102709314A/en active Pending
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| US20020076850A1 (en) * | 2000-12-19 | 2002-06-20 | Sadd Michael A. | Device structure for storing charge and method therefore |
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Application publication date: 20121003 |