CN102709287A - Non-volatile memory cell and manufacturing method thereof - Google Patents
Non-volatile memory cell and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to a non-volatile memory cell and a manufacturing method thereof. The non-volatile memory cell comprises a substrate, a tunneling dielectric layer, floating gates, isolation structures, inter-gate dielectric layers, control gates, a first doped region and a second doped region, wherein the substrate is provided with a plurality of channels; the tunneling dielectric layer is arranged on the substrate; the floating gates are arranged on the tunneling dielectric layer; the isolation structures are positioned in the channels and comprise first insulating layers and second insulating layers; the second insulating layers are positioned in the channels; the first insulating layers are positioned between the second insulating layers and the substrate and extend from the side walls of the channels to part of side walls of the floating gates; the height of the first insulating layers is greater than that of the second insulating layers; and the first insulating layers and the second insulating layers are made of different materials. Through the isolation structures of the non-volatile memory cell, the problem of leakage current caused by the breakdown of electrons from the substrate to the inter-gate dielectric layers and the control gates can be solved, and the problem that two floating gates interfere with each other can be solved.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacturing approach thereof, particularly relate to a kind of non-volatile memory cell and manufacturing approach thereof.
Background technology
The stack memory cell has superior data preservation characteristic, is one of main product of non-volatile memory cell.The stack memory cell comprises dielectric layer between substrate, tunnel oxide, floating grid, grid, control grid and source area and drain region.Along with the raising of element integration (integration), component size is constantly dwindled, and the size of each member is more and more little in the element, and distance to each other is also more and more near.Thus, adjacent two floating grids will produce parasitic capacitance, the serious disturbance of deriving problem with isolation structure in order to isolated two floating grids.Yet, if solve the problem that adjacent floating grid disturbs and the isolation structure height between the floating grid reduced, can cause the breakdown problem between control grid and the substrate again, and cause the problem of element leakage current.
This shows that above-mentioned existing non-volatile memory cell and manufacturing approach thereof obviously still have inconvenience and defective, and demand urgently further improving in product structure, manufacturing approach and use.In order to solve the problem of above-mentioned existence; Relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly; But do not see always that for a long time suitable design is developed completion; And common product and method do not have appropriate structure and method to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new non-volatile memory cell and manufacturing approach thereof, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Summary of the invention
The objective of the invention is to; Overcome the defective that existing non-volatile memory cell and manufacturing approach thereof exist; And a kind of new non-volatile memory cell and manufacturing approach thereof are provided; Technical problem to be solved is to make it can reduce the interference between floating grid and the floating grid, and avoids electronics to puncture from substrate that dielectric layer is very suitable for practicality to controlling grid between grid.
The object of the invention and solve its technical problem and adopt following technical scheme to realize.A kind of non-volatile memory cell that proposes according to the present invention comprises: dielectric layer and control grid between substrate, tunneling dielectric layer, floating grid, isolation structure, grid.Substrate has a plurality of irrigation canals and ditches.Tunneling dielectric layer is disposed in the substrate.Floating grid is disposed on the tunneling dielectric layer.Isolation structure is positioned at irrigation canals and ditches.Isolation structure comprises first insulating barrier and second insulating barrier.Second insulating barrier is arranged in irrigation canals and ditches.First insulating barrier extends the partial sidewall that covers floating grid between second insulating barrier and substrate and from trench sidewall.The height of first insulating barrier is higher than the height of second insulating barrier.The control grid is disposed on floating grid and the isolation structure.Dielectric layer is disposed between floating grid and the control grid and between isolation structure and the control grid between grid.
The object of the invention and solve its technical problem and also can adopt following technical measures further to realize.
Aforesaid non-volatile memory cell, the material of wherein said first insulating barrier is different with the material of above-mentioned second insulating barrier.
Aforesaid non-volatile memory cell, the material of wherein said first insulating barrier comprises silica or silicon oxynitride.
Aforesaid non-volatile memory cell, the material of wherein said second insulating barrier comprise spin-on glasses (Spin-on-glass) or spin-coating dielectric material (Spin-on-dielectric).
Aforesaid non-volatile memory cell, the thickness of wherein said first insulating barrier are 50 dust to 300 dusts.
Aforesaid non-volatile memory cell, the height of wherein said first insulating barrier are higher than surface 150 to 300 dusts of above-mentioned tunneling dielectric layer.
Aforesaid non-volatile memory cell, the end face of wherein said first insulating barrier are the inclined plane.
Aforesaid non-volatile memory cell, the surface of the height of wherein said second insulating barrier and this tunneling dielectric layer is suitable, and the surface of the surface of this second insulating barrier and this tunneling dielectric layer differs less than 100 dusts.
Aforesaid non-volatile memory cell also comprises lining, between first insulating barrier and substrate.
The object of the invention and solve its technical problem and also adopt following technical scheme to realize.The manufacturing approach of a kind of non-volatile memory cell that proposes according to the present invention comprises the following steps.In substrate, form tunneling dielectric layer, first conductor layer and cover curtain layer in regular turn.Then, patterning cover curtain layer, first conductor layer and tunneling dielectric layer, and in substrate, form a plurality of irrigation canals and ditches.Then, in substrate, form first insulating barrier, this first insulating barrier covers cover curtain layer, cover curtain layer sidewall, the first conductor layer sidewall, tunneling dielectric layer sidewall and irrigation canals and ditches inwall.Afterwards, in substrate and first coated insulating layer cover second insulating barrier., carry out first remove step, remove cover curtain layer above second insulating barrier and first insulating barrier thereafter.Then; Carry out second again and remove step; Remove part first insulating barrier, part second insulating barrier and cover curtain layer; Make first insulating barrier that stays extend the partial sidewall that covers floating grid, and the height of first insulating barrier is higher than second insulating barrier, first insulating barrier that stays and second insulating barrier formation isolation structure from trench sidewall.Afterwards, forming the dielectric layer and second conductor layer between grid in the substrate in regular turn.Then, dielectric layer, first conductor layer and tunneling dielectric layer between patterning second conductor layer, grid make second conductor layer form a plurality of control grids, and first conductor layer forms a plurality of floating grids.
The object of the invention and solve its technical problem and also can adopt following technical measures further to realize.
The manufacturing approach of aforesaid non-volatile memory cell; Wherein said second removes step comprises with the cover curtain layer being the cover curtain in regular turn; Remove part first insulating barrier and part second insulating barrier; Make the sidewall of cover curtain layer expose out, remove cover curtain layer and serve as cover curtain with first conductor layer, remove part first insulating barrier and part second insulating barrier with etching solution, etching solution is higher than the rate of etch for first insulating barrier for the rate of etch of second insulating barrier.
The manufacturing approach of aforesaid non-volatile memory cell wherein is the cover curtain with the cover curtain layer, and the method that removes part first insulating barrier and part second insulating barrier comprises anisotropic etch process.
The manufacturing approach of aforesaid non-volatile memory cell, wherein said first to remove step be to implement with chemical mechanical milling tech or etch back process.
The manufacturing approach of aforesaid non-volatile memory cell; The step that wherein forms cover curtain layer comprises: forming the first cover curtain material layer on the conductor layer and on first cover curtain layer, forming the second cover curtain material layer; And remove step and more comprise and remove second cover curtain layer carrying out first, expose first cover curtain layer.
The manufacturing approach of aforesaid non-volatile memory cell, the material that wherein forms first insulating barrier comprises silica or silicon oxynitride.
The manufacturing approach of aforesaid non-volatile memory cell, the material that wherein forms second insulating barrier comprises spin-on glasses or spin-coating dielectric material.
The manufacturing approach of aforesaid non-volatile memory cell; Wherein said second remove step make part second insulating barrier height and tunneling dielectric layer the surface quite, and the surface of the surface of this second insulating barrier and this tunneling dielectric layer highly differs less than 100 dusts.
The manufacturing approach of aforesaid non-volatile memory cell, also be included in form first insulating barrier before, between first insulating barrier and substrate, form lining.
The present invention compared with prior art has tangible advantage and beneficial effect.By technique scheme, non-volatile memory cell of the present invention and manufacturing approach thereof have advantage and beneficial effect at least:
Non-volatile memory cell of the present invention is by first insulating barrier and the height of second insulating barrier that are provided with in the isolation structure; Let the height of second insulating barrier be higher than the height of second insulating barrier near the height of the height of tunneling dielectric layer and first insulating barrier; Can avoid accompanying bulky insulating barrier between two floating grids, causing therebetween, coupling capacitance becomes big and makes interference therebetween become big.In addition, also can avoid electronics to puncture between grid dielectric layer to the leakage problem of controlling grid from substrate.
In sum, the invention relates to a kind of non-volatile memory cell and manufacturing approach thereof.This non-volatile memory cell comprises: dielectric layer, control grid and first doped region and second doped region between substrate, tunneling dielectric layer, floating grid, isolation structure, grid.Substrate has a plurality of irrigation canals and ditches.Tunneling dielectric layer is disposed in the substrate.Floating grid is disposed on the tunneling dielectric layer.Isolation structure is positioned at irrigation canals and ditches.Isolation structure comprises first insulating barrier and second insulating barrier.Second insulating barrier is arranged in irrigation canals and ditches.First insulating barrier extends the partial sidewall that covers floating grid between second insulating barrier and substrate and from trench sidewall, it highly is higher than the height of second insulating barrier, and its material with second insulating barrier is different.The present invention has obvious improvement technically, and has tangible good effect, really is the new design of a novelty, progress, practicality.
Above-mentioned explanation only is the general introduction of technical scheme of the present invention; Understand technological means of the present invention in order can more to know; And can implement according to the content of specification, and for let of the present invention above-mentioned with other purposes, feature and advantage can be more obviously understandable, below special act preferred embodiment; And conjunction with figs., specify as follows.
Description of drawings
Fig. 1 is the vertical view of a kind of non-volatile memory cell of one embodiment of the invention.
Fig. 2 A to Fig. 2 H is the flow process generalized section of the non-volatile memory cell that illustrated of embodiment of the invention shop drawings 1, and it is the generalized section of Fig. 1 along the II-II line.
Fig. 3 A to Fig. 3 H is the flow process generalized section of the non-volatile memory cell that illustrated of embodiment of the invention shop drawings 1, and it is the generalized section of Fig. 1 along the III-III line.
100: substrate 110: tunneling dielectric layer
110 ', 130b ': 120: the first conductor layers in surface
120a: floating grid 122: cover curtain layer
126: the second cover curtains of 124: the first cover curtain material layers material layer
130: isolation structure 130a: first insulating barrier
130b: the second insulating barrier 130a ': top
130c: lining 140: dielectric layer between grid
150: the second conductor layer 150a: control grid
160: irrigation canals and ditches 170,180: doped region
200: active region
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention; Below in conjunction with accompanying drawing and preferred embodiment; To non-volatile memory cell and its embodiment of manufacturing approach, structure, method, step, characteristic and the effect thereof that proposes according to the present invention, specify as after.
Relevant aforementioned and other technology contents, characteristics and effect of the present invention can be known to appear in the following detailed description that cooperates with reference to graphic preferred embodiment.Through the explanation of embodiment, when can being to reach technological means that predetermined purpose takes and effect to obtain one more deeply and concrete understanding to the present invention, yet the appended graphic usefulness that only provides reference and explanation be not to be used for the present invention is limited.
Fig. 1 is the vertical view of a kind of non-volatile memory cell of one embodiment of the invention.Fig. 2 A to Fig. 2 H is the flow process generalized section of the non-volatile memory cell that illustrated of embodiment of the invention shop drawings 1, and it is the generalized section of Fig. 1 along the II-II line.Fig. 3 A to Fig. 3 H is the flow process generalized section of the non-volatile memory cell that illustrated of embodiment of the invention shop drawings 1, and it is the generalized section of Fig. 1 along the III-III line.
See also shown in Fig. 1, Fig. 2 A and Fig. 3 A, in substrate 100, form tunneling dielectric layer 110.Substrate 100 for example be whole for the semiconductor-based end, whole for have on semiconducting compound substrate or the insulating barrier the semiconductor-based end (semiconductor over insulator, SOI).Semiconductor for example is the atom for example silicon or the germanium of IVA family.Semiconducting compound for example is the formed semiconducting compound of the atom of IVA family, for example is carborundum or germanium silicide, or IIIA family atom and the formed semiconducting compound of VA family atom, for example is GaAs.Substrate 100 can have doping, and the doping of substrate 100 can be P type or N type.The doping of P type can be an IIIA family ion, for example is the boron ion.It can be that VA family ion for example is arsenic or phosphorus that the N type mixes.
Tunneling dielectric layer 110 can be to be made up of single material layer.Single material layer for example is advanced low-k materials or high dielectric constant material.Advanced low-k materials is meant that dielectric constant is lower than 4 dielectric material, for example is silica or silicon oxynitride.High dielectric constant material is meant that dielectric constant is higher than 4 dielectric material, for example is HfAlO, HfO
2, Al
2O
3Or Si
3N
4Tunneling dielectric layer 110 also can be selected to improve injection current according to energy gap engineering theory (band-gap engineering (BE) theory), makes sequencing double stacked structure or multiple-level stack structure faster.The double stacked structure example is the double stacked structure (representing with advanced low-k materials/high dielectric constant material) formed of advanced low-k materials and high dielectric constant material in this way, for example is silica/HfSiO, silica/HfO
2Or silica/silicon nitride.The multiple-level stack structure example is the multiple-level stack structure (representing with advanced low-k materials/high dielectric constant material/advanced low-k materials) formed of advanced low-k materials, high dielectric constant material and advanced low-k materials in this way, for example is silicon oxide/silicon nitride/silicon oxide or silica/Al
2O
3/ silica.The formation method of tunneling dielectric layer 110 for example is thermal oxidation method or chemical vapour deposition technique.
Then, on tunneling dielectric layer 110, form first conductor layer 120.The material of first conductor layer 120 for example is DOPOS doped polycrystalline silicon, multi-crystal silicification metal or its stack layer that is combined into, and the formation method for example is to utilize chemical vapour deposition technique or physical vaporous deposition.
Afterwards, on first conductor layer 120, form cover curtain layer 122.Cover curtain layer 122 can be homogenous material layer or double layer material layer.In one embodiment, the formation method of cover curtain layer 122 is included in and forms the first cover curtain material layer 124 on first conductor layer 120 earlier, on the first cover curtain material layer 124, forms the second cover curtain material layer 126 then.The material of the first cover curtain material layer 124 for example is a silicon nitride.The material of the second cover curtain material layer 126 for example is a silica.The second cover curtain material layer 126 is used to protect the first cover curtain material layer 124, makes it can possess its shape and enough thickness.
Then, see also shown in Fig. 2 B and Fig. 3 B, patterning cover curtain layer 122, first conductor layer 120, tunneling dielectric layer 110, and in substrate 100, form a plurality of irrigation canals and ditches 160, its mode that can adopt for example is little shadow and etching.Be the active region 200 of substrate 100 beyond the irrigation canals and ditches 160.
Afterwards, in substrate 100, form the first insulating barrier 130a, cover irrigation canals and ditches 160 inwalls and extend and cover on the cover curtain layer 122.Afterwards, forming the second insulating barrier 130b in the substrate 100 and on the first insulating barrier 130a.The material of the second insulating barrier 130b is different with the material of the first insulating barrier 130a.In one embodiment, the material of the first insulating barrier 130a for example is silica or silicon oxynitride.The formation method of the first insulating barrier 130a for example is high-temperature thermal oxidation method, Low Pressure Chemical Vapor Deposition or plasma auxiliary chemical vapor deposition method.The thickness of the first insulating barrier 130a for example is 50 dust to 300 dusts.The material of the second insulating barrier 130b for example is spin-on glasses or spin-coating dielectric material.The formation method of the second insulating barrier 130b for example is a method of spin coating.The thickness of the second insulating barrier 130b for example is 3000 dust to 6000 dusts.In another embodiment, before forming the first insulating barrier 130a, can on first conductor layer, 120 sidewalls, tunneling dielectric layer 110 sidewalls, irrigation canals and ditches 160 inwalls, form lining 130c earlier, with repair etching when forming irrigation canals and ditches 160 for damage that trench sidewall was caused.The material of lining 130c for example is a silica, and the method for formation for example is a thermal oxidation method, and thickness for example is 20 dust to 80 dusts.
Afterwards, see also shown in Fig. 2 C and Fig. 3 C, carry out first and remove step, the second insulating barrier 130b, the first insulating barrier 130a and second cover curtain layer 126 are removed, to the end face that exposes first cover curtain layer 124.The method that removes for example be with first cover curtain layer 124 for stopping layer, remove through chemical mechanical milling method or etch-back method.
Then; See also shown in Fig. 2 D to Fig. 2 F and Fig. 3 D to Fig. 3 F; Carry out second and remove step; Remove the part first insulating barrier 130a, the part second insulating barrier 130b and the first cover curtain material layer 124, make the first insulating barrier 130a that stays extend the partial sidewall that covers first conductor layer 120 from irrigation canals and ditches 160 sidewalls, the height of the top 130a ' of the first insulating barrier 130a then is higher than surface 110 ' about 150-300 dust of tunneling dielectric layer 110.The surperficial 130b ' of the second insulating barrier 130b highly for example is suitable with the surface 110 ' of tunneling dielectric layer 110.
Specifically, see also shown in Fig. 2 D and Fig. 3 D, second remove step phase I be earlier to remove part first insulating barrier 130a and the part second insulating barrier 130b with anisotropic etch process, make the sidewall of the first cover curtain material layer 124 expose out.Anisotropic etch process comprises dry ecthing method, for example is the reactive ion etch method.In one embodiment, carry out second and remove after the phase I of step, roughly the height with first conductive layer 120 is suitable for first left insulating barrier 130a and the height of the second insulating barrier 130b.
Then, see also shown in Fig. 2 E and Fig. 3 E, carry out second remove step second stage, first a cover curtain material layer 124 is removed.Removing the method that the first cover curtain material layer 124 removes for example is wet etch method.In one embodiment, the material of the first cover curtain material layer 124 is a silicon nitride, and removing the first cover curtain material layer, 124 operable etching solutions for example is hot phosphoric acid solution.
Then, see also shown in Fig. 2 F and Fig. 3 F, carry out second remove step phase III, serve as the cover curtain with first conductor layer 120, utilize wet etching to remove part first insulating barrier 130a and the part second insulating barrier 130b.The employed etching solution of wet etching is higher than the rate of etch of the first insulating barrier 130a for the rate of etch of the second insulating barrier 130b, so that the height of the second insulating barrier 130b is lower than the height of the first insulating barrier 130a.Employed etching solution for example is a hydrofluoric acid.Make the first insulating barrier 130a that stays extend the partial sidewall that covers first conductor layer 120, and the height of the first insulating barrier 130a top 130a ' is higher than the height of the surperficial 130b ' of the second insulating barrier 130b from irrigation canals and ditches 160 sidewalls.In one embodiment, the height of second insulating barrier 130b surface 130b ' for example is suitable with the surface 110 ' of tunneling dielectric layer 110, and both highly differ in 100 dusts.The height of the first insulating barrier 130a is higher than tunneling dielectric layer 110 surfaces.In one embodiment, the height of the first insulating barrier 130a is higher than about 150 to 300 dusts in tunneling dielectric layer 110 surfaces.The end face of the first insulating barrier 130a can be the inclined plane.In one embodiment, the height of the top 130a ' of the first insulating barrier 130a then is higher than surface 110 ' about 150-300 dust of tunneling dielectric layer 110.Left lining 130c, the first insulating barrier 130a and the second insulating barrier 130b are isolation structure 130.
See also shown in Fig. 2 G and Fig. 3 G, forming dielectric layer 140 between grid in the substrate 100.Dielectric layer 140 can be to be made up of single material layer between grid.Single material layer for example is advanced low-k materials or high dielectric constant material.Advanced low-k materials is meant that dielectric constant is lower than 4 dielectric material, for example is silica or silicon oxynitride.High dielectric constant material is meant that dielectric constant is higher than 4 dielectric material, for example is HfAlO, HfO
2, Al
2O
3Or Si
3N
4 Dielectric layer 140 also can be selected to improve injection current according to the energy gap engineering theory between grid, makes sequencing double stacked structure or multiple-level stack structure faster.The double stacked structure example is the double stacked structure (representing with advanced low-k materials/high dielectric constant material) formed of advanced low-k materials and high dielectric constant material in this way, for example is silica/HfSiO, silica/HfO
2Or silica/silicon nitride.The multiple-level stack structure example is the multiple-level stack structure (representing with advanced low-k materials/high dielectric constant material/advanced low-k materials) formed of advanced low-k materials, high dielectric constant material and advanced low-k materials in this way, for example is silicon oxide/silicon nitride/silicon oxide or silica/Al
2O
3/ silica.The formation method of dielectric layer 140 for example is a chemical vapour deposition technique between grid.
Then, on dielectric layer between grid 140, form second conductor layer 150.The material of second conductor layer 150 for example is DOPOS doped polycrystalline silicon, multi-crystal silicification metal or its stack layer that combines, and its formation method can be selected physical vaporous deposition or chemical vapour deposition technique for use according to its material.
See also shown in Fig. 2 H and Fig. 3 H dielectric layer 140, first conductor layer 120 and tunneling dielectric layer 110 between patterning second conductor layer 150, grid.The method of patterning for example is little shadow and etching method.Second conductor layer 150 of patterning is as a plurality of control grid 150a; First conductor layer 120 of patterning is as a plurality of floating grid 120a.Then, in the substrate 100 of control grid 150 2 sides, forming first doped region 170 and second doped region 180, respectively as source area and drain region, is channel region between source area and the drain region.The doping of first doped region 170 and second doped region 180 can be P type or N type.The doping of P type can be an IIIA family ion, for example is the boron ion.It can be that VA family ion for example is arsenic or phosphorus that the N type mixes.
See also shown in Figure 1ly, the non-volatile memory cell of the embodiment of the invention comprises dielectric layer 140 between substrate 100, tunneling dielectric layer 110, floating grid 120, isolation structure 130, grid, control grid 150 and first doped region 170 and second doped region 180.Isolation structure 130 is positioned at the irrigation canals and ditches 160 of substrate 100, and substrate 100 is defined a plurality of active regions 200.Isolation structure 130 comprises the first insulating barrier 130a and the second insulating barrier 130b.The first insulating barrier 130a and extends the partial sidewall cover floating grid 120 from irrigation canals and ditches 160 sidewalls between the substrate 100 and the second insulating barrier 130b, and the height of the first insulating barrier 130a is higher than the height of the second insulating barrier 130b.Tunneling dielectric layer 110 is positioned on the active region 200 of substrate 100 with floating grid 120.Dielectric layer 140 is between floating grid 120 and the control grid 150 and between isolation structure 130 and the control grid 150 between grid.
The non-volatile memory cell of the embodiment of the invention; The height of the second insulating barrier 130b in the isolation structure 130 is reduced near the height of tunneling dielectric layer 110, can avoids accompanying between two floating grids 120 bulky insulating barrier and cause therebetween that coupling capacitance becomes big interference problem of deriving.In addition, the height of the first insulating barrier 130a is higher than the height of the second insulating barrier 130b, extends the partial sidewall that covers floating grid 120 from irrigation canals and ditches 160 sidewalls, therefore, can avoid the problem of electronics from puncturing between substrate 100 to the control grid 150.
In sum, the isolation structure of the non-volatile memory cell of the embodiment of the invention can avoid electronics to puncture between grid dielectric layer to controlling the leakage problem that grid is derived from substrate, and can avoid two interference problems between the floating grid.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction; Though the present invention discloses as above with preferred embodiment; Yet be not in order to limiting the present invention, anyly be familiar with the professional and technical personnel, in not breaking away from technical scheme scope of the present invention; When the method for above-mentioned announcement capable of using and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations; In every case be the content that does not break away from technical scheme of the present invention, to any simple modification, equivalent variations and modification that above embodiment did, all still belong in the scope of technical scheme of the present invention according to technical spirit of the present invention.
Claims (11)
1. non-volatile memory cell is characterized in that it comprises:
One substrate, this substrate has a plurality of irrigation canals and ditches;
One tunneling dielectric layer is disposed in this substrate;
One floating grid is disposed on this tunneling dielectric layer;
One isolation structure is positioned at this irrigation canals and ditches, and this isolation structure comprises one first insulating barrier and one second insulating barrier, wherein
This first insulating barrier between this second insulating barrier and this substrate, and extend the partial sidewall that covers this floating grid from this trench sidewall, and the height of this first insulating barrier is higher than the height of this second insulating barrier;
One control grid is disposed on this floating grid and this isolation structure; And
Dielectric layer between one grid is disposed between this floating grid and this control grid and between this isolation structure and this control grid.
2. non-volatile memory cell according to claim 1, the thickness that it is characterized in that wherein said first insulating barrier are 50 dust to 300 dusts.
3. non-volatile memory cell according to claim 1 is characterized in that the height of wherein said first insulating barrier is higher than surface 150 to 300 dusts of this tunneling dielectric layer.
4. non-volatile memory cell according to claim 1, the end face that it is characterized in that wherein said first insulating barrier is the inclined plane.
5. non-volatile memory cell according to claim 1, it is characterized in that wherein said second insulating barrier height and this tunneling dielectric layer the surface quite, and the surface of the surface of this second insulating barrier and this tunneling dielectric layer differs less than 100 dusts.
6. non-volatile memory cell according to claim 1 is characterized in that also comprising a lining, between this first insulating barrier and this substrate.
7. the manufacturing approach of a non-volatile memory cell is characterized in that it may further comprise the steps:
In this substrate, form a tunneling dielectric layer, one first conductor layer and a cover curtain layer in regular turn;
This cover curtain layer of patterning, this first conductor layer and this tunneling dielectric layer, and in this substrate, form a plurality of irrigation canals and ditches;
In this substrate, form one first insulating barrier, this first insulating barrier covers this cover curtain layer, this cover curtain layer sidewall, this first conductor layer sidewall, this tunneling dielectric layer sidewall and those irrigation canals and ditches inwalls;
In this substrate and this first coated insulating layer cover one second insulating barrier;
Carry out first and remove step, remove this cover curtain layer above this second insulating barrier and this first insulating barrier;
Carry out one second and remove step; Remove this first insulating barrier of part, this second insulating barrier of part and this cover curtain layer; Make this first insulating barrier that stays extend the partial sidewall that covers this floating grid from this trench sidewall; And the height of this first insulating barrier is higher than this second insulating barrier, and this that stays first insulating barrier and this second insulating barrier constitute an isolation structure;
Forming dielectric layer between grid in this substrate, cover this isolation structure and this first conductor layer;
On dielectric layer between these grid, form one second conductor layer;
Dielectric layer, this first conductor layer and this tunneling dielectric layer between this second conductor layer of patterning, these grid make this second conductor layer form a plurality of control grids, and this first conductor layer forms a plurality of floating grids.
8. the manufacturing approach of non-volatile memory cell according to claim 7 is characterized in that wherein said second removes step and comprise in regular turn:
With this cover curtain layer is the cover curtain, removes this first insulating barrier of part and this second insulating barrier of part, makes the sidewall of this cover curtain layer expose out;
Remove this cover curtain layer; And
With this first conductor layer is the cover curtain, removes this first insulating barrier of part and this second insulating barrier of part with an etching solution, and this etching solution is higher than the rate of etch for this first insulating barrier for the rate of etch of this second insulating barrier.
9. the manufacturing approach of non-volatile memory cell according to claim 8 is characterized in that serving as the cover curtain with this cover curtain layer wherein, and the method that removes this first insulating barrier of part and this second insulating barrier of part comprises anisotropic etch process.
10. the manufacturing approach of non-volatile memory cell according to claim 7; It is characterized in that wherein said second remove step that make this part second insulating barrier with surface this tunneling dielectric layer quite, and the surface of the surface of this second insulating barrier and this tunneling dielectric layer highly differs less than 100 dusts.
11. the manufacturing approach of non-volatile memory cell according to claim 7, it is characterized in that also being included in form this first insulating barrier before, formation one lining between this first insulating barrier and this substrate.
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| CN112259545A (en) * | 2020-10-20 | 2021-01-22 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
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