CN102647374B - Cross-clock domain interference cancellation device and cross-clock domain interference cancellation method - Google Patents
Cross-clock domain interference cancellation device and cross-clock domain interference cancellation method Download PDFInfo
- Publication number
- CN102647374B CN102647374B CN201110041056.8A CN201110041056A CN102647374B CN 102647374 B CN102647374 B CN 102647374B CN 201110041056 A CN201110041056 A CN 201110041056A CN 102647374 B CN102647374 B CN 102647374B
- Authority
- CN
- China
- Prior art keywords
- signal
- interference
- clock
- digital transmission
- injection time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Noise Elimination (AREA)
Abstract
A cross-clock domain interference cancellation device and a cross-clock domain interference cancellation method are applicable to a communication system which comprises a transmitter operating in a first clock domain and a receiver operating in a second clock domain. The interference cancellation device comprises a first-in-first-out (FIFO) circuit and a cancellation signal generation circuit. The FIFO circuit can receive the digital transmitted signal of the transmitter in the first clock domain, and can output the digital transmitted signal in the second clock domain according to the accumulated time sequence difference between the first clock domain and the second clock domain. The cancellation signal generation circuit can generate a cancellation signal for cancelling an interference signal received by the receiver according to the digital transmitted signal outputted by the FIFO circuit, and the interference signal is generated due to responding to the digital transmitted signal. According to the phase difference between the interference signal and the cancellation signal, the cancellation signal generation circuit regulates the cancellation signal.
Description
Technical field
Present invention is directed to interference to eliminate, espespecially a kind of interference blanking unit of cross clock domain and method.
Background technology
In conventional communication system, when (interference cancellation) is eliminated in the interference performing cross clock domain (cross clock domain), normal employing expense Lip river structure (Farrow structure) performs interpolative operation, to carry out the clock zone conversion of related data.Expense Lip river structure utilizes the approximation method of multinomial (polynomial), simplifies the complexity of interpolative operation.But use polynomial approximation method to produce error, it is 180 degree of parts that the maximum place of usual error occurs in phase place, and, when both constrained input data clock more close to time, error is larger, and the usefulness of taking Lip river structure is also poorer.Particularly, when the clock of both constrained input data is almost equal, expense Lip river structure almost cannot go out the data value that phase place is 180 degree by accurate interpolation.
For example, in the application of HDMI (High Definition Multimedia Interface) Ethernet passage (HDMI Ethernet channel), owing to adopting single line transmitted in both directions, therefore can receive square signal and the echo (echo) of returning that rebounds is disturbed because one's own side institute transmits simultaneously.So, need to use echo canceller (echo canceller) to perform echo cancellation.A little error (0 ~ 200ppm) is had due between the clock that the network equipment at HDMI Ethernet passage two ends uses, therefore, after needing first the data of one's own side's conveyer (Tx) to be converted to from the clock zone of Tx the clock zone of one's own side's receiver (Rx), echo canceller carries out echo cancellation in the clock zone of Rx again.Now, carry out clock zone conversion according to expense Lip river structure, then the gap clock due to Tx and Rx is minimum, and the interpolation usefulness of taking Lip river structure can be very poor, and must use the multinomial of very high-order to be similar to, and just has good usefulness.But multinomial exponent number is higher, the tapping point (tap) taken needed for the structure of Lip river is more, and therefore complexity is higher, and signal delay (delay) is also longer.
Another shortcoming of usage charges Lip river structure is, the complexity of computing performed by echo canceller also can increase.In HDMI Ethernet passage, the data that original Tx launches are MLT-3 signal, only have 0 ,+1 ,-1 three level, do clock zone conversion if do not need, then echo canceller does not need to perform multiplication, only needs addition just can complete.But be through after expense Lip river structure interpolation goes out the data value of out of phase and time point, more figure place just must be used could to represent the data of Tx, and echo canceller just must use multiplication just can complete thus, causes computational complexity to increase.
Summary of the invention
In view of this, an object of the present invention, is to provide a kind of interference blanking unit and method, eliminates problem, and reduce the complexity of system architecture and computing with the interference processing cross clock domain.
In one embodiment of this invention, disclose a kind of interference blanking unit, be applicable in a communication system, this communication system comprises the receiver that a conveyer and operating on one first clock zone operates on a second clock territory.This interference blanking unit comprises: a first in first out (FIFO) circuit, in order to receive a digital transmission signal of this conveyer at this first clock zone, and according to the accumulative difference of injection time of between this first clock zone and this second clock territory, export this digital transmission signal in this second clock territory; And one erasure signal produce circuit, in order to this digital transmission signal exported according to this fifo circuit, produce an erasure signal, in order to eliminate the interference signal that this receiver receives, this interference signal responds this digital transmission signal and produces, wherein this erasure signal produces circuit according to the phase difference between this interference signal and this erasure signal, to adjust this erasure signal.
In another embodiment of the invention, disclose a kind of interference elimination method, be applicable in a communication system, this communication system comprises the receiver that a conveyer and operating on one first clock zone operates on a second clock territory.This interference elimination method comprises the following step: the digital transmission signal receiving this conveyer at this first clock zone; According to the accumulative difference of injection time of between this first clock zone and this second clock territory, export this digital transmission signal in this second clock territory; And according to this digital transmission signal exported in this second clock territory, produce an erasure signal, in order to eliminate the interference signal that this receiver receives, this interference signal responds this digital transmission signal and produces, and wherein this erasure signal system adjusts according to the phase difference between this interference signal and this erasure signal.
Accompanying drawing explanation
Fig. 1 is the calcspar of an embodiment of interference blanking unit of the present invention.
Fig. 2 is the calcspar of a preferred embodiment of interference blanking unit of the present invention.
3A to 3D figure is with an example, and the echo canceller of display Fig. 2, how in response to the change of the way of output of asynchronous first in first out unit, carries out the adjustment of the relativeness of tap coefficient and sampling value.
4A and 4B figure is with another example, and the echo canceller of display Fig. 2, how in response to the change of the way of output of asynchronous first in first out unit, carries out the adjustment of the relativeness of tap coefficient and sampling value.
Fig. 5 is the flow chart of an embodiment of interference elimination method of the present invention.
Graphic figure number illustrates:
10,20: interference blanking unit 11,21: fifo circuit
12: erasure signal produces circuit 13,23,33: adder
24: sequential accumulator 211: synchronous first in first out unit
212: asynchronous first in first out unit 31: front end receive circuit
311: analog-to-digital converter 32: cutter
34: time sequence recovery circuit 35: clock circuit
36: transfer circuit 37: DAC
38: hybrid circuit
Embodiment
Fig. 1 is the calcspar of an embodiment of interference blanking unit 10 of the present invention, and it is applicable to a communication system, with the interference produced in erasure signal transmitting procedure.This communication system comprises the receiver that a conveyer and operating on the first clock zone operates on second clock territory.Under different system configuration, the transmission signal of this conveyer can cause disturbance during this receiver Received signal strength in transmitting procedure, such as, if this conveyer and receiver are positioned at same one end of a passage (channel), then when conveyer transmits a signal via this passage, receiver can receive the echo of this signal bounce-back from this passage; If this conveyer and receiver belong to different passage, receiver also can receive the transmission signal of response conveyer and the cross-talk (cross-talk) that produces.Interference blanking unit 10 can produce erasure signal according to the transmission signal of conveyer, to offset the interference produced because of this transmission signal from the Received signal strength of receiver.But, because this transmission signal and Received signal strength adhere to the first clock zone and second clock territory separately, the interference that interference blanking unit 10 need perform cross clock domain is eliminated.
As shown in Figure 1, interference blanking unit 10 comprises first in first out (First-In, a First-Out; FIFO) circuit 11, erasure signal produces circuit 12 and an adder 13.Fifo circuit 11 can receive a digital transmission signal of this conveyer at the first clock zone, and according to the accumulative difference of injection time (accumulated timing error) of between the first clock zone and second clock territory, export this digital transmission signal in second clock territory.Fifo circuit 11 is mainly used for the order of control signal I/O and speed, and does not process the size of signal value.Particularly, fifo circuit 11 can according to the accumulative difference of injection time between its input clock territory (i.e. the first clock zone) and output clock territory (i.e. second clock territory), the mode that adjustment exports, to carry out the conversion of clock zone, hereafter can describe in detail this again.
Erasure signal produces the digital transmission signal that circuit 12 can export according to fifo circuit 11, and produce an erasure signal, in order to eliminate the interference signal that this receiver receives, and this interference signal responds this digital transmission signal and produces.Particularly, erasure signal produces circuit 11 and according to the phase difference between this interference signal and this erasure signal, can adjust this erasure signal, to reduce or to remove this phase difference.Because receiver can receive the data that this interference signal and communication counterpart transmit simultaneously, that is, a digital received signals of receiver is contained in this interference signal system, therefore interference blanking unit 10 arranges adder 13, be coupled to the Signal reception path that erasure signal produces circuit 12 and receiver, export after this digital received signals can being deducted this erasure signal, eliminate to perform interference.
In the embodiment in figure 1, the interference of cross clock domain elimination is divided into two parts to process.If aforementioned digital transmission signal is multiple continuous print sampling points at the first clock zone, then on a timeline, each sampling point can be considered an integral point, and the spacing of adjacent 2 is a clock cycle of the first clock zone.In aforementioned prior art, the practice of expense Lip river structure is according to these integral points, and interpolation goes out the value of the sampling point in second clock territory, so in second clock territory, each sampling point of digital transmission signal will depart from the position of integral point originally on a timeline.But, in interference blanking unit 10 of the present invention, do not carry out complicated interpolative operation, but by non-integer point position on a timeline, second clock territory, be divided into integer and decimal two parts, such as, if a sampling point is positioned at the position of x.y (x and y represents integer and fractional part respectively), then be divided into x and 0.y two parts, process respectively.First, utilize fifo circuit 11 will to be positioned at the integral point of x in script the first clock zone, the time point in x.y exports (that is the speed according to second clock territory exports), to process the part of integer.Because the speed of first and second clock zone is different, fifo circuit 11 need with reference to the accumulative difference of injection time between first and second clock zone, once export comparatively multi-sample point (when the first clock zone is faster than second clock territory) or at least skip and once do not export any sampling point (when being slower than second clock territory when the first clock zone) opportune moment, produce to avoid fifo circuit 11 and overflow (overflow) or overflow into (underflow).Then, because fractional part not yet processes, so erasure signal produces the erasure signal that circuit 12 produces according to the output of fifo circuit 11, a phase difference is had between meeting and interference signal, now, erasure signal produces circuit 12 and according to this phase difference, can perform the interference signal that adaptability (adaptive) algorithm following the trail of speed follows the trail of out of phase, to adjust erasure signal, reach the effect comparatively fast reducing or remove this phase difference.Mode by this, just can eliminate untreated the caused error of fractional part, eliminates with the interference completing cross clock domain.
In one embodiment, erasure signal produces circuit 12 is utilize least fibre method (least mean square; Or recursive least-squares method (recursive least squares LMS); RLS), the interference signal of out of phase is followed the trail of.In order to promote speed and the usefulness of tracking, the step-length (step size) that LMS or RLS algorithm uses need coordinate the phase difference between erasure signal and interference signal and adjust.
In one embodiment, aforesaid interference signal is an echo signal, and it is an echo canceller (echo canceller) that erasure signal produces circuit 12.Such as, this embodiment can be applicable to the situation that conveyer and receiver carry out in same one end of HDMI Ethernet passage (HDMI Ethernet channel) transmitting Yu receiving respectively.In another embodiment, this interference signal is a crosstalk signal, and it is a crosstalk canceller that erasure signal produces circuit 12.Such as, this embodiment can be applicable to the situation that conveyer and receiver are connected to the different port of network switch.Some network switch can use multiport transformer (multi-port transformer), to save cost and circuit area, but due to the coil between two ports too near, near-end crosstalk (the near-end cross-talk across port can be caused; NEXT) disturb, and the clock of different port is likely very close but not identical, therefore can use interference blanking unit of the present invention, removes this kind of tradition and is considered as indelible interference.
Fig. 2 is the calcspar of a preferred embodiment of interference blanking unit 20 of the present invention, and it is be arranged at a conveyer and operating on the first clock zone to operate between the receiver in second clock territory.This conveyer and receiver are positioned at same one end of a passage, and are all coupled to this passage via mixing (hybrid) circuit 38.This conveyer has oneself clock frequency (i.e. the first clock zone), this receiver then adopts the synchronization mode of loop sequential (loop timing), to pin the clock frequency (i.e. second clock territory) of the other side's conveyer, therefore one's own side's conveyer and receiver can be caused to be in different clock zones, and to need interference blanking unit 20 to perform the echo cancellation of cross clock domain.Interference blanking unit 20 comprises fifo circuit 21, echo canceller 22, adder 23 and a sequential accumulator 24.Fifo circuit 21 comprises synchronous first in first out (Sync FIFO) unit 211 and an asynchronous first in first out (Async FIFO) unit 212.In Fig. 2, the transfer circuit 36 of conveyer exports a digital transmission signal, converts analog signal to via DAC 37, delivers to hybrid circuit 38, to carry out channel transfer.Synchronization fifo unit 211 receives this digital transmission signal at the first clock zone, and it comprises multiple sampling point, and synchronization fifo unit 211 can keep in wherein a part of sampling point, for the output of asynchronous FIFO unit 212 elasticity.Asynchronous FIFO unit 212 can according to the accumulative difference of injection time of between the first clock zone and second clock territory, each clock in second clock territory performs one of following way of output: export one of these sampling points (general situation), export continuous 2 points of these sampling points and (be hereafter also called benefit point, mean than general situation multi output a bit) and do not export any sampling point (hereafter be also called to fall a little, mean export a bit fewer than general situation).When accumulative difference of injection time when between first and second clock zone does not reach a clock cycle (that is between two clock zones gap less than a sampling range), asynchronous FIFO unit 212 only normally need export a sampling point from synchronization fifo unit 211, does not need carry out benefit point or fall a little.But, when the first clock zone faster than second clock territory and this accumulative difference of injection time reaches a clock cycle time, represent second clock territory and fall behind a sampling point, now asynchronous FIFO unit 212 must once export continuous two sampling points from synchronization fifo unit 211, just can catch up with the first clock zone; And when the first clock zone is slower than second clock territory and this accumulative difference of injection time reaches a clock cycle, represent the super previous sampling point in second clock territory, now asynchronous FIFO unit 212 suspends any sampling point of output, makes the first clock zone can catch up with.
As shown in Figure 2, the mechanism of the difference of injection time can detected between two clock zones is comprised: it is the transmission clock being faster or slower than the other side that time sequence recovery circuit 34 can detect current receive clock in receiver, if hurry up, then notify that clock circuit 35 tunes up the receive clock delivering to analog-to-digital converter (ADC) 311; If slow, then notify that clock circuit 35 slows down, by this mode come pin the transmission clock of the other side.Therefore, the sequential accumulator 24 in interference blanking unit 20 can according to each detecting result of time sequence recovery circuit 34, the accumulative number of times tuned up or slow down.When cumulative number reach be equivalent to tune up a clock cycle or sampling range time, namely sequential accumulator 24 notifies that asynchronous FIFO unit 212 carries out action a little; And when cumulative number reach be equivalent to slow down a clock cycle time, sequential accumulator 24 namely notify asynchronous FIFO unit 212 carry out mend point action.In one embodiment, clock circuit 35 is a phase-locked loop (PLL), and sequential accumulator 24 is phase accumulators, and the accumulative difference of injection time between aforesaid two clock zones is that an accumulated phase is poor.Such as, if this phase-locked loop has 64 phase places, then when this phase accumulator accumulation toward front jumping 64 phase places (namely having added up 64 times to tune up) or backward jump 64 phase place (namely having added up 64 times to slow down) time, just must notify asynchronous FIFO unit 212 do corresponding fall a little or benefit action.In another embodiment, clock circuit 35 is a voltage controlled oscillator (VCO), and sequential accumulator 24 is clock accumulators, and this accumulative difference of injection time is that a cumulative frequency is poor.The adjustment of frequency can be scaled corresponding phase place adjustment, therefore can calculate and namely be equivalent to tune up or slow down a clock cycle when this frequency accumulator adds up how many number of times.
The erasure signal that echo canceller 22 is similar to Fig. 1 produces circuit 12, and the sampling point of the digital transmission signal that can export according to asynchronous FIFO unit 212, produces an erasure signal, the echo signal received in order to cancellation receiver.Further, echo canceller 22 also according to the phase difference between this erasure signal and echo signal, can adjust this erasure signal, to reduce or to remove this phase difference.Adder 23 receives a digital received signals (including this echo signal) and this erasure signal respectively from front end receive circuit 31 and echo canceller 22 respectively, to deduct this erasure signal from this digital received signals, carries out echo cancellation.In addition, receiver also comprises cutter 32 and an adder 33, and cutter 33 can carry out a cutting action to the output signal of adder 23, to convert a series of reference position value to; Adder 33 can calculate the difference of signal value before these reference position values and cutting, send into echo canceller 22, to estimate the phase difference between echo signal and interference signal, produces erasure signal for echo canceller 22.
When sequential accumulator 24 notifies that asynchronous FIFO unit 212 need carry out benefit point or to fall, also can notify that echo canceller 22 adjusts accordingly to its inside, to maintain the continuity of produced erasure signal simultaneously.In one embodiment, echo canceller 22 is for having the filter of multiple tapping point (tap), and the relativeness between each sampling point of the coefficient of each tapping point and digital transmission signal, need adjust according to the way of output of this asynchronous FIFO unit 212, make this relativeness can keep coherent along with the time.Be that the example of finite impulse response (FIR) (FIR) filter of four tapping points is described as follows with echo canceller 22: suppose that the sampling value of each tapping point is respectively D (n), D (n-1), D (n-2), D (n-3), and the tap coefficient of correspondence is sequentially a0, a1, a2, a3, as shown in Figure 3A.The action of mending point if do not carry out or falling a little, then at next clock, can as situation increase newly a sampling value D (n+1), other sampling value then sequentially forward impelling one tapping point (D (n-3) is then rejected), each tap coefficient is still sequentially a0, a1, a2, a3, the relativeness between tap coefficient and sampling value is made to keep coherent, as shown in Figure 3 B.But, if be not general situation when this next clock, but carry out benefit point, then the sampling value of each tapping point becomes D (n+2), D (n+1), D (n), D (n-1) (namely once increasing two sampling value D (n+1) and D (n+2) newly), and be maintain linking up of aforementioned relativeness, tap coefficient must move a tapping point forward, be adjusted to 0, a0, a1, a2 be (because D (n+2) is additional in addition, corresponding tap coefficient produces not yet, therefore be reset to 0), as shown in Figure 3 C; Otherwise, if carry out a little, the sampling value of each tapping point still maintains D (n), D (n-1), D (n-2), D (n-3) (i.e. not newly-increased sampling value), tap coefficient then moves a tapping point afterwards, be adjusted to a1, a2, a3,0 (because D (n-3) should give up originally, therefore corresponding tap coefficient is reset to 0), as shown in Figure 3 D.
The another kind of practice is, the position of tap coefficient remains motionless, the only position of mobile sampling value, and the same can reaching maintains the coherent effect of relativeness.Such as, if mend the situation of point, then by the mobile tapping point forward of each sampling value in Fig. 3 A, the position that D (n) is available is filled by increasing sampling value D (n+1) newly, another newly-increased sampling value D (n+2) then directly replaces the position of D (n-2), and corresponding tap coefficient was reset to for 0 (as shown in Figure 4 A), the effect as Fig. 3 C can be reached.If fall situation a little, then by each sampling value loopy moving in Fig. 3 A, that is each sampling value mobile tapping point forward, the sampling value D (n-3) of foremost then retracts the position of D (n) originally, and the tap coefficient that D (n-3) is corresponding was reset to for 0 (as shown in Figure 4 B), the effect as Fig. 3 D can be reached.
Fig. 5 is the flow chart of an embodiment of interference elimination method of the present invention, and it is applicable in a communication system, and this communication system comprises the receiver that a conveyer and operating on the first clock zone operates on second clock territory.Step S51 is the digital transmission signal receiving this conveyer in the first clock zone.Step S52 is according to the accumulative difference of injection time of between the first clock zone and second clock territory, exports this digital transmission signal in second clock territory.This accumulative difference of injection time can be one accumulated phase difference or a cumulative frequency poor.Step S53 is according to the digital transmission signal exported in second clock territory, and produce an erasure signal, in order to eliminate the interference signal that this receiver receives, this interference signal responds this digital transmission signal and produces.In step S53, also according to the phase difference between this interference signal and erasure signal, adjust this erasure signal.Finally, in step S54, due to this interference signal be in be contained in a digital received signals of receiver, so export after this digital received signals is deducted this erasure signal, eliminate to perform interference.
In one embodiment, this interference signal is an echo signal.Such as, this embodiment can be applicable to the situation that conveyer and receiver carry out in same one end of HDMI Ethernet passage transmitting Yu receiving respectively.In another embodiment, this interference signal is a crosstalk signal.Such as, this embodiment can be applicable to the situation that conveyer and receiver system are connected to the different port of network switch.
Preferably, this digital transmission signal comprises multiple sampling point, step S52 is according to the accumulative difference of injection time between first and second clock zone, and each clock in second clock territory performs one of following way of output: export one of these sampling points, export continuous 2 points of these sampling points and do not export any sampling point.The Time window of the aforementioned various way of output is below described:
(1) when the first clock zone faster than second clock territory and this accumulative difference of injection time reaches a clock cycle time, step S52 exports continuous 2 points of these sampling points.
(2) when the first clock zone is slower than second clock territory and this accumulative difference of injection time reaches a clock cycle, step S52 does not export any sampling point.
(3) when this accumulative difference of injection time does not reach a clock cycle, step S52 exports one of these sampling points.
Comprehensively above-mentioned, interference blanking unit of the present invention and method, the interference of cross clock domain can be eliminated problem to be divided into two parts to process, Part I can be considered integer part, namely sampling point is when carrying out clock zone conversion, need postpone in sequential or shift to an earlier date, this part can be reached by asynchronous first-in first-out; Part II is fractional part, and namely when producing the erasure signal being used for eliminating interference, this interference signal of palpus energy fast track is in the response of out of phase, and this part can realize by adopting the adaptive algorithm strengthening step-length.By with upper type, just can reduce the complexity of system architecture and circuit, the interference performing cross clock domain is eliminated.
The above utilizes preferred embodiment to describe the present invention in detail, but not limits the scope of the invention.Generally those skilled in the art all can understand, the suitably change done slightly and adjustment, will not lose main idea place of the present invention, also not depart from the spirit and scope of the present invention.
Claims (22)
1. an interference blanking unit, is applicable in a communication system, and described communication system comprises the receiver that a conveyer and operating on one first clock zone operates on a second clock territory, and described interference blanking unit comprises:
One fifo circuit, in order to receive a digital transmission signal of described conveyer at described first clock zone, and according to the accumulative difference of injection time of between described first clock zone and described second clock territory, exports described digital transmission signal in described second clock territory; And
One erasure signal produces circuit, couples described fifo circuit, produces an erasure signal according to described digital transmission signal, in order to eliminate the interference signal that described receiver receives;
Wherein, described interference signal is the described digital transmission signal of response and produces, and described erasure signal produces circuit according to the phase difference between described interference signal and described erasure signal to adjust described erasure signal,
Wherein, described digital transmission signal comprises multiple sampling point, and described fifo circuit comprises:
One synchronous first in first out unit, in order to receive these sampling points described at described first clock zone, and a temporary part these sampling points described; And
One asynchronous first in first out unit, be coupled to described synchronous first in first out unit, in order to according to described accumulative difference of injection time, each clock in described second clock territory performs one of following way of output: export one of these sampling points described, export continuous 2 points of these sampling points described and do not export any sampling point.
2. interference blanking unit according to claim 1, wherein, be contained in a digital received signals of described receiver in described interference signal, described interference blanking unit comprises further:
One adder, exports after described digital received signals is deducted described erasure signal.
3. interference blanking unit according to claim 1, wherein, described interference signal is an echo signal, and it is an echo canceller that described erasure signal produces circuit.
4. interference blanking unit according to claim 3, wherein, described conveyer and described receiver carry out respectively transmitting in same one end of a HDMI (High Definition Multimedia Interface) Ethernet passage and receive.
5. interference blanking unit according to claim 1, wherein, described interference signal is a crosstalk signal, and it is a crosstalk canceller that described erasure signal produces circuit.
6. interference blanking unit according to claim 5, wherein, described conveyer and described receiver are connected to the different port of a network switch.
7. interference blanking unit according to claim 1, wherein, described accumulative difference of injection time is that an accumulated phase is poor, and described interference blanking unit comprises further:
One phase accumulator, poor in order to the described accumulated phase produced between described first clock zone and described second clock territory.
8. interference blanking unit according to claim 1, wherein, described accumulative difference of injection time is that a cumulative frequency is poor, and described interference blanking unit comprises further:
One clock accumulator, poor in order to the described cumulative frequency produced between described first clock zone and described second clock territory.
9. interference blanking unit according to claim 1, wherein, when described first clock zone faster than described second clock territory and described accumulative difference of injection time reaches a clock cycle time, described asynchronous first in first out unit exports continuous 2 points of these sampling points described.
10. interference blanking unit according to claim 1, wherein, when described first clock zone is slower than described second clock territory and described accumulative difference of injection time reaches a clock cycle, described asynchronous first in first out unit does not export any sampling point.
11. interference blanking units according to claim 1, wherein, when described accumulative difference of injection time does not reach a clock cycle, described asynchronous first in first out unit exports one of these sampling points described.
12. interference blanking units according to claim 1, wherein, described erasure signal produces circuit and comprises multiple tapping point, each tapping point has the tap coefficient of a correspondence, the relativeness of these tap coefficient wherein said and these sampling points described, adjusts according to the way of output of described asynchronous first in first out unit.
13. 1 kinds of interference elimination methods, are applicable in a communication system, and described communication system comprises the receiver that a conveyer and operating on one first clock zone operates on a second clock territory, and described interference elimination method comprises the following step:
A digital transmission signal of described conveyer is received at described first clock zone;
According to the accumulative difference of injection time of between described first clock zone and described second clock territory, export described digital transmission signal in described second clock territory; And
According to the described digital transmission signal exported in described second clock territory, produce an erasure signal, in order to eliminate the interference signal that described receiver receives, described interference signal responds described digital transmission signal and produces, wherein said erasure signal adjusts according to the phase difference between described interference signal and described erasure signal
Wherein, described digital transmission signal comprises multiple sampling point, the step of described output digital transmission signal is according to described accumulative difference of injection time, and each clock in described second clock territory performs one of following way of output: export one of these sampling points described, export at continuous 2 and do not export any sampling point of these sampling points described.
14. interference elimination methods according to claim 13, wherein, described interference signal is contained in a digital received signals of described receiver in being, described interference elimination method comprises further:
Export after described digital received signals is deducted described erasure signal.
15. interference elimination methods according to claim 13, wherein, described interference signal is an echo signal.
16. interference elimination methods according to claim 15, wherein, described conveyer and described receiver carry out respectively transmitting in same one end of a HDMI (High Definition Multimedia Interface) Ethernet passage and receive.
17. interference elimination methods according to claim 13, wherein, described interference signal is a crosstalk signal.
18. interference elimination methods according to claim 17, wherein, described conveyer and described receiver are connected to the different port of a network switch.
19. interference elimination methods according to claim 13, wherein, described accumulative difference of injection time is that an accumulated phase difference or a cumulative frequency are poor.
20. interference elimination methods according to claim 13, wherein, when described first clock zone faster than described second clock territory and described accumulative difference of injection time reaches a clock cycle time, the step of described output digital transmission signal exports continuous 2 points of these sampling points described.
21. interference elimination methods according to claim 13, wherein, when described first clock zone is slower than described second clock territory and described accumulative difference of injection time reaches a clock cycle, the step of described output digital transmission signal does not export any sampling point.
22. interference elimination methods according to claim 13, wherein, when described accumulative difference of injection time does not reach a clock cycle, the step of described output digital transmission signal exports one of these sampling points described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110041056.8A CN102647374B (en) | 2011-02-18 | 2011-02-18 | Cross-clock domain interference cancellation device and cross-clock domain interference cancellation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110041056.8A CN102647374B (en) | 2011-02-18 | 2011-02-18 | Cross-clock domain interference cancellation device and cross-clock domain interference cancellation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102647374A CN102647374A (en) | 2012-08-22 |
| CN102647374B true CN102647374B (en) | 2015-01-28 |
Family
ID=46659956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110041056.8A Active CN102647374B (en) | 2011-02-18 | 2011-02-18 | Cross-clock domain interference cancellation device and cross-clock domain interference cancellation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102647374B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113098563A (en) * | 2019-12-23 | 2021-07-09 | 瑞昱半导体股份有限公司 | Interference canceller and interference cancellation method |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104601335B (en) * | 2013-11-01 | 2018-04-03 | 瑞昱半导体股份有限公司 | The network equipment of multiple transmission ports |
| US10168731B2 (en) * | 2016-07-13 | 2019-01-01 | Advanced Micro Devices, Inc. | Managing frequency changes of clock signals across different clock domains |
| CN109391275B (en) * | 2017-08-04 | 2020-06-19 | 瑞昱半导体股份有限公司 | Receiving circuit and receiving method of radio frequency signal of wireless communication system |
| TWI718808B (en) | 2019-12-16 | 2021-02-11 | 瑞昱半導體股份有限公司 | Interference canceller and method for cancelling interference |
| CN112698363B (en) * | 2020-12-29 | 2024-04-16 | 成都国星通信有限公司 | High-precision data acquisition method and acquisition circuit for Beidou anti-interference antenna |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6307905B1 (en) * | 1998-11-09 | 2001-10-23 | Broadcom Corporation | Switching noise reduction in a multi-clock domain transceiver |
| CN101488780A (en) * | 2008-01-15 | 2009-07-22 | 瑞昱半导体股份有限公司 | Network apparatus for eliminating interference between transmission interfaces and method thereof |
-
2011
- 2011-02-18 CN CN201110041056.8A patent/CN102647374B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6307905B1 (en) * | 1998-11-09 | 2001-10-23 | Broadcom Corporation | Switching noise reduction in a multi-clock domain transceiver |
| CN101488780A (en) * | 2008-01-15 | 2009-07-22 | 瑞昱半导体股份有限公司 | Network apparatus for eliminating interference between transmission interfaces and method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113098563A (en) * | 2019-12-23 | 2021-07-09 | 瑞昱半导体股份有限公司 | Interference canceller and interference cancellation method |
| CN113098563B (en) * | 2019-12-23 | 2022-11-11 | 瑞昱半导体股份有限公司 | Interference canceller and interference cancellation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102647374A (en) | 2012-08-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102647374B (en) | Cross-clock domain interference cancellation device and cross-clock domain interference cancellation method | |
| TWI462493B (en) | Apparatus and method for cross clock domain interference cancellation | |
| US10809297B2 (en) | Eye opening measurement circuit calculating difference between sigma levels, receiver including the same, and method for measuring eye opening | |
| US7880543B2 (en) | Data transmitting circuit and transmitting method | |
| US8477056B2 (en) | Method, system, and apparatus for interpolating an output of an analog-to-digital converter | |
| EP2965470B1 (en) | High-resolution link-path delay estimator and method for estimating a signal-path delay | |
| US9225367B2 (en) | Decision feedback equalizer and receiver | |
| US6898379B2 (en) | System and method for reducing interference in an optical data stream | |
| US5384806A (en) | Modem with time-invariant echo path | |
| US7590077B2 (en) | Canceller device and data transmission system | |
| US9577705B2 (en) | Network apparatus with multiple communication ports | |
| EP1484844B1 (en) | Spectrum spread reception apparatus | |
| CN107370720B (en) | Multi-protocol and multi-data rate communications | |
| US8472561B2 (en) | Receiver circuit | |
| CN112118063B (en) | Clock synchronization device, optical transmitter, optical receiver and method | |
| US8320503B2 (en) | Receiver | |
| CN110113074B (en) | High-speed pseudo code parallel capturing and tracking method based on FPGA | |
| US7236463B2 (en) | Transceiver for echo and near-end crosstalk cancellation without loop timing configuration | |
| US8204152B2 (en) | Digitally synchronized receiving device and associated signal processing method | |
| CN101471765B (en) | Network device and method for processing network signal | |
| CN104601335A (en) | Network device with a plurality of transmission ports | |
| US8295421B1 (en) | Data communications circuitry with high jitter tolerance | |
| Vijayan | Energy-efficient MAC for Wireless Sensor Networks | |
| CN106911413A (en) | A kind of overlapped time division multiplexing modulator approach, apparatus and system | |
| JPH0787405B2 (en) | Eco-removal device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |