CN102646452B - Programmable memory and its writing and reading method - Google Patents

Abstract

The present invention provides a programmable memory and a writing and reading method thereof, wherein the programmable memory comprises a plurality of single-time programmable memory cells, a search unit, a writing unit and a reading unit. The plurality of single-time programmable memory cells correspond to a plurality of addresses. The searching unit is used to search for the closest writable programmable memory cell from the plurality of single-time programmable memory cells in a writing operation, or to search for the last group of programmed memory cells from the plurality of single-time programmable memory cells in a reading operation. The writing unit is used to write the bit length of an input data and the input data immediately from the closest writable programmable memory cell. The reading unit is used to read data sequentially from the last group of programmed memory cells. The programmable memory comprising a plurality of single-time programmable memory cells provided by the present invention has the advantage of reasonable application of storage space.

Description

Programmable memory and its writing and reading method

technical field

The invention relates to a programmable memory and its writing and reading method, in particular to a programmable memory including a plurality of one-time programmable memory units and its writing and reading method.

Background technique

In the manufacturing process of integrated circuits, due to the variation of process parameters between equipment and machines, after the completion of individual integrated circuit manufacturing, there is a gap between each batch of goods (lot) and goods, and between each wafer (wafer) and wafer. Between, and even between each die on the same wafer, there are varying degrees of variation in process parameters, resulting in integrated circuit components, such as resistors, capacitors, transistors, etc., resulting in variations in component parameters Variety. Therefore, the frequency or output voltage of a circuit composed of components, such as an oscillator or a voltage regulator (Voltage Regulator), will deviate from the design value. If the parameter variation of these circuits is too large and exceeds the error range specified in the specification, it will be judged as a defective product during testing. Therefore, integrated circuit manufacturers often need to perform fine-tuning steps to correct circuit errors, so as to improve manufacturing yield (yield). Generally speaking, one-time programming (OTP) elements such as fuses or metal wires are mostly used in the fine-tuning step to achieve the fine-tuning function.

Generally, OTP adjustment methods commonly used in integrated circuits are laser trimming (lasertrim) or fuse repairing (polyfuse or E-fuse). The laser repair method uses groups of OTP elements, such as metal wire segments, to perform a programming step. During the programming process, a high-energy laser is used to burn away the various metal wire segments. On the other hand, the fuse repair method uses multiple sets of OTP elements, such as polysilicon lines or metal lines, to perform the programming step. During the programming process, high current or voltage is used to burn out different polysilicon line segments or metal line segments. The above programming process is an irreversible destructive action, that is, these OTP components cannot be used again after programming.

In order to achieve the purpose of multiple programming, multiple programmable (Multiple-Time Programming, hereinafter referred to as MTP) components, such as: erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM) , Flash memory (FLASHMEMORY) and other MTP components can be used to achieve the purpose of multiple programming. However, MTP components require additional circuits and complex process steps to obtain, and their process costs are high, and are highly related to semiconductor processes, so it is not easy to disperse production capacity risks.

Therefore, if the OTP element can be used to achieve multiple programmable functions, the manufacturing steps and costs can be reduced, and the flexibility of multiple settings can be maintained. In the prior art, US Patent Publication No. 6728137 discloses a programmable memory architecture. Referring to FIG. 1 , the programmable memory 10 utilizes multiple sets of OTP memory blocks 15 to achieve multiple programmable functions. The programmable memory 10 controls the circuit 11 to write and read data through the column decoder 12 and the row decoder 13 . During operation, the programmable memory 10 must additionally use the recording element 14 to record which one or which one-time programmable memory blocks 15 have been programmed.

In the programmable memory 10 in the known architecture, each time data is rewritten, no matter how big the bit length of the data is, it will be written into a new set of one-time programmable memory elements. Therefore, even if the data to be written is only 1-bit in length, the conventional method uses a complete set of one-time programmable memory elements to store the data. In other words, the conventional architecture wastes extra memory space when writing input data.

Based on the above reasons, the industry urgently needs a programmable memory including a plurality of one-time programmable memory cells to solve the above problems.

Contents of the invention

In order to solve the above-mentioned problems in the prior art, the present invention discloses a programmable memory and its writing and reading methods.

According to an embodiment of the present invention, the programmable memory includes a plurality of one-time programmable memory units, a search unit, a write unit and a read unit. The multiple one-time programmable memory cells correspond to multiple addresses. The search unit is used for searching the closest writable programmable memory cell from the plurality of one-time programmable memory cells in a write operation, or from the plurality of one-time programmable memory cells in a read operation Among the programmable memory cells, the last group of programmed memory cells is searched. The writing unit is used for writing the bit length of an input data and the input data from the closest writable programmable memory unit. The read unit is used for sequentially reading data from the last group of programmed memory cells.

Another embodiment of the present invention discloses a method for writing a programmable memory, wherein the programmable memory includes a plurality of one-time programmable memory cells corresponding to a plurality of addresses. The writing method comprises the steps of: searching for the closest writable programmable memory unit from a start address; and performing the following data writing steps from the closest writable programmable memory unit: writing an input the bit length of the data; and writing the input data.

Yet another embodiment of the present invention discloses a method for reading a programmable memory, wherein the programmable memory includes a plurality of one-time programmable memory cells corresponding to a plurality of addresses. Data is written in the programmable memory according to the writing method disclosed in the above-mentioned embodiment examples. The reading method includes the following steps: searching the last group of programmed memory cells from a starting address; and sequentially reading data from the last group of programmed memory cells.

The programmable memory comprising a plurality of one-time programmable memory units provided by the present invention has the advantage of rational application of storage space.

Description of drawings

FIG. 1 is a schematic block diagram showing a known programmable memory;

2 is a schematic block diagram of a programmable memory according to an embodiment of the present invention;

3 is a flowchart of a writing method of a programmable memory according to an embodiment of the present invention;

FIG. 4 is a schematic block diagram showing the search unit according to an embodiment of the present invention;

Fig. 5 shows the writing mode of the programmable memory of an embodiment of the present invention;

6 is a flowchart of a method for reading a programmable memory according to an embodiment of the present invention; and

FIG. 7 shows a reading method of a programmable memory according to an embodiment of the present invention.

The reference numerals in the above-mentioned accompanying drawings are explained as follows:

10 programmable memories

11 control circuit

12-column decoder

13 line decoder

14 recording elements

15OTP memory block

20 programmable memories

21 Examination unit

22 memory array

24 search unit

242 address given unit

244 inspection units

246 displacement units

26 write units

28 read units

100, 200, 300OTP memory cells

110, 220, 330 marking column

Steps from S20 to S22

Steps S50-S52

detailed description

The direction of the present invention discussed here is a programmable memory and its writing and reading methods. In order to have a thorough understanding of the present invention, detailed steps and structures will be presented in the following description. It is evident that the practice of the invention is not limited to specific details familiar to those skilled in the relevant art. In other instances, well-known structures or steps are not described in detail in order to avoid unnecessarily limiting the invention. The preferred embodiments of the present invention will be described in detail as follows, but in addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited, it is based on the appended claims allow.

In order to explain the writing and reading method of the programmable memory of the present invention more smoothly, the programmable memory architecture implementing the method of the present invention will first be described below. FIG. 2 is a schematic block diagram of a programmable memory 20 according to an embodiment of the present invention, which includes a plurality of one-time programmable (OTP) memory units 22 , a search unit 24 , a write unit 26 and a read unit 28 . The OTP memory cells 100 , 200 and 300 are located in a memory array 22 . The search unit 24 is designed to search for the closest writable programmable memory cell from the memory array 22 in a write operation, or to search for the last set of programmed memory cells in the memory array 22 in a read operation. memory unit. The writing unit 26 is designed to write the bit length of an input data and the input data from the nearest writable programmable memory cell immediately. The read unit 28 is designed to sequentially read data from the last group of programmed memory cells.

Referring to FIG. 2 , in an embodiment of the present invention, the programmable memory 20 further includes a checking unit 21 for checking the remaining bit length of the programmable memory 20 . The checking unit 21 is designed to read the remaining bit length of the programmable memory 20 and compare the remaining bit length with the bit length of a data to be input Data_in. When the remaining bit length is greater than the bit length of the input data Data_in, the programmable memory 20 starts to perform the data writing step.

FIG. 3 is a flowchart of a writing method of a programmable memory according to an embodiment of the present invention. The programmable memory includes a plurality of one-time programmable memory cells corresponding to a plurality of addresses. The writing method comprises the following steps: searching for the closest writable programmable memory unit from a starting address (step S20), and performing the following data writing steps from the closest writable programmable memory unit: Writing a bit length of input data and writing the input data (step S22). The writing method of the programmable memory of the present invention will be further described below.

Referring to FIG. 2 , when the programmable memory 20 performs a write operation, the search unit 24 first searches the memory array 22 for the closest writable programmable memory cell to prepare for writing data. Since the OTP memory cells in the memory array 22 are one-time programmable elements, once an OTP memory cell has been programmed, data cannot be written into the memory cell again. Therefore, the programmable memory 20 needs the search unit 24 to select unprogrammed OTP memory cells. FIG. 4 shows a schematic block diagram of the search unit 24 according to an embodiment of the present invention. The searching unit 24 includes an address setting unit 242 , a checking unit 244 and a displacement unit 246 . The address giving unit 242 is used for providing a start address or a refresh address to the memory array 22 . The check unit 244 is used for checking the written data bit length of the one-time programmable memory unit corresponding to the start address or the update address. The displacement unit 246 is used for providing the update address to the address setting unit 242 according to the checking result of the checking unit 244 .

An embodiment is now used to illustrate the operation of the programmable memory 20 of the present invention. Please refer to FIG. 4 and FIG. 5 at the same time. When the programmable memory 20 performs a write operation, the address giving unit 242 first provides a starting address, such as address “0x0000”, to the memory array 22 . Next, the checking unit 244 checks whether the OTP memory unit (memory unit 100 in this embodiment) corresponding to the address “0x0000” has been programmed. In an embodiment of the present invention, the checking unit 244 determines whether the memory unit 100 has been programmed by checking the data stored in a flag 110 of the OTP memory unit 100 . If the flag column 110 stores a bit “0”, it means that the OTP memory unit 100 has not been written with data, so the OTP memory unit 100 corresponding to the address “0x0000” is the closest writable programmable memory unit. Referring to FIG. 5 , in this embodiment, the flag column 110 stores a bit “X”, which means that the OTP memory unit 100 has been programmed, and data of X-bit length has been written. Therefore, the shift unit 246 adds up the bit “0x0000” and the written bit length (here, X bit length) to obtain an update address (address “0x0000+X”).

Next, the address giving unit 242 provides the update address (address “0x0000+X”) to the memory array 22 . The check unit 244 checks the written data bit length of the corresponding OTP memory unit (the memory unit 200 in this embodiment) according to the update address. As shown in FIG. 5, the OTP memory cell 200 has been written with data of Y-bit length. Therefore, the shifting unit 246 sums the address “0x0000+X” and the written length of Y bits again to obtain the next update address (address “0x0000+X+Y”).

Next, the address giving unit 242 provides the next update address (address “0x0000+X+Y”) to the memory array 22 . The check unit 244 checks the written data bit length of the corresponding OTP memory unit (the memory unit 300 in this embodiment) according to the update address. As shown in Figure 5, the label column 330 in the OTP memory unit 300 stores a bit "0", which means that the OTP memory unit 300 has not yet written data, so the OTP memory unit 300 corresponding to the address "0x0000+X+Y" That is, the closest writable programmable memory cell.

Compared with the conventional architecture, the programmable memory 20 disclosed in the present invention uses the flag column of the OTP memory cell to determine whether the memory cell has been programmed. Therefore, the programmable memory 20 disclosed in the present invention does not require additional recording elements to record programmed OTP memory cells. In addition, the programmable memory 20 configures the memory space according to the bit length of the data each time when rewriting data, and then records the written data bit length in the label column. Therefore, only by checking the data stored in the label column of the OTP memory unit, the latest address of the memory unit to which data is written this time can be known. In other words, the storage space of the memory unit can be fully utilized by using the programmable memory 20 disclosed in the present invention.

On the other hand, after the input data Data_in is written into the OTP memory cells in the memory array 22 , a read step is performed to read the written data. FIG. 6 is a flowchart of a method for reading a programmable memory according to an embodiment of the present invention. After writing data according to the aforementioned steps, the reading method includes the following steps: searching for the last group of programmed memory cells from a starting address (step S50), and reading sequentially from the last group of programmed memory cells. Get data (step S52). Now, an embodiment is used to illustrate the reading method of the programmable memory 10 of the present invention.

Please refer to FIG. 4 and FIG. 7 at the same time. When the programmable memory 20 performs a read operation, the search unit 24 searches the last group of programmed memory cells from the memory array 22 to prepare for reading data. During operation, firstly, the address giving unit 242 provides a start address, such as address “0x0000”, to the memory array 22 . Next, the checking unit 244 checks the written data bit length of the OTP memory unit (the memory unit 100 in this embodiment) corresponding to the address “0x0000”. In this embodiment, the checking unit 244 checks the data stored in the label column 110 of the memory unit 100 . If the flag 110 stores a bit “0”, it means that no data is written into each memory cell in the memory array 22 , so the read operation will be terminated.

In this embodiment, the flag column 110 stores a bit “Z”, which means that the OTP memory unit 100 has been programmed, and the data of Z-bit length has been written. Therefore, the shift unit 246 sums the bit “0x0000” and the written bit length (here, Z bit length) to obtain an update address (address “0x0000+Z”). Next, the address giving unit 242 provides the update address (address “0x0000+Z”) to the memory array 22 . The checking unit 244 checks the written data bit length of the memory unit (the memory unit 200 in this embodiment) corresponding to the address “0x0000+Z”. If the written data bit length of the memory unit is equal to zero, then the previous address of the address “0x0000+Z”, that is, the address “0x0000”, the corresponding OTP memory unit 100 is the last group of programmed optimized memory cells.

In addition, if the written data bit length of the memory unit corresponding to the address "0x0000+Z" is greater than zero, the displacement unit 246 adds the address "0x0000+Z" and the written bit length again to obtain Get another updated address. The above steps are then repeated to select the last group of programmed memory cells from the OTP memory cells according to the previous address of another update address. The reading unit 28 sequentially reads and writes data from the last group of programmed memory cells.

Each unit according to an embodiment of the present invention may be realized by all hardware, all software, or elements including hardware and software. Furthermore, the unit can also be implemented by a computer program product. The computer program product may be accessed from a computer usable or computer readable medium providing program code for execution by or connected to a computer or any instruction execution system. The computer-usable or computer-readable medium can be any device that can contain, store, communicate, propagate, or transmit programs for execution by or connected to a computer or any instruction execution system.

The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to the disclosed embodiments, but should include various replacements and modifications that do not depart from the present invention, and should be covered by the appended claims.

Claims (15)

1. A writing method of a programmable memory, the programmable memory comprises a plurality of one-time programmable memory cells, and the multiple one-time programmable memory cells correspond to multiple addresses, and the writing method comprises the following steps: searching for the closest writable programmable memory cell from a starting address; read the remaining bit length of the programmable memory; comparing the remaining bit length with a bit length of an input data; and When the remaining bit length is greater than the bit length of the input data, the following data writing steps are performed immediately from the closest writable programmable memory unit: the bit length of the input data to be written; and Write the input data. 2. The writing method as claimed in claim 1, wherein the step of searching for the closest writable programmable memory unit from a starting address comprises the following steps: From the start address, checking the written data bit length of the corresponding one-time programmable memory cell; and According to the checking result, the closest writable programmable memory cell is selected to write the input data next to it. 3. The writing method as claimed in claim 2, wherein the step of checking the written data bit length of the corresponding one-time programmable memory unit from the starting address comprises the following steps: (a1) Read the written data bit length of the one-time programmable memory unit corresponding to the start address, wherein the written data bit length is greater than zero; (a2) adding up the starting address and the written bit length to obtain an address one at a time; (a3) taking the next address as an updated initial address, repeating the steps above until the length of the written data bit of the one-time programmable memory unit corresponding to the updated initial address is equal to zero; and The one-time programmable memory unit corresponding to step (a3) is designated as the closest writable programmable memory unit. 4. The writing method as claimed in claim 2, wherein the step of checking the written data bit length of the corresponding one-time programmable memory unit from the starting address comprises the following steps: reading the written data bit length of the one-time programmable memory cell corresponding to the start address, wherein the data bit length is equal to zero; and The one-time programmable memory unit corresponding to the starting address is designated as the closest writable programmable memory unit. 5. The writing method as claimed in claim 1, wherein each one-time programmable memory cell has a data bit storage area with a length of one bit. 6. A method for reading a programmable memory, the programmable memory includes a plurality of one-time programmable memory cells corresponding to multiple addresses, and the programmable memory writes data according to the writing method as claimed in claim 1, The read method includes the following steps: searching for the last set of programmed memory cells from a starting address; and Data is sequentially read from the last group of programmed memory cells. 7. The read method as claimed in claim 6, wherein the step of searching the last group of programmed memory cells from a starting address comprises the following steps: From the start address, checking the written data bit length of the corresponding one-time programmable memory cell; and According to the checking result, the last group of programmed memory cells is selected to read data sequentially. 8. The reading method as claimed in claim 7, wherein the step of checking the written data bit length of the corresponding one-time programmable memory unit from the starting address comprises the following steps: Read the written data bit length of the one-time programmable memory unit corresponding to the start address, wherein the written data bit length is greater than zero; summing up the start address and the written data bit length to obtain one-at-a-time addresses; Taking the next address as an updated starting address, repeating the above steps until the length of the written data bit of the one-time programmable memory unit corresponding to the updated starting address is equal to zero; and If the written data bit length of the one-time programmable memory cell corresponding to the updated start address is zero, return a previous address of the updated start address; and Designate the one-time programmable memory unit corresponding to the previous address as the last group of programmed memory units. 9. The read method as claimed in claim 7, wherein each one-time programmable memory cell has a data bit storage area with a length of one bit. 10. A programmable memory comprising: Multiple one-time programmable memory cells, corresponding to multiple addresses; A search unit for searching the closest writable programmable memory cell from the plurality of one-time programmable memory cells in a write operation, or from the plurality of one-time programmable memory cells in a read operation In sub-programmable memory cells, search for the last group of programmed memory cells; a writing unit for writing the bit length of an input data and the input data immediately from the nearest writable programmable memory unit; a read unit for sequentially reading data from the last group of programmed memory cells; and A checking unit is used for checking the remaining bit length of the programmable memory. 11. The programmable memory of claim 10, wherein each one-time programmable memory cell has a data bit storage area with a length of one bit. 12. The programmable memory as claimed in claim 10, wherein the search unit further comprises: an address giving unit for providing a start address or an update address to the plurality of one-time programmable memory units; A check unit, used to check the written data bit length of the one-time programmable memory unit corresponding to the start address or the update address; A displacement unit is used for providing the update address to the address given unit according to the checking result of the checking unit. 13. The programmable memory according to claim 12, wherein when the programmable memory performs the write action, when the written data bit of the one-time programmable memory unit corresponding to the start address or the update address When the element length is equal to zero, the one-time programmable memory unit corresponding to the start address or the update address is the closest writable programmable memory unit. 14. The programmable memory according to claim 12, wherein when the programmable memory performs the write action, when the length of the written data bit of the one-time programmable memory unit corresponding to the start address is greater than zero , then the displacement unit adds up the start address and the bit length to obtain the update address. 15. The programmable memory according to claim 12, wherein when the programmable memory executes the read action, when the written data bit of the one-time programmable memory unit corresponding to the start address or the update address When the element length is equal to zero, the displacement unit will provide an address before the start address or the update address to the address given unit, and the one-time programmable memory unit corresponding to the previous address is the last group programmed memory unit.