CN102623450B - Transient voltage suppressor based on field limiting ring silicon controlled structure - Google Patents
Transient voltage suppressor based on field limiting ring silicon controlled structure Download PDFInfo
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- CN102623450B CN102623450B CN201210091687.5A CN201210091687A CN102623450B CN 102623450 B CN102623450 B CN 102623450B CN 201210091687 A CN201210091687 A CN 201210091687A CN 102623450 B CN102623450 B CN 102623450B
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- injection region
- trap
- active injection
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- transient voltage
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- 230000001052 transient effect Effects 0.000 title claims abstract description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title abstract description 3
- 229910052710 silicon Inorganic materials 0.000 title abstract description 3
- 239000010703 silicon Substances 0.000 title abstract description 3
- 230000000903 blocking effect Effects 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000002347 injection Methods 0.000 claims description 95
- 239000007924 injection Substances 0.000 claims description 95
- 239000002184 metal Substances 0.000 claims description 10
- 230000002028 premature Effects 0.000 abstract description 2
- 239000007943 implant Substances 0.000 abstract 7
- 230000003068 static effect Effects 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000002800 charge carrier Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 238000005215 recombination Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000006798 recombination Effects 0.000 description 2
- 241000700605 Viruses Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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Abstract
The invention discloses a transient voltage suppressor based on a field limiting ring silicon controlled structure, which comprises a P substrate layer, wherein the P substrate layer is provided with an N well and a P well which are connected side by side. The N well is embedded with a first N+ active implant area and a first P+ active implant area, and the P well is embedded with a second P+ active implant area and a second N+ active implant area. One or two current blocking areas are embedded into the well layer composed of the N well and the P well and between the first P+ active implant area and the second N+ active implant area. In the transient voltage suppressor, the active implant areas, of which the conduction type is opposite to that of the wells, are embedded into the wells so as to form depletion layers on the surfaces of the wells and lead current to the inside of a device. The design of the transient voltage suppressor can avoid premature failure of the device due to excessive concentration of ESD (electro-static discharge) current in any of the parts of the surfaces to improve the robustness of the device.
Description
Technical field
The invention belongs to integrated circuit electrostatic defending technical field, be specifically related to a kind of Transient Voltage Suppressor based on field limiting ring SCR structure.
Background technology
It is the one of the main reasons that current electronic product lost efficacy that static discharges (ESD) problem.Along with developing rapidly of electronic information technology, current electronic device tends to miniaturization, high density and multifunction day by day, particularly as fashional consumption electronics and portable product etc. to the stricter application of mainboard area requirements, be easy to be subject to the impact of static discharge.Static is at every moment ubiquitous, in the sixties, along with the appearance to the highstrung MOS device of static, electrostatic discharge problem also arises at the historic moment, to the seventies electrostatic discharge problem more and more come seriously, the 80-90 age, along with the density of integrated circuit is increasing, the thickness of its silicon dioxide film more and more thinner (micron changes to nanometer) on the one hand, the ability to bear of static is more and more lower; On the other hand, the material producing and accumulate static is as plastics, rubber etc. are a large amount of to be used, make more and more ubiquity of static, the loss that only U.S.'s electronics industry causes because of static every year reaches hundred million dollars of hundreds ofs, therefore electrostatic breakdown has become the stealthy killer of electronics industry, is electronics industry ubiquitous " virus firmly ", has caused people's extensive concern.
The solution of the current ESD protection question for chip is normally made an electrostatic discharge protection component in the I/O of chip internal (I/O) mouthful.But along with people are more and more higher to the reliability requirement of electronic device product, merely rely on ESD protection in sheet cannot meet the demands.So will need plate level electrostatic discharge protective for a reliable electronic system.Transient Voltage Suppressor is exactly a kind of main devices of plate level electrostatic discharge protective, and it must have very high robustness; The robustness of so-called electrostatic protection device refers to that this device bears the striking capabilities of static, can weigh with the secondary failure electric current of device, and secondary failure electric current is the maximum electrostatic discharging current that electrostatic protection device can bear.
Transient Voltage Suppressor based on SCR structure is the device that robustness is higher at present, can protect preferably core circuit and avoid electrostatic damage; The structure of this device and equivalent circuit diagram are respectively as depicted in figs. 1 and 2; But this single Transient Voltage Suppressor based on common SCR structure still cannot reach the ESD protective capacities standard of plate level completely, therefore currently available technology mostly by adopting insert to refer to that structure technology further improves its robustness more; But need to expend so too large chip area, and the increase of slotting index order can make device occur can not uniform conducting problem; Therefore require high Transient Voltage Suppressor for plate level ESD protective capacities, need a kind of structure of high robust badly.
Summary of the invention
For the existing above-mentioned technological deficiency of prior art, the invention provides a kind of Transient Voltage Suppressor based on field limiting ring SCR structure, can not expend under chip area prerequisite, further the robustness of boost device.
Based on a Transient Voltage Suppressor for field limiting ring SCR structure, comprising: P substrate layer;
Described P substrate layer is provided with side by side connected N trap and P trap;
On described N trap, be embedded with an active injection region of N+ away from a side of P trap, be embedded with an active injection region of P+ near a side of P trap;
On described P trap, be embedded with the 2nd active injection region of P+ away from a side of N trap, be embedded with the 2nd active injection region of N+ near a side of N trap;
On the trap floor being formed by N trap and P trap and between the first active injection region of P+ and the 2nd active injection region of N+, be embedded with one or two current blocking district;
A described active injection region of N+ is connected by the first metal electrode with an active injection region of P+, and the 2nd described active injection region of P+ is connected by the second metal electrode with the 2nd active injection region of N+.
If the number in described current blocking district is two, Ze Zheliangge current blocking district is respectively the 3rd active injection region of P+ being embedded on N trap and is embedded in the 3rd active injection region of N+ on P trap;
If the number in described current blocking district is one and is embedded on N trap, Ze Gai current blocking district is the 3rd active injection region of P+;
If the number in described current blocking district is one and is embedded on P trap, Ze Gai current blocking district is the 3rd active injection region of N+.
Preferably, shallow-trench isolation is all passed through in a described active injection region of N+ and an active injection region of P+ and the 2nd active injection region of P+ and the 2nd active injection region of N+; Can increase dead resistance between the two, contribute to the unlatching of device.
Preferably, the doping content of described N trap is (5 × 10
16～5 × 10
17) atom/cm
3, thickness is (3～3.5) um; The doping content of P trap is (5 × 10
15～5 × 10
16) atom/cm
3, thickness is (3～3.5) um; Can effectively improve the robustness of controllable devices.
Preferably, the width of described shallow slot is (1.5～2) um, and the degree of depth is (0.2～0.5) um; Can effectively improve the opening speed of silicon-controlled device.
The equivalent electric circuit of Transient Voltage Suppressor of the present invention is made up of two triodes and two resistance; Wherein: one end of the first resistance is connected with the emitter of the second triode and forms the anode of Transient Voltage Suppressor, the other end of the first resistance is connected with the collector electrode of the first triode with the base stage of the second triode, the base stage of the first triode is connected with one end of the second resistance with the collector electrode of the second triode, and the other end of the second resistance is connected with the emitter of the first triode and forms the negative electrode of Transient Voltage Suppressor.
The first described resistance is the trap resistance of N trap, and the second resistance is the trap resistance of P trap; A described active injection region of P+, N trap and P trap emitter, base stage and the collector electrode of corresponding the first triode respectively, the 2nd active injection region of N+, P trap and N trap be emitter, base stage and the collector electrode of corresponding the first triode respectively.
Under ESD stress, after device of the present invention is triggered, ESD electric current is more concentrated in trap surface ratio, and the active injection region by embedding on trap with the conductivity type opposite of trap can form depletion layer on the surface of trap, electric current is guided into the inside of device; Such design can prevent that ESD electric current is too concentrated in surperficial somewhere, and causes device premature failure, has promoted the robustness of device.
Under larger ESD stress, device works in current state simultaneously, and the present invention can provide extra charge carrier compensation, improves the conductive capability of device; Due to extra charge carrier compensation being provided, under large current work state, there is part electric current through this active injection region, therefore near current ratio anode and the negative electrode of device is more even, is difficult for occurring local thermal failure.
Brief description of the drawings
Fig. 1 is the structural representation of the Transient Voltage Suppressor of tradition based on SCR structure.
Fig. 2 is the equivalent circuit diagram of Fig. 1.
The domain that Fig. 3 (a) is Transient Voltage Suppressor the first example of the present invention.
Fig. 3 (b) is the generalized section of Fig. 3 (a) along AA ' direction.
The domain that Fig. 4 (a) is Transient Voltage Suppressor the second example of the present invention.
Fig. 4 (b) is the generalized section of Fig. 4 (a) along AA ' direction.
The domain that Fig. 5 (a) is the third example of Transient Voltage Suppressor of the present invention.
Fig. 5 (b) is the generalized section of Fig. 5 (a) along AA ' direction.
What Fig. 6 was ESD electric current by Transient Voltage Suppressor of the present invention flows to path schematic diagram.
Fig. 7 is the current-voltage characteristic schematic diagram of traditional Transient Voltage Suppressor and Transient Voltage Suppressor of the present invention.
Embodiment
In order more specifically to describe the present invention, below in conjunction with the drawings and the specific embodiments, technical scheme of the present invention is elaborated.
Embodiment 1
As shown in Figure 3, a kind of Transient Voltage Suppressor based on field limiting ring SCR structure, comprising: P substrate layer 10;
P substrate layer 10 is provided with side by side connected N trap 21 and P trap 22; N trap 21 and P trap 22 are connected to form a PN junction side by side, and the charge carrier that this PN junction avalanche breakdown produces is for triggering the unlatching of SCR structure;
On N trap 21, be from left to right embedded with successively an active injection region 31 of N+, an active injection region 41 of P+ and the active injection region 43 of the 3rd P+; On P trap 22, be from left to right embedded with successively the 2nd active injection region 32 of N+ and the active injection region 42 of the 2nd P+;
Wherein, an active injection region 31 of N+ and the active injection region 41 of a P+ and the active injection region 32 of the 2nd N+ and the active injection region 42 of the 2nd P+ isolate by shallow slot 50, in shallow slot 50, are filled with silica; Increase the dead resistance between active injection region, contributed to the unlatching of SCR structure;
The one active injection region 31 of N+ is connected by the first metal electrode A with an active injection region 41 of P+, and the 2nd active injection region 42 of P+ is connected by the second metal electrode K with the 2nd active injection region 32 of N+.
In present embodiment, the doping content of N trap 21 is 1 × 10
17atom/cm
3, thickness is 3um; The doping content of P trap 22 is 2 × 10
16atom/cm
3, thickness is 3um; The width of shallow slot 50 is 2um, and the degree of depth is 0.3um.
As shown in Figure 2, the equivalent electric circuit of the Transient Voltage Suppressor of present embodiment is made up of two triode Q1～Q2 and two resistance R 1～R2; Wherein: one end of the first resistance R 1 is connected with the emitter of the second triode Q2 and forms the anode of Transient Voltage Suppressor, the other end of the first resistance R 1 is connected with the collector electrode of the first triode Q1 with the base stage of the second triode Q2, the base stage of the first triode Q1 is connected with one end of the second resistance R 2 with the collector electrode of the second triode Q2, and the other end of the second resistance R 2 is connected with the emitter of the first triode Q1 and forms the negative electrode of Transient Voltage Suppressor.
The first resistance R 1 is the trap resistance of N trap 21, and the second resistance R 2 is the trap resistance of P trap 22; The one active injection region 41 of P+, N trap 21 and P trap 22 emitter, base stage and the collector electrode of corresponding the second triode Q2 respectively, the 2nd active injection region 32 of N+, P trap 21 and N trap 22 emitter, base stage and the collector electrode of corresponding the first triode Q1 respectively.
Embodiment 2
As shown in Figure 4, a kind of Transient Voltage Suppressor based on field limiting ring SCR structure, comprising: P substrate layer 10;
P substrate layer 10 is provided with side by side connected N trap 21 and P trap 22; N trap 21 and P trap 22 are connected to form a PN junction side by side, and the charge carrier that this PN junction avalanche breakdown produces is for triggering the unlatching of SCR structure;
On N trap 21, be from left to right embedded with successively an active injection region 31 of N+ and the active injection region 41 of a P+; On P trap 22, be from left to right embedded with successively the 3rd active injection region 33 of N+, the 2nd active injection region 32 of N+ and the active injection region 42 of the 2nd P+;
Wherein, an active injection region 31 of N+ and the active injection region 41 of a P+ and the active injection region 32 of the 2nd N+ and the active injection region 42 of the 2nd P+ isolate by shallow slot 50, in shallow slot 50, are filled with silica; Increase the dead resistance between active injection region, contributed to the unlatching of SCR structure;
The one active injection region 31 of N+ is connected by the first metal electrode A with an active injection region 41 of P+, and the 2nd active injection region 42 of P+ is connected by the second metal electrode K with the 2nd active injection region 32 of N+.
In present embodiment, the doping content of N trap 21 is 1 × 10
17atom/cm
3, thickness is 3um; The doping content of P trap 22 is 2 × 10
16atom/cm
3, thickness is 3um; The width of shallow slot 50 is 2um, and the degree of depth is 0.3um.
The equivalent electric circuit of the Transient Voltage Suppressor of present embodiment is identical with embodiment 1.
Embodiment 3
As shown in Figure 5, a kind of Transient Voltage Suppressor based on field limiting ring SCR structure, comprising: P substrate layer 10;
P substrate layer 10 is provided with side by side connected N trap 21 and P trap 22; N trap 21 and P trap 22 are connected to form a PN junction side by side, and the charge carrier that this PN junction avalanche breakdown produces is for triggering the unlatching of SCR structure;
On N trap 21, be from left to right embedded with successively an active injection region 31 of N+, an active injection region 41 of P+ and the active injection region 43 of the 3rd P+; On P trap 22, be from left to right embedded with successively the 3rd active injection region 33 of N+, the 2nd active injection region 32 of N+ and the active injection region 42 of the 2nd P+;
Wherein, an active injection region 31 of N+ and the active injection region 41 of a P+ and the active injection region 32 of the 2nd N+ and the active injection region 42 of the 2nd P+ isolate by shallow slot 50, in shallow slot 50, are filled with silica; Increase the dead resistance between active injection region, contributed to the unlatching of SCR structure;
The one active injection region 31 of N+ is connected by the first metal electrode A with an active injection region 41 of P+, and the 2nd active injection region 42 of P+ is connected by the second metal electrode K with the 2nd active injection region 32 of N+.
In present embodiment, the doping content of N trap 21 is 1 × 10
17atom/cm
3, thickness is 3um; The doping content of P trap 22 is 2 × 10
16atom/cm
3, thickness is 3um; The width of shallow slot 50 is 2um, and the degree of depth is 0.3um.
The equivalent electric circuit of the Transient Voltage Suppressor of present embodiment is identical with embodiment 1.
Taking the device architecture of embodiment 3 as example, under large current work state, due to conductivity modulation effect, in N trap 21 and P trap 22, excess carrier are full of, i.e. superfluous electronics and hole.Portions of electronics in N trap 21 will diffuse into the 3rd active injection region 43 of P+, and with the hole-recombination in the 3rd active injection region 43 of P+, some electronics enters the hole-recombination in an active injection region 41 of P+ and the active injection region 41 of a P+; Part hole in P trap 22 will diffuse into the 3rd active injection region 33 of N+, and with the electron recombination in the 3rd active injection region 33 of N+, some hole enters the electron recombination in the 2nd active injection region 32 of N+ and the active injection region 32 of the 2nd N+; The formation in these electronics and hole flows to as shown in Figure 6, therefore extra the 3rd active injection region 43 of P+ and the active injection region 33 of the 3rd N+ of inserting makes the CURRENT DISTRIBUTION of device inside more even, be not easy local inefficacy occurs, thereby improved the secondary failure electric current of device.
As shown in Figure 7, under the device widths of 40um, the secondary failure electric current of the Transient Voltage Suppressor of traditional SCR structure is 3.2A, and the secondary failure electric current of present embodiment Transient Voltage Suppressor can rise to 5.6A; Therefore under identical device widths, the relative prior art of the present invention has obviously improved the secondary failure electric current of device.
Claims (3)
1. the Transient Voltage Suppressor based on field limiting ring SCR structure, comprises P substrate layer (10); It is characterized in that:
Described P substrate layer (10) is provided with side by side connected N trap (21) and P trap (22);
Described N trap (21) is upper is embedded with an active injection region of N+ (31) away from a side of P trap (22), is embedded with an active injection region of P+ (41) near a side of P trap (22);
Described P trap (22) is upper is embedded with the 2nd active injection region of P+ (42) away from a side of N trap (21), is embedded with the 2nd active injection region of N+ (32) near a side of N trap (21);
On the trap floor being formed by N trap (21) and P trap (22) and be positioned between an active injection region of P+ (41) and the 2nd active injection region of N+ (32) and be embedded with one or two current blocking district;
A described active injection region of N+ (31) is connected by the first metal electrode with an active injection region of P+ (41), and the 2nd described active injection region of P+ (42) is connected by the second metal electrode with the 2nd active injection region of N+ (32);
If the number in described current blocking district is two, Ze Zheliangge current blocking district is respectively and is embedded in the 3rd active injection region of P+ (43) on N trap (21) and is embedded in the 3rd active injection region of N+ (33) on P trap (22);
If the number in described current blocking district is one and to be embedded in N trap (21) upper, Ze Gai current blocking district is the 3rd active injection region of P+ (43);
If the number in described current blocking district is one and to be embedded in P trap (22) upper, Ze Gai current blocking district is the 3rd active injection region of N+ (33);
A described active injection region of N+ (31) all isolates by shallow slot (50) with the 2nd active injection region of N+ (32) with an active injection region of P+ (41) and the 2nd active injection region of P+ (42).
2. the Transient Voltage Suppressor based on field limiting ring SCR structure according to claim 1, is characterized in that: the doping content of described N trap (21) is 5 × 10
16～5 × 10
17atom/cm
3, thickness is 3～3.5um; The doping content of P trap (22) is 5 × 10
15～5 × 10
16atom/cm
3, thickness is 3～3.5um.
3. the Transient Voltage Suppressor based on field limiting ring SCR structure according to claim 1, is characterized in that: the width of described shallow slot (50) is 1.5～2um, and the degree of depth is 0.2～0.5um.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210091687.5A CN102623450B (en) | 2012-03-30 | 2012-03-30 | Transient voltage suppressor based on field limiting ring silicon controlled structure |
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|---|---|---|---|
| CN201210091687.5A CN102623450B (en) | 2012-03-30 | 2012-03-30 | Transient voltage suppressor based on field limiting ring silicon controlled structure |
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| CN102623450A CN102623450A (en) | 2012-08-01 |
| CN102623450B true CN102623450B (en) | 2014-12-03 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103354229B (en) * | 2013-07-11 | 2016-04-27 | 江苏艾伦摩尔微电子科技有限公司 | A kind of Breaking-through transient voltage inhibitor |
| CN107731811B (en) * | 2017-09-06 | 2020-03-27 | 电子科技大学 | SCR device for ESD protection triggered by longitudinal BJT |
| US10141300B1 (en) * | 2017-10-19 | 2018-11-27 | Alpha And Omega Semiconductor (Cayman) Ltd. | Low capacitance transient voltage suppressor |
| CN109166850A (en) * | 2018-10-09 | 2019-01-08 | 浙江大学昆山创新中心 | The diode triggered of Integrated circuit electrostatic protection is silicon-controlled |
| CN114121944B (en) * | 2022-01-27 | 2022-05-17 | 江苏应能微电子有限公司 | Transient voltage suppression protection device with high maintenance voltage and electrostatic discharge circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101017819A (en) * | 2007-03-05 | 2007-08-15 | 浙江大学 | A protection circuit for constructing ESD release channel with the polycrystalline silicon |
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| US20030042498A1 (en) * | 2001-08-30 | 2003-03-06 | Ming-Dou Ker | Method of forming a substrate-triggered SCR device in CMOS technology |
| US7332748B2 (en) * | 2002-12-04 | 2008-02-19 | Nec Electronics Corporation | Electro-static discharge protection device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101017819A (en) * | 2007-03-05 | 2007-08-15 | 浙江大学 | A protection circuit for constructing ESD release channel with the polycrystalline silicon |
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