CN102623362A - Three-dimensional packaging method and package - Google Patents
Three-dimensional packaging method and package Download PDFInfo
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- CN102623362A CN102623362A CN201110449518XA CN201110449518A CN102623362A CN 102623362 A CN102623362 A CN 102623362A CN 201110449518X A CN201110449518X A CN 201110449518XA CN 201110449518 A CN201110449518 A CN 201110449518A CN 102623362 A CN102623362 A CN 102623362A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
The invention provides a three-dimensional packaging method and a package. The method includes the steps: providing a semiconductor substrate and a support substrate; forming insulating layers on the surfaces of the semiconductor substrate and/or the support substrate; attaching the semiconductor substrate and the support substrate together by the aid of the insulating layers serving as middle layers; removing a support layer and a heavily doped layer in the semiconductor substrate by means of an etch-stop process; forming a plurality of through holes in a device layer, leading the positions of the through holes to correspond to those of pads of semiconductor devices and exposing the pads of the semiconductor devices; and filling and leveling up the through holes by the aid of conductive fillers. The semiconductor substrate sequentially comprises the support layer, the heavily doped layer and the device layer, wherein the heavily doped layer is arranged on the surface of the support layer, and the device layer is arranged on the surface of the heavily doped layer and comprises at least one semiconductor device. The three-dimensional packaging method and the package have the advantage that the thickness of the thinned substrates is decreased while evenness of the surfaces of the substrates is ensured.
Description
Technical field
The present invention relates to the semiconductor packages field, relate in particular to a kind of three-dimension packaging method and packaging body.
Background technology
Following electronic system need satisfy following several aspect requirement day by day: volume is little, in light weight, high frequency and high-speed cruising, low-power consumption, sensitivity, multi-functional and low-cost.And three-dimension packaging satisfies the approach of a very attractive of this several aspects requirement just, and it has the advantage that reduces volume and increase backing material utilance.
Advanced three-dimensional packaging technology requires the continuous attenuate of thickness of chip; The Semiconductor substrate thinning back side of having made device is the very important operation in the package fabrication process; Superfine grinding, grinding, polishing, corrosion obtain extensive use in the Semiconductor substrate technique for thinning back side; Chip behind the attenuate can improve thermal transpiration efficient, mechanical performance, electrical property, reduce the Chip Packaging volume, alleviates the scribing processing capacity.With the silicon substrate is example, and at present, the silicon substrate of making device of diameter 200mm can be thinned to 0.12-0.15mm, and diameter 300mm silicon substrate will reach this level also need adopt technology such as grind after chemico-mechanical polishing, plasma etching, the first scribing.This technology development trend from now on is the thickness that is thinned to below the 0.05mm.The effective thickness of circuit layer is generally 5-10 μ m on the silicon substrate, and for guaranteeing its function, and certain support thickness, the thickness limit of silicon substrate attenuate are arranged is 20-30 μ m.The average thickness of the silicon substrate of diameter 300mm is 775 μ m in the market, and the average thickness of the silicon substrate of diameter 200mm is 725 μ m, and so thick substrate is for guaranteeing in chip manufacturing, testing, transport enough intensity is arranged in the process; Therefore; After circuit layer completes, need carry out thinning back side to it, substrate is thin more; Its pliability is good more, and the stress that caused by external impacts is also more little.
But in the present three-dimension packaging technology, existing thinning technique is difficult in the substrate thinning that is thinned also can be satisfied photoetching to the evenness requirement time 50 μ m.
Therefore, present integrated circuit manufacturing field needs a kind of thickness that can reduce the substrate that is thinned, and can improve the three-dimensional packaging technology of the evenness on surface.
Summary of the invention
Technical problem to be solved by this invention is, a kind of three-dimension packaging method and packaging body are provided, and guarantees the evenness of substrate surface when can reduce the thickness of the substrate that is thinned.
In order to address the above problem; The invention provides a kind of three-dimension packaging method; Comprise the steps: to provide Semiconductor substrate and support substrates; Said Semiconductor substrate comprises the heavily doped layer of supporting layer, support layer surface and the device layer on heavily doped layer surface successively, comprises at least one semiconductor device in the said device layer; Surface in Semiconductor substrate and/or support substrates forms insulating barrier; With said insulating barrier is the intermediate layer, and said Semiconductor substrate and support substrates are fit together; Adopt etch stop technology to remove supporting layer and heavily doped layer in the said Semiconductor substrate; In device layer, form a plurality of perforations, the position of said perforation is corresponding with the position of the pad of semiconductor device, and exposes the pad of semiconductor device; Adopt conductive filler to fill and lead up said perforation.
As optional technical scheme, said Semiconductor substrate adopts following steps to form: Semiconductor substrate is provided; Doped chemical is injected in the Semiconductor substrate, forms heavily doped layer, and the while goes out device layer in the surface isolation of Semiconductor substrate; In device layer, make at least one semiconductor device.
As optional technical scheme, the material of said Semiconductor substrate is a monocrystalline silicon, and the doped chemical in the said heavily doped layer is a boron.
As optional technical scheme, the material of said insulating barrier is selected from any one in silica, silicon nitride and the silicon oxynitride.
As optional technical scheme, said conductive filler is a metal.
As optional technical scheme, the material of said support substrates is selected from any one in monocrystalline silicon, sapphire, carborundum and the glass.
As optional technical scheme, preparation in advance has complete integrated circuit structure or single tube in the said support substrates.
The present invention also provides a kind of packaging body that adopts said method to form; Comprise support substrates, the insulating barrier on support substrates surface and the device layer of surface of insulating layer successively; Comprise at least one semiconductor device in the said device layer, have a plurality of perforations in the said device layer, the position of said perforation is corresponding with the position of the pad of semiconductor device; And expose the pad of semiconductor device, be filled with conductive filler in the said perforation.
As optional technical scheme, the material of said insulating barrier is selected from any one in silica, silicon nitride and the silicon oxynitride.
As optional technical scheme, said conductive filler is a metal.
As optional technical scheme, the material of said Semiconductor substrate is a monocrystalline silicon, and the material of said support substrates is selected from any one in monocrystalline silicon, sapphire, carborundum and the glass.
The invention has the advantages that, through below device layer, forming heavily doped layer, and after applying, adopt etch stop technology to remove heavily doped layer, can in the thickness of the substrate that reduction is thinned, guarantee the evenness of substrate surface.
Description of drawings
It shown in the accompanying drawing 1 flow chart of steps of the said method of this embodiment.
Accompanying drawing 2A is to shown in the accompanying drawing 2H being the process schematic representation of the said method of this embodiment.
Embodiment
Elaborate below in conjunction with the embodiment of accompanying drawing to three-dimension packaging method provided by the invention and packaging body.
Be the flow chart of steps of the said method of this embodiment shown in the accompanying drawing 1, comprise: step S101 provides Semiconductor substrate; Step S102 is injected into doped chemical in the Semiconductor substrate, forms heavily doped layer, and the while goes out device layer in the surface isolation of Semiconductor substrate; Step S103 makes at least one semiconductor device in device layer; Step S110 provides support substrate; Step S111 forms insulating barrier on the surface of support substrates; Step S120 is the intermediate layer with said insulating barrier, and said Semiconductor substrate and support substrates are fit together; Step S130 adopts etch stop technology to remove supporting layer and heavily doped layer in the said Semiconductor substrate; Step S140 forms a plurality of perforations in device layer, the position of said perforation is corresponding with the position of the pad of semiconductor device, and exposes the pad of semiconductor device; Step S150 adopts conductive filler to fill and lead up said perforation.
Shown in the accompanying drawing 2A, refer step S101 provides Semiconductor substrate 200.In this embodiment, the material of said Semiconductor substrate 200 is a monocrystalline silicon, and resistivity 0.1 to 1000 Ω .cm is optimized for 10 to 20 Ω .cm.That optimizes carries out insulating to Semiconductor substrate 200 surfaces and handles, and also can not carry out this insulating and handle, and generates SiO after the insulation processing on the surface
2Layer also can be Si
3N
4Or other insulating medium layer, be optimized for SiO
2, the generation method can be CVD, LPCVD, PECVD etc., is optimized for oxidation, and oxidation technology can be that wet oxygen also can be dried oxygen, also can be both combinations, and oxidated layer thickness is not more than 500nm, is optimized for 50 nm.In other embodiment, the material of Semiconductor substrate 200 can be any one common semi-conducting material, for example germanium, carborundum, gallium nitride, GaAs, aluminium nitride etc.
Shown in the accompanying drawing 2B, refer step S102 is injected into doped chemical in the Semiconductor substrate 200, forms heavily doped layer 201, and the while goes out device layer 202 and supporting layer 203 in the surface isolation of Semiconductor substrate.In this embodiment, the doped chemical in the said heavily doped layer 201 is a boron.The ion that injects is boron ion or BF
2Molecule, implantation dosage are 5 * 10
14To 5 * 10
17Cm
-2, optimizing implantation dosage is 3 * 10
16Cm
-2, the concentration at the distribution peak value place of boron is 6 * 10
18To 6 * 10
22Cm
-3, be optimized for 8 * 10
20Cm
-3The selective rule of the implantation dosage of boron does, the resistivity of the boron implanted layer of optimization should be less than 0.1 Ω .cm, and the injection energy is 1keV to 1000keV.Inject degree of depth final devices layer 202 thickness and determine that preference rule should be optimized for 100nm greater than 50nm to 5000nm for injecting the thickness that the degree of depth should be slightly larger than resulting devices layer 202.For example the final top layer silicon thickness of device layer is 200nm, and then its injection degree of depth should be about 300 nm.
After above-mentioned steps is implemented to finish,, can also further implement the step that thickens of a homogeneity extension if the thickness of device layer 202 can not meet the demands.Epitaxial device is preferably the reduced pressure epitaxy stove; For the homoepitaxy of monocrystalline substrate; Reacting gas is dichloro hydrogen silicon, silane or trichlorosilane, and growth temperature is 400 to 1300 ℃, is optimized for 700 ℃; The advantage of low-temperature epitaxy is to guarantee the heavy doping boron indiffusion in the heavily doped layer 201 that epitaxial thickness is 10nm to 20 μ m.Thickness after the extension is by the silicon thickness decision of device layer 202 needs, and its preferred prerequisite is that the thickness of silicon epitaxial layers should be reserved enough thickness surpluses for CMP like this greater than the silicon thickness of final devices layer 202 needs.
Refer step S103 makes at least one semiconductor device (not shown) in device layer 202.The substrate that is obtained based on step S102 carries out flow, prepares complete integrated circuit structure or single tube.Integrated circuit can be to be formed through alloy-layer is interconnected by other devices such as several metal-oxide semiconductor fieldeffect transistors (MOSFETs) and electric capacity, resistance.Single tube for example can be bipolar transistor or power transistor etc.
The purpose of above step is to form a Semiconductor substrate 200 that is made up of the heavily doped layer 201 and the heavily doped layer 201 surperficial device layers 202 on supporting layer 203, supporting layer 203 surfaces.
Shown in the accompanying drawing 2C, refer step S110 provides support substrate 220.In this embodiment, support substrates 220 is monocrystalline substrate.In other execution mode, can also be SOI substrate or Ge substrate, or even sapphire, carborundum and glass substrate etc.Because support substrates 220 mainly plays the effect of supporting packaging body, the scope of therefore selecting is very wide in range.In other embodiment, preparation in advance has complete integrated circuit structure or single tube in the said support substrates, and in this embodiment, the device in support substrates and the lightly-doped layer can be aligned with each other the formation electric interconnects.
Shown in the accompanying drawing 2D, refer step S111 forms insulating barrier 240 on the surface of support substrates 220.This insulating barrier can be that silicon dioxide also can be silicon nitride, aluminium nitride or aluminium oxide etc.In other execution mode, also can be to form insulating barrier on the surface of device layer 202, perhaps all form insulating barrier on the surface of device layer 202 and support substrates 220.
Shown in the accompanying drawing 2E, refer step S120 is the intermediate layer with said insulating barrier 240, and said Semiconductor substrate 200 is fit together with support substrates 220.During said applying is selected from bonding and pastes any one is preferably stickup.Said bonding for example can be the plasma enhanced bonding, use plasma as, Ar, N
2Perhaps O
2Washed with de-ionized water is adopted on the processing wafers surface subsequently, and with two wafer bondings together, with post-reinforcing, reinforcing temperature is 100 to 800 ℃, is optimized for 300 ℃, and consolidation time is 0.5 hour to 10 hours, is optimized for 3 hours.Said stickup is to adopt glue that Semiconductor substrate 200 and support substrates 220 are linked together; If use glue; Then Semiconductor substrate 200 need not carried out the insulating processing with support substrates 220 surfaces, promptly need not form insulating barrier 240 on the surface, only needs get final product at the surfaces coated insulating cement.
Shown in the accompanying drawing 2F, refer step S130 adopts etch stop technology to remove supporting layer 203 and heavily doped layer 201 in the said Semiconductor substrate 200.This step for example can be at first to grind attenuate supporting layer 203, and extremely the thickness of remaining supporting layer 203 is 1 μ m to 10 μ m, is optimized for 10 μ m.Subsequently, adopt the method for spin etching, make etchant solution flow through supporting layer 203 surfaces to remove remaining supporting layer 203 to exposing heavily doped layer 201, the angular speed of spin etching is that 100 to 5000 weeks of per minute are preferred technical parameters.Less than the underspeed in per minute 100 week so that reacted residual substance promptly breaks away from the surface; Make promptly the flow through surface of substrate of corrosive liquid greater than the rotating speeds in 5000 weeks; The time of staying on the surface is too short; Thereby abundant inadequately with surface generation chemical reaction, therefore caused the waste of corrosive liquid.The etchant solution of said corrosion monocrystalline substrate is the mixed solution of catechol, ethylenediamine and water.After exposing heavily doped layer 201, adopt HNA solution rotating erosion removal heavily doped layer 201 again, the etchant solution of the corrosion monocrystalline substrate of optimization is the mixed solution of hydrofluoric acid, nitric acid and acetic acid, HF, HNO in the mixed liquor
3And CH
3The volume ratio of COOH is 1:3:8.The device layer 202 that the corrosion back adopts the CMP polishing to expose.
After step S130 implements to finish, can also be preferably the insulating processing be carried out on the surface of the device layer 202 that exposes, the generation silicon dioxide layer can carry out the CMP polishing to this layer, subsequently to reduce its roughness.
Shown in the accompanying drawing 2G; Refer step S140 forms a plurality of perforations in device layer 202, this embodiment is with perforation 251 and 252 expressions; Said perforation 251 is corresponding with the position of the pad (not shown) of semiconductor device with 252 position, and exposes the pad of semiconductor device.Form perforation 251 and can adopt dry method or wet etching with 252 technology because the material of pad metal normally, so can be at the pad place realization oneself stop.
Shown in the accompanying drawing 2H, refer step S150 adopts conductive filler to fill and lead up said perforation 251 and 252.Said conductive filler is a metal, is preferably copper, and forming technology for example can be to electroplate.Can use CMP polishing planarization after the plating.
Form the packaging body of accompanying drawing 2H after above-mentioned steps finishes, comprised the insulating barrier 240 on support substrates 220, support substrates 220 surfaces and the device layer 202 on insulating barrier 240 surfaces successively, comprised at least one semiconductor device in the said device layer 202.Have a plurality of perforations in the said device layer 202; This embodiment is with perforation 251 and 252 expressions; Said perforation 251 is corresponding with the position of the pad of semiconductor device with 252 position, and exposes the pad of semiconductor device, is filled with conductive filler in the said perforation 251 and 252.
The above-mentioned step is the step of individual layer encapsulation, can be used for the encapsulation of devices such as cmos sensor.With the substrate among the accompanying drawing 2H up stack successively, repeat above processing step, can realize the stacked package of multilayer.
The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; Can also make some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.
Claims (12)
1. a three-dimension packaging method is characterized in that, comprises the steps:
Semiconductor substrate and support substrates are provided, and said Semiconductor substrate comprises the heavily doped layer of supporting layer, support layer surface and the device layer on heavily doped layer surface successively, comprises at least one semiconductor device in the said device layer;
Surface in Semiconductor substrate and/or support substrates forms insulating barrier;
With said insulating barrier is the intermediate layer, and said Semiconductor substrate and support substrates are fit together;
Adopt etch stop technology to remove supporting layer and heavily doped layer in the said Semiconductor substrate;
In device layer, form a plurality of perforations, the position of said perforation is corresponding with the position of the pad of semiconductor device, and exposes the pad of semiconductor device; Adopt conductive filler to fill and lead up said perforation.
2. three-dimension packaging method according to claim 1 is characterized in that, said Semiconductor substrate adopts following steps to form:
Semiconductor substrate is provided;
Doped chemical is injected in the Semiconductor substrate, forms heavily doped layer, and the while goes out device layer in the surface isolation of Semiconductor substrate;
In device layer, make at least one semiconductor device.
3. three-dimension packaging method according to claim 1 and 2 is characterized in that, the material of said Semiconductor substrate is a monocrystalline silicon, and the doped chemical in the said heavily doped layer is a boron.
4. three-dimension packaging method according to claim 1 is characterized in that the material of said insulating barrier is selected from any one in silica, silicon nitride and the silicon oxynitride.
5. three-dimension packaging method according to claim 1 is characterized in that, said conductive filler is a metal.
6. three-dimension packaging method according to claim 1 is characterized in that the material of said support substrates is selected from any one in monocrystalline silicon, sapphire, carborundum and the glass.
7. three-dimension packaging method according to claim 1 is characterized in that, preparation in advance has complete integrated circuit structure or single tube in the said support substrates.
8. packaging body that adopts the said method of claim 1 to form; It is characterized in that, comprise support substrates, the insulating barrier on support substrates surface and the device layer of surface of insulating layer successively, comprise at least one semiconductor device in the said device layer; Have a plurality of perforations in the said device layer; The position of said perforation is corresponding with the position of the pad of semiconductor device, and exposes the pad of semiconductor device, is filled with conductive filler in the said perforation.
9. packaging body according to claim 8 is characterized in that the material of said insulating barrier is selected from any one in silica, silicon nitride and the silicon oxynitride.
10. packaging body according to claim 8 is characterized in that, said conductive filler is a metal.
11. packaging body according to claim 8 is characterized in that, the material of said Semiconductor substrate is a monocrystalline silicon, and the material of said support substrates is selected from any one in monocrystalline silicon, sapphire, carborundum and the glass.
12. packaging body according to claim 8 is characterized in that, preparation in advance has complete integrated circuit structure or single tube in the said support substrates.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104835714A (en) * | 2014-02-10 | 2015-08-12 | 北大方正集团有限公司 | Metal layer forming method based on bottoms of grooves |
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| CN101471347A (en) * | 2007-12-26 | 2009-07-01 | 上海新傲科技有限公司 | Semiconductor substrate, method for preparing the same and three-dimensional encapsulation method |
| JP2011100935A (en) * | 2009-11-09 | 2011-05-19 | Nitto Denko Corp | Laminated body, and application and manufacturing method of the same |
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| WO2009017073A1 (en) * | 2007-07-27 | 2009-02-05 | Ube Industries, Ltd. | Polyimide film and wiring board |
| CN101471347A (en) * | 2007-12-26 | 2009-07-01 | 上海新傲科技有限公司 | Semiconductor substrate, method for preparing the same and three-dimensional encapsulation method |
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| JP2011100935A (en) * | 2009-11-09 | 2011-05-19 | Nitto Denko Corp | Laminated body, and application and manufacturing method of the same |
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Application publication date: 20120801 |