CN102623291A - A data acquisition parallel storage device and method - Google Patents

Abstract

The invention discloses a data acquisition parallel storage device and a method to ensure effective storage of data. The device includes a connected clock generation module, a data buffer module and a data storage module; the data buffer module includes first to fourth first-in-first-out buffers with the same frequency and different phase write clock signals, the first to fourth The first-in-first-out buffers are respectively connected with the clock generation module, and the first to fourth first-in first-out buffers are also respectively connected with the data storage module; the data storage module is used to use the 4-way data signals of the data buffer module in the order of sampling signals Spliced into a signal.

Description

A data acquisition parallel storage device and method

technical field

The invention relates to a time-of-flight mass spectrometer detection technology, in particular to a high-speed data acquisition parallel storage device and method in a time-of-flight mass spectrometer.

Background technique

Time-of-flight mass spectrometer (TOFMS) determines the mass-to-charge ratio of different ions based on their flight time in vacuum. The analysis speed is fast and it can detect a single charge. In practical applications, the measurement of time-of-flight mass spectrometry not only depends on the time-of-flight of the ion beam emitted by the ion pulse generator, but also depends on the accumulation of many ion pulse signals. Each time the ion pulser is triggered as a transient, the data acquisition system of the time-of-flight mass spectrometer records a set of spectral lines per transient. The spectral lines recorded each time are superimposed to the expected number to obtain a complete spectrum. We use ADC (analog-to-digital converter, analog-to-digital converter) to record the amplified ion detector output signal at a fixed time interval, and store the continuous conversion results in the memory, and finally the computer uses PCI or USB reads its data and displays it in real time with spectrogram. Since the ADC analog input bandwidth of the time-of-flight mass spectrometer is only 10M, its measurement range is very limited; in addition, the sampling accuracy is relatively low.

Contents of the invention

The primary purpose of the present invention is to provide a parallel storage device for data collection in order to solve the technical problems of low sampling accuracy and inaccurate collection information in the prior art, so as to ensure effective storage of data.

Another object of the present invention is to provide a data acquisition parallel storage method.

The primary purpose of the present invention is achieved through the following technical solutions: the data acquisition parallel storage device includes a connected clock generation module, a data buffer module and a data storage module; the data buffer module includes a write clock signal with the same frequency and different phases The first FIFO buffer, the second FIFO buffer, the third FIFO buffer and the fourth FIFO buffer, the first FIFO buffer, the second FIFO buffer, the The three FIFO buffers and the fourth FIFO buffer are respectively connected with the clock generation module, the first FIFO buffer, the second FIFO buffer, the third FIFO buffer and the fourth FIFO buffer The devices are also respectively connected to the data storage modules; the data storage modules are used to splice the 4-way data signals of the data buffer module into one-way signal according to the sequence of sampling signals.

The data storage module adopts on-chip memory data storage RAM.

Another object of the present invention is achieved through the following technical solutions: the data acquisition parallel storage method based on the above-mentioned data acquisition parallel storage device includes the following steps:

S1. The sample is ionized by the ion source to form charged ions;

S2. Charged ions are introduced into the electrodes through pulses to obtain kinetic energy;

S3. The ions that have gained kinetic energy in step S2 enter the electrostatic lens to be focused;

S4. The ions focused in step S3 continue to enter the delay electrode to be accelerated and reflected to the ion detector;

S5. The ion detector multiplies the ions and outputs the signal to the data acquisition system;

S6. The analog signal forms a differential signal through an analog conditioning circuit, and the differential signal is converted from an analog signal to a digital signal through an ADC sampling chip, stored in a data acquisition parallel storage device, and read out by a computer after being processed by a data processing circuit;

Step S6 specifically includes the following steps:

S61. The analog signal conditioning circuit performs impedance matching on the input transmission line, adjusts the amplitude of the analog signal to meet the full range of the ADC sampling chip, and converts the single-ended signal into a differential signal;

S62, the differential signal enters the ADC sampling chip, and converts the analog signal into a digital signal;

S63. The digital signal enters the data acquisition parallel storage device, and the data acquisition parallel storage device realizes buffering and cross output of the data stream output by the ADC sampling chip;

S64. The buffered data stream is read out and analyzed in time domain and frequency domain;

S65. Finally, the computer reads out the analyzed data and performs filtering processing.

The working principle of the present invention is: the data acquisition system fully utilizes the advantages of FPGA in parallel processing and sequential logic design, and utilizes the ping-pong operation mode to achieve the effect of processing high-speed data flow with low-speed modules. The data acquisition module includes two parts of data buffering and data storage. Compared with the prior art, the present invention has the following advantages and effects:

(1) The analog input bandwidth is effectively improved from 10M to 300M, and the measurement range of the time-of-flight mass spectrometer is increased.

(2) The sampling accuracy of the time-of-flight mass spectrometer is improved in a large range.

(3) Due to the enhanced storage performance of the data acquisition system, the sensitivity of the time-of-flight mass spectrometer has been greatly improved.

(4) The high-speed data is effectively reduced to low-speed data, which can be received by the back-end MCU (FPGA) and processed quickly and in real time, effectively improving the accuracy of the time-of-flight mass spectrometer in detecting samples.

Description of drawings

Fig. 1 is a schematic diagram of circuit structure of the present invention;

FIG. 2 is a schematic diagram of data timing simulation.

Detailed ways

The present invention will be further described in detail below in conjunction with the embodiments and the accompanying drawings, but the embodiments of the present invention are not limited thereto.

Example

The time-of-flight mass spectrometer includes an ion source, an ion extraction pulse electrode, an ion extraction lens, a vertical introduction time-of-flight mass spectrometer, an ion selective repulsion electrode, and an MCP (Microchannel Plate) ion detector. After the sample passes through the time-of-flight mass spectrometer, the separated signal enters the high-speed data acquisition system, is stored by the parallel storage device of the present invention, and is finally read by the computer after data processing. The high-speed data acquisition system includes a front-end analog conditioning circuit, an ADC sampling circuit, a parallel storage device of the present invention, a data processing circuit and a data reading circuit. The ion extraction pulse electrode enables the ions generated by the ion source to obtain kinetic energy under the action of the pair of electrodes, and the voltage amplitude applied to the pair of electrodes determines the kinetic energy of the ions; the ion extraction pulse electrode can be used for different ion source forms different. The vertical-introduction time-of-flight mass spectrometer can be a conventional vertical-introduction time-of-flight mass spectrometer; the ion-selective repeller electrode and the MCP ion detector are arranged therein. The MCP ion detector is an ion detector composed of conventional two-chip MCP.

Fig. 1 shows the circuit structure of the present invention. It can be seen from Fig. 1 that the present invention includes a connected clock generation module, a data buffer module and a data storage module.

The first to fourth first-in-first-out (FIFO) buffers with a bit width of 8 bits form a data buffer module, and they have write clock signals with the same frequency and different phases. The first to fourth FIFO buffers are respectively connected to the clock generation module and the data storage module. The function of the data buffer module is to divide the high-speed data signal into 4 low-speed data and write them into 4 FIFO buffers. First construct 4 FIFO1-FIFO4 first-in-first-out buffers, and store the output signals of the data acquisition module into the 4 first-in-first-out buffers respectively. The two data buffers corresponding to PortA are the first FIFO1 and the third FIFO3 respectively, and the two data buffers corresponding to PortB are the second FIFO2 and the fourth First in first out buffer FIFO4.

The data storage module adopts the on-chip memory data storage RAM, and its function is to splice the 4-way 8-bit data signal of the front-end data buffer module into a 32-bit signal in the order of sampling signals, and maintain its correct order.

An example of a specific application is as follows: For example, according to the specific implementation, the sampling rate of a single channel of an ADC sampling chip with 8-bit conversion precision can reach 1Gsps. After digital-to-analog conversion, a single channel outputs 1G data stream. The data stored in the four first-in-first-out buffers FIFO1-FIFO4 of the data buffer module after data acquisition is started are N, N+1, N+2, N+3... respectively. The timing control module defines that after each startup, the data is stored from the first first-in-first-out buffer FIFO1, so as to meet the requirement of sequential reading. Finally, the bits of the data are rearranged to obtain parallel data arranged in sampling order.

After the data storage module starts, at the rising edge of the read-write clock signal FIFO-Rdclk of each FIFO buffer, read 4 paths of 8-bit data from the four FIFO1-FIFO4 at the same time, and transfer all The read 4 channels of 8-bit data are spliced into one channel of 32-bit data and stored in a 32-bit wide dual-clock dual-port RAM. The write clock RAM-Wrclk of RAM and the write clock FIFO-Rclk of the first-in-first-out buffer are signals of the same frequency. Since there is a delay (tco) between the read and write clock of the FIFO buffer and the output, a clock signal that shifts the phase of the read and write clock FIFO-Rdclk of the FIFO-Rdclk backward by a certain phase is used in the design As the way of writing clock RAM-Wrclk of RAM, in order to avoid the risk of competition (use FIFO1 shown in Figure 2 as FIFO-Rdclk in the design, FIFO2 as RAM-WrcIk). When storing data, RAM uses a little-endian structure. When writing data of a word length (4 bytes), you only need to connect the output of FIFO1-4 to the first to fourth bytes of RAM respectively. As shown in Figure 1, FIFO1 is stored in the lower 8 bits of a word, while FIFO4 is stored in the upper 8 bits of the same word, so that the data sequence in RAM is the same as the collected data sequence. The data storage control module adopts an interrupt mode to control the data flow. When the data stored in the FIFO buffer reaches a threshold (the threshold can be set, the threshold of this system is 32 bytes, and the capacity of the FIFO is 64 bytes), the control module Read data from the buffer and store it in RAM. When the amount of data in the data memory RAM reaches a threshold (the RAM capacity of this system is 4K bytes. The threshold is set to 4K, and can also be set to other values smaller than the RAM capacity), the control module sends a data processing interrupt request to the CPU, and the CPU RAM is accessed directly via the bus.

Theoretically, when FIFO-Rdclk=CLK/4 (CLK is the sampling clock), the storage speed of the signal is equal to the collection speed, and the amount of data stored in the FIFO buffer remains unchanged. If FIFO-Rdclk<CLK/4, it will cause buffer overflow, otherwise, if FIFO-RdcIk>CLK/4, it will cause the buffer to frequently send empty interrupts, so the system design should be FIFO-Rdclk=CLK/4. At the same time, in order to facilitate the observation of low-frequency data, the design also implements a programmable sampling frequency. By setting the value of the FPGA clock generation module register through software, the FIFO write clock signal can be divided by 2n (0<n<8), so as to realize data Divide by 2n of samples. Figure 2 shows the clock signal when the frequency is divided by 8 and no frequency division. The principle is to reduce the frequency of data storage by reducing the write clock frequency of FIFO, so as to realize the function of changing the sampling frequency. Among them, clkin is the data output clock of the data acquisition chip, while coutA1, coutB1, coutA2, and coutB2 represent the data input clocks of FIFO1-FIFO4 respectively, and clkA and clkB are intermediate variables.

The method for storing data using the parallel storage device of the present invention comprises the following steps:

S1. The sample is ionized by the ion source to form charged ions.

S2. Charged ions are introduced into the electrodes through pulses to obtain kinetic energy.

S3. The ions that have gained kinetic energy in step S2 enter the electrostatic lens to be focused.

S4. The focused ions in step S3 continue to enter the delay electrode to be accelerated and reflected to the ion detector.

S5. The ion detector multiplies the ions and outputs signals to the high-speed data acquisition system.

S6, the analog signal forms a differential signal through the analog conditioning circuit, the differential signal is converted from the analog signal into a digital signal by the ADC sampling chip, stored in the serial-to-parallel conversion storage device of the present invention, and read by the computer through USB or PCI after being processed by the data processing circuit .

Step S6 specifically includes the following steps:

S61. The role of the analog signal conditioning circuit includes performing impedance matching on the input transmission line, adjusting the amplitude of the analog signal to meet the full range of the ADC sampling chip, and converting the single-ended signal into a differential signal. The conditioning of the analog signal is generally realized by a preamplifier or a transformer.

S62. The differential signal enters the ADC sampling chip, and converts the analog signal into a digital signal. The ADC sampling chip has a conversion precision of 8 bits, and the sampling rate of a single channel can reach 1Gsps. Parallel sampling in alternate mode can equivalently reach a sampling frequency of 2Gsps.

S63. The digital signal enters the data acquisition parallel storage device, and the data acquisition parallel storage device is implemented on the FPGA. It can reliably realize the buffering and interleaving output of the high-speed data stream output by the ADC sampling chip.

S64. The cached data can be read out by another FPGA for fast data processing. The FPGA reads and stores the data without data reorganization, and directly analyzes the array in the time domain and frequency domain.

S65. Finally, the computer reads out the analyzed data and performs filtering processing.

The above-mentioned embodiment is a preferred embodiment of the present invention, but the embodiment of the present invention is not limited by the above-mentioned embodiment, and any other changes, modifications, substitutions, combinations, Simplifications should be equivalent replacement methods, and all are included in the protection scope of the present invention.

Claims (3)

1. a data acquisition parallel memory device is characterized in that, comprises the clock generating module, data buffering module and the data memory module that are connected; Said data buffering module comprises first first-in first-out buffer, second first-in first-out buffer, the 3rd first-in first-out buffer and the 4th first-in first-out buffer that has with the out of phase write clock signal of frequency; First first-in first-out buffer, second first-in first-out buffer, the 3rd first-in first-out buffer and the 4th first-in first-out buffer respectively with the clock generating module, first first-in first-out buffer, second first-in first-out buffer, the 3rd first-in first-out buffer and the 4th first-in first-out buffer also are connected with data memory module respectively; Said data memory module is used for 4 circuit-switched data signals of data buffering module are spliced into one road signal by the order of sampled signal.

2. data acquisition parallel memory device according to claim 1 is characterized in that, said data memory module adopts on-chip memory storage RAM.

3. based on the parallel storage means of the data acquisition of the said data acquisition parallel memory device of claim 1, it is characterized in that, comprise the steps:

S1, sample carry out ionization through ion source, form charged ion;

S2, charged ion are introduced electrode through pulse, obtain kinetic energy;

S3, the ion that in step S2, obtains kinetic energy get into electrostatic lens and obtain focusing on;

S4, the ion in step S3 after the focusing continue to get into postpones electrode acquisition acceleration and reflexes to ion detector;

S5, ion detector output signal to data acquisition system after ion is doubled;

S6, analog signal form differential signal through the simulated modulation circuit, and differential signal becomes digital signal through the ADC sampling A by analog signal conversion, store through the data acquisition parallel memory device, handle the back through data processing circuit and are read by computer;

Specifically may further comprise the steps among the step S6:

S61, analog signal conditioner circuit carry out impedance matching to the transmission line of input, and the amplitude of adjustment analog signal makes it to meet the full amplitude range of ADC sampling A, and converts single-ended signal to differential signal;

S62, differential signal get into the ADC sampling A, become digital signal by analog signal conversion;

S63, digital signal get into the data acquisition parallel memory device, and the data acquisition parallel memory device is realized the buffer memory and intersection output to the data flow of ADC sampling A output;

S64, read and carried out the analysis on time domain and the frequency domain through data in buffer stream;

S65, last being read by computer are again passed through the data of analyzing, and are carried out Filtering Processing.

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