CN102610502A - MOS element manufacturing method for reducing damage caused by hot carriers injection - Google Patents
MOS element manufacturing method for reducing damage caused by hot carriers injection Download PDFInfo
- Publication number
- CN102610502A CN102610502A CN201210081226XA CN201210081226A CN102610502A CN 102610502 A CN102610502 A CN 102610502A CN 201210081226X A CN201210081226X A CN 201210081226XA CN 201210081226 A CN201210081226 A CN 201210081226A CN 102610502 A CN102610502 A CN 102610502A
- Authority
- CN
- China
- Prior art keywords
- side wall
- region
- drain
- source
- heavily doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000002347 injection Methods 0.000 title claims abstract description 11
- 239000007924 injection Substances 0.000 title claims abstract description 11
- 239000000969 carrier Substances 0.000 title abstract 4
- 238000000034 method Methods 0.000 claims abstract description 17
- 230000007935 neutral effect Effects 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 230000008569 process Effects 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 12
- 239000007943 implant Substances 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 229910052724 xenon Inorganic materials 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 10
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 230000008021 deposition Effects 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 230000005685 electric field effect Effects 0.000 description 2
- 239000003031 high energy carrier Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a MOS element manufacturing method for reducing damage caused by hot carriers injection; a photoresist layer is formed on a lateral wall deposition layer above a drain region; a method that neutral ions process ion injection to the lateral wall deposition layer above a source region is used, thus, a cross section width of an etched source lateral wall is relatively small; and the cross section width of a drain lateral wall is relatively increased. When voltage is added to grid, the strength of a longitudinal electric field generated on the drain is weakened; therefore, holes of electronic hole pairs generated by carriers collision accelerated by a transverse electric field will be injected into the grid under the action of a relatively weak longitudinal electric field; thus, grid current formed by injecting the hot carrier is reduced; and damage of hot carriers injection of semiconductors is reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of MOS device manufacture method that reduces the hot carrier implant damage.
Background technology
Hot carrier's effect is an important failure mechanism of MOS (metal-oxide semiconductor (MOS)) device, and along with dwindling day by day of MOS device size, the hot carrier injection effect of device is more and more serious.With PMOS (P-type mos) device is example, and the hole in the raceway groove is accelerated under the effect of high transverse electric field between the drain-source; Form high energy carriers, high energy carriers and silicon crystal lattice collision produce the electron hole pair of ionization; Electronics is collected by substrate, forms substrate current, the hole that most of collision produces; Flow to drain electrode, but also have the part hole, under the effect of longitudinal electric field; Be injected into and form grid current in the grid, this phenomenon is called hot carrier and injects (Hot Carrier Injection).Hot carrier can cause the fracture of silicon substrate and silicon dioxide gate oxygen interface place ability key; Produce interfacial state at silicon substrate and silicon dioxide gate oxygen interface place; Cause device performance, the degeneration like threshold voltage, mutual conductance and linear zone/saturation region electric current finally causes the MOS component failure.The MOS component failure at first occurs in drain terminal usually, and this is that after arriving drain terminal, the energy of charge carrier reaches maximum, so the hot carrier of drain terminal injection phenomenon is more serious because charge carrier passes through the electric field acceleration of whole raceway groove.Therefore, how to reduce the research focus that semiconductor device hot carrier implant damage becomes this area staff.
Shown in Figure 1A～1C, in the technology, the side wall etching technics of MOS device comprises usually:
At first; Substrate 11 is provided, and said substrate 11 comprises source region and drain region, is formed with source electrode extension area 14 in the said source region; Be formed with drain electrode extension area 15 in the said drain region; Be formed with grid structure 12 on the said substrate 11, deposition forms side wall sedimentary deposit 13 on substrate 11 and grid structure 12 subsequently, shown in Figure 1A;
Next; Adopt anisotropic dry etch process that side wall sedimentary deposit 13 is carried out etching,, above the drain region, form drain electrode side wall 13b above the source region, to form source electrode side wall 13a; Said source electrode side wall 13a and drain electrode side wall 13b are symmetrical structure, shown in Figure 1B;
Then; Shown in Fig. 1 C, carry out the source and leak heavy doping and annealing process, in substrate 11, form source electrode heavily doped region 141 and drain electrode heavily doped region 151; Can learn; The position of source electrode heavily doped region 141 and drain electrode heavily doped region 151 receives the influence of source electrode side wall 13a and drain electrode side wall 13b, that is, dopant ion determines apart from the distance of the device channel width by side wall in source electrode heavily doped region 141 and the drain electrode heavily doped region 151.
Summary of the invention
The object of the present invention is to provide a kind of MOS device manufacture method that can effectively reduce the hot carrier implant damage.
For solving the problems of the technologies described above, the present invention provides a kind of MOS device manufacture method that reduces the hot carrier implant damage, comprising: on substrate, form grid structure, said substrate comprises source region and drain region; With said grid structure is mask, in the substrate of grid structure both sides, carries out light dope, forms source electrode extension area and drain electrode extension area; On said substrate, form the side wall sedimentary deposit; On the side wall sedimentary deposit above the said drain region, form photoresist layer; Adopt neutral ion that the side wall sedimentary deposit of top, source region is carried out the ion injection; Remove said photoresist layer, said side wall sedimentary deposit is carried out etching, above said source region, to form the source electrode side wall, above said drain region, form the drain electrode side wall, the cross-sectional width of said drain electrode side wall is greater than the cross-sectional width of said source electrode side wall; Carry out the source and leak heavy doping and annealing process, form source electrode heavily doped region and drain electrode heavily doped region, said drain electrode heavily doped region and source electrode heavily doped region are unsymmetric structure, and said source electrode heavily doped region ratio drain electrode heavily doped region is more near raceway groove.
Preferable, in the described MOS device manufacture method that reduces the hot carrier implant damage, said neutral ion is germanium ion or xenon ion.
The present invention is through forming photoresist layer and adopting neutral ion that the side wall sedimentary deposit above the source region is carried out the method that ion injects on the side wall sedimentary deposit above the said drain region; Make in the side wall etching technics side wall etch rate above the source region is higher than the side wall etch rate above the drain region; The cross-sectional width of source electrode side wall is less relatively after the etching, and the cross-sectional width of drain electrode side wall increases relatively.After grid adds voltage; Longitudinal electric field strength reduction in the drain electrode generation; Therefore, the electron hole pair that the carrier impact of being quickened by transverse electric field produces, the hole can be injected in grid under more weak longitudinal electric field effect; Thereby reduced owing to hot carrier is injected the grid current that forms, reduced the damage that the semiconductor device hot carrier is injected.
Description of drawings
Figure 1A～1C is the device profile sketch map in the side wall etching technics of MOS device in the prior art;
Fig. 2 A～2F is the device profile sketch map in the MOS device manufacture method that reduces the hot carrier implant damage of the present invention's one specific embodiment.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
With reference to Fig. 2 A-Fig. 2 F, be example with the nmos device in the CMOS transistor technology please, the MOS device manufacture method that reduces the hot carrier implant damage of the present invention comprises:
At first; Shown in Fig. 2 A; On substrate 21, form grid structure 22, said substrate 21 comprises source region and drain region, and said source region is meant the follow-up zone that will form source electrode extension area and source electrode heavily doped region; In like manner, said drain region is meant the follow-up zone that will form drain electrode extension area and drain electrode heavily doped region;
Then, shown in Fig. 2 B, be mask with grid structure 22, in the substrate 21 of grid structure 22 both sides, carry out light dope, form source electrode extension area 23 and drain electrode extension area 24;
Subsequently; Shown in Fig. 2 C; On above-mentioned substrate 21 and grid structure 22, form side wall sedimentary deposit 25; Said side wall sedimentary deposit 25 comprises side wall sedimentary deposit 251 that covers the top, source region and the side wall sedimentary deposit 252 that covers the top, drain region, and wherein, side wall sedimentary deposit material is silica or silicon nitride;
Then; Please with reference to Fig. 2 D; On the side wall sedimentary deposit 252 above the drain region, cover photoresist layer 26, and adopt neutral ion that the side wall sedimentary deposit 251 of top, source region is carried out the ion injection, wherein said neutral ion can be germanium, xenon plasma; The embodiment of the invention adopts germanium ion that the side wall sedimentary deposit 251 of source electrode top is carried out the ion injection, can increase the etch rate of the side wall sedimentary deposit 251 of top, source region with respect to the side wall sedimentary deposit 252 of top, drain region;
Then, please with reference to Fig. 2 E, remove the top, drain region photoresist 26, side wall sedimentary deposit 25 is carried out the side wall etching.Because the etch rate of the side wall sedimentary deposit 251 of top, source region will be higher than the etch rate of the side wall sedimentary deposit 252 of top, drain region; Suitably regulate the side wall etching menu (recipe) of etching machine bench, the side wall after the final etching can reduce at the width of source electrode; Can increase in drain electrode; Promptly drain the width of side wall 252A greater than the width of source electrode side wall 251A, and those skilled in the art can be known concrete etching menu through the limited number of time experiment, repeat no more at this;
At last; Please, above-mentioned device is carried out the source leak heavy doping and annealing steps, leak in heavy doping and the annealing process in the source with reference to Fig. 2 F; Because the distance of dopant ion and device channel is determined by the width of side wall; Therefore after mixing, the dopant ion of source electrode heavily doped region and the distance of device channel are furthered, and the dopant ion of drain electrode heavily doped region and the distance of device channel are zoomed out.Make the overlapping region area between drain electrode heavily doped region and the grid structure reduce; After grid adds voltage, at the longitudinal electric field strength reduction of drain electrode generation, therefore; The electron hole pair that the carrier impact that has longitudinal electric field to quicken produces; The hole can be injected in grid under more weak longitudinal electric field effect, thereby has reduced owing to hot carrier is injected the grid current that forms, and has reduced the damage that the semiconductor device hot carrier is injected.
In addition; Because when the distance of dopant ion and the raceway groove of drain electrode heavily doped region is zoomed out; The dopant ion of source end heavily doped region and the distance of raceway groove are furthered; The distance that leak between the heavy doping ion in total source remains unchanged, so the length of effective channel of device (Effective Channel Length) remains unchanged basically, and other performances of device are able to keep.
The above is merely preferred embodiment of the present invention, and all equalizations of being done according to claim example of the present invention change and modify, and all should belong to claim covering scope of the present invention.
Claims (2)
1. a MOS device manufacture method that reduces the hot carrier implant damage is characterized in that, comprising:
On substrate, form grid structure, said substrate comprises source region and drain region;
With said grid structure is mask, in the substrate of grid structure both sides, carries out light dope, forms source electrode extension area and drain electrode extension area;
On said substrate, form the side wall sedimentary deposit;
On the side wall sedimentary deposit above the said drain region, form photoresist layer;
Adopt neutral ion that the side wall sedimentary deposit of top, source region is carried out the ion injection;
Remove said photoresist layer, said side wall sedimentary deposit is carried out etching, above said source region, to form the source electrode side wall, above said drain region, form the drain electrode side wall, the cross-sectional width of said drain electrode side wall is greater than the cross-sectional width of said source electrode side wall;
Carry out the source and leak heavy doping and annealing process, form source electrode heavily doped region and drain electrode heavily doped region, said drain electrode heavily doped region and source electrode heavily doped region are unsymmetric structure, and said source electrode heavily doped region ratio drain electrode heavily doped region is more near raceway groove.
2. the MOS device manufacture method that reduces the hot carrier implant damage as claimed in claim 1 is characterized in that said neutral ion is germanium ion or xenon ion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210081226XA CN102610502A (en) | 2012-03-23 | 2012-03-23 | MOS element manufacturing method for reducing damage caused by hot carriers injection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210081226XA CN102610502A (en) | 2012-03-23 | 2012-03-23 | MOS element manufacturing method for reducing damage caused by hot carriers injection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102610502A true CN102610502A (en) | 2012-07-25 |
Family
ID=46527794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210081226XA Pending CN102610502A (en) | 2012-03-23 | 2012-03-23 | MOS element manufacturing method for reducing damage caused by hot carriers injection |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102610502A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157557A (en) * | 2014-08-15 | 2014-11-19 | 上海华力微电子有限公司 | Ion implantation method for improving hot carrier implantation loss |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060281273A1 (en) * | 2005-06-09 | 2006-12-14 | Seiko Epson Corporation | Semiconductor device and manufacturing method of the semiconductor device |
| CN101647108A (en) * | 2005-10-07 | 2010-02-10 | 国际商业机器公司 | Structure and method for forming asymmetrical overlap capacitance in field effect transistors |
| CN101673687A (en) * | 2009-09-22 | 2010-03-17 | 上海宏力半导体制造有限公司 | Manufacturing method for field effect transistor |
| CN101800179A (en) * | 2010-02-05 | 2010-08-11 | 上海宏力半导体制造有限公司 | Preparation method of asymmetrical MOSFET |
-
2012
- 2012-03-23 CN CN201210081226XA patent/CN102610502A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060281273A1 (en) * | 2005-06-09 | 2006-12-14 | Seiko Epson Corporation | Semiconductor device and manufacturing method of the semiconductor device |
| CN101647108A (en) * | 2005-10-07 | 2010-02-10 | 国际商业机器公司 | Structure and method for forming asymmetrical overlap capacitance in field effect transistors |
| CN101673687A (en) * | 2009-09-22 | 2010-03-17 | 上海宏力半导体制造有限公司 | Manufacturing method for field effect transistor |
| CN101800179A (en) * | 2010-02-05 | 2010-08-11 | 上海宏力半导体制造有限公司 | Preparation method of asymmetrical MOSFET |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157557A (en) * | 2014-08-15 | 2014-11-19 | 上海华力微电子有限公司 | Ion implantation method for improving hot carrier implantation loss |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103178093B (en) | The structure of high-voltage junction field-effect transistor and preparation method | |
| US20140158990A1 (en) | Tunneling Field Effect Transistor (TFET) With Ultra Shallow Pockets Formed By Asymmetric Ion Implantation and Method of Making Same | |
| CN101740517A (en) | Lightly doped drain forming method and semiconductor device | |
| CN103515238B (en) | Nmos pass transistor and formation method, CMOS structure and formation method | |
| CN104037083A (en) | Manufacture method of semiconductor device | |
| CN102364663A (en) | Grid side wall etching method, metal-oxide-semiconductor (MOS) device manufacturing method and MOS device | |
| US9312378B2 (en) | Transistor device | |
| CN101894865B (en) | Impact-ionization metal oxide semiconductor transistor (I-MOS) and manufacturing method thereof | |
| CN103000501B (en) | NMOS (N-channel metal oxide semiconductor) transistor forming method | |
| CN102610526A (en) | Side wall etching method for reducing heat current carrier injection damage | |
| CN111129107B (en) | Semiconductor device and method for manufacturing the same | |
| CN104347370A (en) | Method for improving negative bias temperature stability of grid of PMOS device | |
| CN102610502A (en) | MOS element manufacturing method for reducing damage caused by hot carriers injection | |
| CN101330048A (en) | Light dope ion injection method | |
| CN101452956B (en) | High voltage PMOS device and production method | |
| CN211700293U (en) | Semiconductor device with a plurality of transistors | |
| CN102299113A (en) | Method for manufacturing metal oxide semiconductor (MOS) device in use for reducing damage to semiconductor device during hot carrier injection | |
| JP2014154862A (en) | Semiconductor device | |
| CN102468162B (en) | Production method for n-channel metal oxide semiconductor (NMOS) field effect transistor | |
| CN102437057B (en) | Method for reducing semiconductor device hot carrier injection damage | |
| CN104867974A (en) | Ldmos device and manufacturing method thereof | |
| CN110943129A (en) | Semiconductor device and method for manufacturing the same | |
| CN105023831B (en) | The manufacturing method of polysilicon resistance in CMOS technology | |
| CN102364661A (en) | Grid side wall forming method, metal-oxide-semiconductor (MOS) device manufacturing method and MOS device | |
| CN102446717A (en) | Method for reducing damage of semiconductor device caused during hot carrier injection |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120725 |