CN102570989B - Operational amplification circuit - Google Patents
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- CN102570989B CN102570989B CN201010605372.9A CN201010605372A CN102570989B CN 102570989 B CN102570989 B CN 102570989B CN 201010605372 A CN201010605372 A CN 201010605372A CN 102570989 B CN102570989 B CN 102570989B
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Abstract
A kind of operational amplifier, it is characterised in that comprising: input structure, it includes that NMOS input discharge circuit and PMOS input discharge circuit；Feedback network, it includes the NMOS feedback circuit being connected with NMOS input discharge circuit and the PMOS feedback circuit being connected with PMOS input discharge circuit, described NMOS feedback circuit and PMOS feedback circuit, in the case of being less than reference voltage Vref at input voltage Vi more than reference voltage Vref and input voltage Vi, make the electric current of transistor each depend on the size of input voltage and input pickup resistance；Export structure, the signal transmitted by input structure is amplified；And biasing networks, input structure, export structure and feedback network are powered simultaneously.The present invention arranges reference voltage and uses the operational amplifier feedback loop of high-gain, and the electric current in transistor has unipolarity, can obtain good linear transconductance, realize the voltage input dynamic range on big (from ground to supply voltage) simultaneously.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the field of integrated circuit design, in particular to an operational amplifier circuit.
[ background of the invention ]
In a semiconductor device, an operational amplifier is widely used to amplify a signal to be processed. An example of an operational amplifier is disclosed in japanese unexamined patent application publication No. h6-326529 (U.S. patent No.5,311,145). The operational amplifier includes an input stage amplifier and an output stage amplifier. The input stage amplifier converts an input signal and amplifies the input signal according to an input structure of the output stage amplifier. In addition, the input stage amplifier sets the no-load current flowing through the transistors that make up the output stage amplifier. The output stage amplifier amplifies the signal generated in the input stage amplifier and outputs the signal.
As MOS size decreases, it is desirable to reduce the supply voltage to ensure that the transistors are not damaged. However, considering that the threshold voltage of the transistor is almost kept unchanged (mainly due to the consideration of the threshold in the digital logic circuit, maintaining a proper large MOS transistor threshold is beneficial to ensuring a high noise margin), when the power supply voltage is reduced to 1.5V, even about 1V, a cascade structure is often adopted to ensure a certain gain, but the conventional cascade structure operational amplifier is difficult to operate normally. Meanwhile, the reduction of the power supply voltage leads to the reduction of the input common-mode voltage range, in order to solve the problem, a Rail-to-Rail input structure is often adopted to solve the problem that the input signal range is small, but the technical problem of the Rail-to-Rail operational amplifier is that the input transconductance of the circuit structure changes along with the change of the input signal, so that the input transconductance generates large nonlinear fluctuation. Although current regulation techniques can reduce the nonlinearity of the input transconductance with changes in the input voltage, the effect is not particularly good; meanwhile, the circuit structure is more complex, and the power consumption is higher.
In view of the above drawbacks, it is desirable to provide an improved operational amplifier circuit to solve the above drawbacks.
[ summary of the invention ]
The invention aims to provide an operational amplifier to solve the problem of larger nonlinearity caused by the change of input transconductance of a circuit structure along with the change of an input signal.
The technical scheme for realizing the purpose is as follows: an operational amplification circuit, comprising:
the NMOS input two-stage operational amplifier circuit comprises a resistor R connected with an input end Vi in series, a first electrode of a PMOS input tube and a first electrode of an NMOS input tube which are connected with the other end of the resistor R respectively, an NMOS input two-stage operational amplifier circuit connected between the resistor R and a grid electrode of the PMOS input tube, a PMOS input two-stage operational amplifier circuit connected between the resistor R and a grid electrode of the NMOS input tube, an NMOS current mirror circuit connected with a second electrode of the PMOS input tube, and a PMOS current mirror circuit connected with a second electrode of the NMOS input tube; wherein,
the NMOS input two-stage operational amplifier circuit comprises PMOS tubes MP 1-MP 4 and NMOS tubes MN 1-MN 5, a grid electrode of MN1 connected with the other end of the resistor R, a first electrode of MN1 connected with a first electrode of MN2 and a second electrode of MN3, and a second electrode of MN1 connected with a second electrode of MP1 and a grid electrode of MP 3; the gate of MN2 is connected with reference voltage Vref, the second electrode of MN2 is connected with the second electrode of MP2 and the gate of MP 4; the gate of MN3 is connected with a bias voltage Vb1, and the first electrode of MN3 is connected with the first electrodes of MN4 and MN5 and the ground; the gate of MN4 is connected to the gate of MN5, the second electrode of MN4 is connected to the gate thereof and the second electrode of MP 3; the second electrode of MN5 is connected with the second electrode of MP4 as output; the gate of MP1 is connected with the gate of MP2, and the first electrode of MP1 is connected with the first electrodes of MP2, MP3 and MP4 and the voltage Vdd; a first RC series circuit is connected between the second electrode of MN1 and the second electrode of MN4, and comprises a Miller compensation resistor Rc and a capacitor Cc connected with one end of the Miller compensation resistor Rc, the other end of the Miller compensation resistor Rc is connected with the second electrode of MN1, and the other end of the capacitor Cc is connected with the second electrode of MN 4; a second RC series circuit is connected between the second electrode of MN2 and the second electrode of MN5, and comprises a Miller compensation resistor Rc and a capacitor Cc connected with one end of the Miller compensation resistor Rc, the other end of the Miller compensation resistor Rc is connected with the second electrode of MN5, and the other end of the capacitor Cc is connected with the second electrode of MN 2;
the PMOS input two-stage operational amplifier circuit comprises a PMOS tube MP1 ' -MP 5 ' and an NMOS tube MN1 ' -MN 4 ', the grid electrode of the MP1 ' connected with the other end of the resistor R, the first electrode of the MP1 ' connected with the first electrode of the MP2 ' and the second electrode of the MP3 ', and the second electrode of the MP1 ' connected with the second electrode of the MN1 ' and the grid electrode of the MN3 '; the gate of MP2 'is connected with reference voltage Vref, and the second electrode of MP 2' is connected with the second electrode of MN2 'and the gate of MN 4'; the gate of MP3 ' is connected with bias voltage Vb1 ', and the first electrode of MP3 ' is connected with the first electrodes of MP4 ' and MP5 ' and voltage Vdd; the gate of MP4 'is connected to the gate of MP 5', and the second electrode of MP4 'is connected to the gate and the second electrode of MN 3'; the second electrode of the MP5 'is connected with the second electrode of the MN 4' as an output; the gate of MN1 'is connected with the gate of MN 2', and the first electrode of MN1 'is connected with the first electrodes of MN 2', MN3 'and MN 4' and the ground; a third RC series circuit is connected between the second electrode of MP1 ' and the second electrode of MP4 ', and comprises a Miller compensation resistor Rc ' and a capacitor Cc ' connected with one end of the Miller compensation resistor Rc ', the other end of the Miller compensation resistor Rc ' is connected with the second electrode of MP4 ', and the other end of the capacitor Cc ' is connected with the second electrode of MP1 '; a fourth RC series circuit is connected between the second electrode of MP2 'and the second electrode of MP 5', and includes a miller compensation resistor RC ', a capacitor Cc connected to one end of miller compensation resistor RC', the other end of miller compensation resistor RC 'being connected to the second electrode of MP 2', the other end of capacitor Cc 'being connected to the second electrode of MP 5';
the NMOS current mirror circuit comprises a second electrode of MN6 connected with a second electrode of the PMOS input tube, a gate of MN6 is connected with a gate of MN7, and a first electrode of MN6 is connected with a first electrode of MN7 and the ground;
the PMOS current mirror circuit comprises a second electrode of MP6 'connected with a second electrode of the NMOS input tube, a gate of MP 6' is connected with a gate of MP7 ', a first electrode of MP 6' is connected with a first electrode of MP7 'and a voltage Vdd, and a second electrode of MP 7' is connected with a second electrode of MN 7.
Optionally, a value of the miller compensation resistor Rc in the NMOS input two-stage operational amplifier circuit is greater than or equal to an inverse of a transconductance value of MP3 or MP4, and a value of the miller compensation resistor Rc ' in the PMOS input two-stage operational amplifier circuit is greater than or equal to an inverse of a transconductance value of MN3 ' or MN4 '.
Compared with the prior art, the operational amplifier has the beneficial effects that: the invention sets reference voltage and adopts a high-gain operational amplifier feedback loop, and the current in the transistor has unidirectionality, thereby obtaining good linear transconductance and realizing large voltage input dynamic range (from ground to power voltage).
[ description of the drawings ]
FIG. 1 is a schematic diagram of an operational amplifier according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a PMOS input structure with a feedback loop for an operational amplifier according to the present invention;
FIG. 3 is a diagram of an NMOS input two-stage operational amplifier circuit of the circuit of FIG. 2;
FIG. 4 is a circuit diagram of an NMOS input structure with a feedback loop for an operational amplifier according to the present invention;
fig. 5 is a PMOS input two-stage operational amplifier circuit configuration of the circuit shown in fig. 4.
[ detailed description ] embodiments
Referring to fig. 1, an operational amplifier circuit according to an embodiment of the present invention includes:
an input structure to obtain a signal and transmit the signal to an output structure;
the output structure is used for amplifying the signal transmitted by the input structure;
the feedback network extracts the signal amplified by the output structure and feeds the signal back to the input structure;
the network is biased while the input structure, the output structure and the feedback network are powered.
The operational amplifier circuit according to the above embodiment monitors an output signal of the output structure, that is, an output terminal signal of the entire operational amplifier, through the feedback network.
The operational amplification circuit adopts a low-voltage high-gain operational amplifier to clamp the potential of the input end and ensures that the input voltage value of the input end is the reference voltage Vref. The low-voltage high-gain operational amplifier is further described below by some circuit examples.
Referring to fig. 2, it is a PMOS input structure circuit with feedback loop of the operational amplifier circuit of the present invention, a resistor R connected in series with an input end Vi, a first electrode of a PMOS input tube connected to the other end of the resistor R, an NMOS input two-stage operational amplifier circuit connected between the resistor R and the gate of the PMOS input tube, and an NMOS current mirror circuit connected to a second electrode of the PMOS input tube; wherein,
the NMOS current mirror circuit comprises a second electrode of MN6 connected with a second electrode of the PMOS input tube, a gate of MN6 is connected with a gate of MN7, and a first electrode of MN6 is connected with a first electrode of MN7 and the ground.
The PMOS input tube is a PMOS transistor P1, when the voltage of the input signal is less than the reference voltage Vref, no current flows into the input end P1, and the input end P1 does not participate in the amplification of the signal; when the voltage of the input signal is larger than the reference voltage Vref, the size of the inflow current is (Vi-Vref)/R, and the stability of the equivalent transconductance of the input end P1 is ensured in the range that Vi is larger than Vref, namely the input transconductance cannot change along with the amplitude of the input signal.
Referring to fig. 3, it is a circuit structure of a low-voltage high-gain operational amplifier of an operational amplifier circuit according to the present invention, which is a two-stage operational amplifier structure for providing a higher gain. The NMOS input two-stage operational amplifier circuit comprises PMOS tubes MP 1-MP 4 and NMOS tubes MN 1-MN 5, a grid electrode of MN1 connected with the other end of the resistor R, a first electrode of MN1 connected with a first electrode of MN2 and a second electrode of MN3, and a second electrode of MN1 connected with a second electrode of MP1 and a grid electrode of MP 3; the gate of MN2 is connected with reference voltage Vref, the second electrode of MN2 is connected with the second electrode of MP2 and the gate of MP 4; the gate of MN3 is connected with a bias voltage Vb1, and the first electrode of MN3 is connected with the first electrodes of MN4 and MN5 and the ground; the gate of MN4 is connected to the gate of MN5, the second electrode of MN4 is connected to the gate thereof and the second electrode of MP 3; the second electrode of MN5 is connected with the second electrode of MP4 as output; the gate of MP1 is connected with the gate of MP2, and the first electrode of MP1 is connected with the first electrodes of MP2, MP3 and MP4 and the voltage Vdd; a first RC series circuit is connected between the second electrode of MN1 and the second electrode of MN4, and comprises a Miller compensation resistor Rc and a capacitor Cc connected with one end of the Miller compensation resistor Rc, the other end of the Miller compensation resistor Rc is connected with the second electrode of MN1, and the other end of the capacitor Cc is connected with the second electrode of MN 4; a second RC series circuit is connected between the second electrode of MN2 and the second electrode of MN5, and includes a miller compensation resistor RC and a capacitor Cc connected to one end of the miller compensation resistor RC, the other end of the miller compensation resistor RC is connected to the second electrode of MN5, and the other end of the capacitor Cc is connected to the second electrode of MN 2.
The NMOS is adopted as an input stage in the circuit structure, the PMOS is adopted as a second stage, and the RC series Miller compensation technology is adopted in the circuit structure to eliminate the influence of a right zero point on the system stability due to the consideration of the stability of the circuit. The miller compensation resistance Rc is required to be greater than or equal to the reciprocal of the transconductance value of MP3 (or MP4), so that the left zero can be introduced to increase the phase margin of the operational amplifier structure while eliminating the right zero.
In order to adapt to the continuously reduced power supply voltage and simultaneously meet the higher direct current voltage gain, a cascade structure is generally adopted in the circuit structure to meet the higher gain requirement, and meanwhile, a frequency compensation technology is adopted in the circuit structure to ensure the stability of the circuit structure. The low-voltage high-gain operational amplifier includes: PMOS tubes MP 1-MP 4 and NMOS tubes MN 1-MN 5, wherein the NMOS tubes MN1 and MN2 are used as differential tubes to receive an input signal Vi and a reference signal Vref respectively; the NMOS transistor MN3 receives a bias voltage Vb 1.
Referring to fig. 4, it is an NMOS input structure circuit with feedback loop of the operational amplifier circuit of the present invention, a resistor R connected in series with an input terminal Vi, a first electrode of an NMOS input tube connected to the other end of the resistor R, a PMOS input two-stage operational amplifier circuit connected between the resistor R and the gate of the NMOS input tube, and a PMOS current mirror circuit connected to a second electrode of the NMOS input tube; wherein,
the PMOS current mirror circuit comprises a second electrode of MP6 'connected with a second electrode of the NMOS input tube, a gate of MP 6' is connected with a gate of MP7 ', a first electrode of MP 6' is connected with a first electrode of MP7 'and a voltage Vdd, and a second electrode of MP 7' is connected with a second electrode of MN 7.
The NMOS input tube is an NMOS transistor N1, when the voltage of an input signal is smaller than the reference voltage Vref, the current flowing through the input end N1 is (Vref-Vi)/R, and the stability of the transconductance of the input end N1 is also ensured at the moment, namely the input transconductance cannot change along with the amplitude of the input signal; when the voltage amplitude of the input signal is higher than the reference voltage Vref, the current flowing through the input terminal N1 is zero, i.e., the input terminal N1 does not participate in the amplification of the signal.
Referring to fig. 5, it is a circuit structure of another low-voltage high-gain operational amplifier of the operational amplifier circuit of the present invention, which is a two-stage operational amplifier structure for providing a higher gain. The PMOS input two-stage operational amplifier circuit comprises a PMOS tube MP1 ' -MP 5 ' and an NMOS tube MN1 ' -MN 4 ', the grid electrode of the MP1 ' connected with the other end of the resistor R, the first electrode of the MP1 ' connected with the first electrode of the MP2 ' and the second electrode of the MP3 ', and the second electrode of the MP1 ' connected with the second electrode of the MN1 ' and the grid electrode of the MN3 '; the gate of MP2 'is connected with reference voltage Vref, and the second electrode of MP 2' is connected with the second electrode of MN2 'and the gate of MN 4'; the gate of MP3 ' is connected with bias voltage Vb1 ', and the first electrode of MP3 ' is connected with the first electrodes of MP4 ' and MP5 ' and voltage Vdd; the gate of MP4 'is connected to the gate of MP 5', and the second electrode of MP4 'is connected to the gate and the second electrode of MN 3'; the second electrode of the MP5 'is connected with the second electrode of the MN 4' as an output; the gate of MN1 'is connected with the gate of MN 2', and the first electrode of MN1 'is connected with the first electrodes of MN 2', MN3 'and MN 4' and the ground; a third RC series circuit is connected between the second electrode of MP1 ' and the second electrode of MP4 ', and comprises a Miller compensation resistor Rc ' and a capacitor Cc ' connected with one end of the Miller compensation resistor Rc ', the other end of the Miller compensation resistor Rc ' is connected with the second electrode of MP4 ', and the other end of the capacitor Cc ' is connected with the second electrode of MP1 '; a fourth RC series circuit is connected between the second electrode of MP2 'and the second electrode of MP 5', and includes a miller compensation resistor RC ', a capacitor Cc connected to one end of miller compensation resistor RC', the other end of miller compensation resistor RC 'being connected to the second electrode of MP 2', and the other end of capacitor Cc 'being connected to the second electrode of MP 5'.
The PMOS is adopted as an input stage in the circuit structure, the NMOS input is adopted in the subsequent second stage, and the RC series Miller compensation technology is adopted in the circuit structure to eliminate the influence of the right zero point on the system stability due to the consideration of the stability of the circuit. The miller compensation resistance Rc is required to be greater than or equal to the reciprocal of the transconductance value of MN3 '(or MN 4'), so that the right zero point can be eliminated and the left zero point can be introduced to increase the phase margin of the operational amplifier structure.
The low-voltage high-gain operational amplifier includes: the PMOS tubes MP1 'to MP 5' and the NMOS tubes MN1 'to MN 4', wherein the PMOS tubes MP1 'and MP 2' are used as differential tubes to respectively receive an input signal Vi and a reference signal Vref; the PMOS transistor MP 3' receives the bias voltage Vb 1.
It can be seen that the circuit can form complementary inputs and outputs over the entire signal variation range while maintaining the stability of the transconductance over the entire range. Namely, the output current of the operational amplifier structure is all | Vi-Vref)/R | in the whole input signal amplitude range, the obtained input transconductance is 1/R, and the stability of the input transconductance can be ensured.
In summary, the overall structure of the operational amplifier circuit of the present invention employs a reference voltage, a high gain operational amplifier and a feedback loop, and the unidirectionality of the transistor current determines the conduction state of the transistor under different input voltages and reference voltages. And in the whole input voltage range, the current is only determined by the input voltage and the series resistance of the input end, so the structure can obtain good linear transconductance and simultaneously realize large input dynamic range (from ground to power voltage).
Although the present invention has been described with reference to the preferred embodiments, it is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (2)
1. An operational amplifier, comprising:
the NMOS input two-stage operational amplifier circuit comprises a resistor R connected with an input end Vi in series, a first electrode of a PMOS input tube and a first electrode of an NMOS input tube which are connected with the other end of the resistor R respectively, an NMOS input two-stage operational amplifier circuit connected between the resistor R and a grid electrode of the PMOS input tube, a PMOS input two-stage operational amplifier circuit connected between the resistor R and a grid electrode of the NMOS input tube, an NMOS current mirror circuit connected with a second electrode of the PMOS input tube, and a PMOS current mirror circuit connected with a second electrode of the NMOS input tube; wherein,
the NMOS input two-stage operational amplifier circuit comprises PMOS tubes MP 1-MP 4 and NMOS tubes MN 1-MN 5, a grid electrode of MN1 connected with the other end of the resistor R, a first electrode of MN1 connected with a first electrode of MN2 and a second electrode of MN3, and a second electrode of MN1 connected with a second electrode of MP1 and a grid electrode of MP 3; the gate of MN2 is connected with reference voltage Vref, the second electrode of MN2 is connected with the second electrode of MP2 and the gate of MP 4; the gate of MN3 is connected with a bias voltage Vb1, and the first electrode of MN3 is connected with the first electrodes of MN4 and MN5 and the ground; the gate of MN4 is connected to the gate of MN5, the second electrode of MN4 is connected to the gate thereof and the second electrode of MP 3; the second electrode of MN5 is connected with the second electrode of MP4 as output; the gate of MP1 is connected with the gate of MP2, and the first electrode of MP1 is connected with the first electrodes of MP2, MP3 and MP4 and the voltage Vdd; a first RC series circuit is connected between the second electrode of MN1 and the second electrode of MN4, and comprises a Miller compensation resistor Rc and a capacitor Cc connected with one end of the Miller compensation resistor Rc, the other end of the Miller compensation resistor Rc is connected with the second electrode of MN1, and the other end of the capacitor Cc is connected with the second electrode of MN 4; a second RC series circuit is connected between the second electrode of MN2 and the second electrode of MN5, and comprises a Miller compensation resistor Rc and a capacitor Cc connected with one end of the Miller compensation resistor Rc, the other end of the Miller compensation resistor Rc is connected with the second electrode of MN5, and the other end of the capacitor Cc is connected with the second electrode of MN 2;
the PMOS input two-stage operational amplifier circuit comprises a PMOS tube MP1 ' -MP 5 ' and an NMOS tube MN1 ' -MN 4 ', the grid electrode of the MP1 ' connected with the other end of the resistor R, the first electrode of the MP1 ' connected with the first electrode of the MP2 ' and the second electrode of the MP3 ', and the second electrode of the MP1 ' connected with the second electrode of the MN1 ' and the grid electrode of the MN3 '; the gate of MP2 'is connected with reference voltage Vref, and the second electrode of MP 2' is connected with the second electrode of MN2 'and the gate of MN 4'; the gate of MP3 ' is connected with bias voltage Vb1 ', and the first electrode of MP3 ' is connected with the first electrodes of MP4 ' and MP5 ' and voltage Vdd; the gate of MP4 'is connected to the gate of MP 5', and the second electrode of MP4 'is connected to the gate and the second electrode of MN 3'; the second electrode of the MP5 'is connected with the second electrode of the MN 4' as an output; the gate of MN1 'is connected with the gate of MN 2', and the first electrode of MN1 'is connected with the first electrodes of MN 2', MN3 'and MN 4' and the ground; a third RC series circuit is connected between the second electrode of MP1 ' and the second electrode of MP4 ', and comprises a Miller compensation resistor Rc ' and a capacitor Cc ' connected with one end of the Miller compensation resistor Rc ', the other end of the Miller compensation resistor Rc ' is connected with the second electrode of MP4 ', and the other end of the capacitor Cc ' is connected with the second electrode of MP1 '; a fourth RC series circuit is connected between the second electrode of MP2 'and the second electrode of MP 5', and includes a miller compensation resistor RC ', a capacitor Cc connected to one end of miller compensation resistor RC', the other end of miller compensation resistor RC 'being connected to the second electrode of MP 2', the other end of capacitor Cc 'being connected to the second electrode of MP 5';
the NMOS current mirror circuit comprises a second electrode of MN6 connected with a second electrode of the PMOS input tube, a gate of MN6 is connected with a gate of MN7, and a first electrode of MN6 is connected with a first electrode of MN7 and the ground;
the PMOS current mirror circuit comprises a second electrode of MP6 'connected with a second electrode of the NMOS input tube, a gate of MP 6' is connected with a gate of MP7 ', a first electrode of MP 6' is connected with a first electrode of MP7 'and a voltage Vdd, and a second electrode of MP 7' is connected with a second electrode of MN 7.
2. The operational amplifier of claim 1, wherein the miller compensation resistance Rc in the NMOS input two-stage operational amplifier circuit is equal to or greater than the reciprocal of the transconductance value of MP3 or MP4, and the miller compensation resistance Rc ' in the PMOS input two-stage operational amplifier circuit is equal to or greater than the reciprocal of the transconductance value of MN3 ' or MN4 '.
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| CN103023440B (en) * | 2012-12-20 | 2015-10-07 | 中国科学院微电子研究所 | Circuit for improving linearity of power amplifier |
| CN105305971B (en) * | 2015-11-03 | 2019-04-26 | 深圳先进技术研究院 | A kind of low noise preamplifier circuit reducing input capacitance |
| WO2021026860A1 (en) | 2019-08-15 | 2021-02-18 | 深圳市汇顶科技股份有限公司 | Amplifier circuit, chip, and electronic apparatus |
| CN113346855B (en) * | 2021-05-12 | 2023-10-10 | 上海磐启微电子有限公司 | Large-signal linear amplifying circuit implementation method |
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| CN1751433A (en) * | 2003-02-13 | 2006-03-22 | 皇家飞利浦电子股份有限公司 | Low voltage class AB transconductor circuits |
| CN101635560A (en) * | 2009-08-26 | 2010-01-27 | 余浩 | High-speed two-stage calculation amplifier |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1751433A (en) * | 2003-02-13 | 2006-03-22 | 皇家飞利浦电子股份有限公司 | Low voltage class AB transconductor circuits |
| CN101635560A (en) * | 2009-08-26 | 2010-01-27 | 余浩 | High-speed two-stage calculation amplifier |
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