CN102569190A - Pixel structure and manufacturing method thereof - Google Patents
Pixel structure and manufacturing method thereof Download PDFInfo
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- CN102569190A CN102569190A CN2012100296586A CN201210029658A CN102569190A CN 102569190 A CN102569190 A CN 102569190A CN 2012100296586 A CN2012100296586 A CN 2012100296586A CN 201210029658 A CN201210029658 A CN 201210029658A CN 102569190 A CN102569190 A CN 102569190A
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Abstract
The invention provides a method for manufacturing a pixel structure. The method comprises the following steps of: forming a thin film transistor on a substrate, and forming an insulating layer on the substrate so as to cover the substrate and the thin film transistor; patterning the insulating layer by utilizing a semi-dimmable photomask so as to form a raised pattern, a recessed pattern connected with the raised pattern, and an opening positioned in the recessed pattern, wherein the thickness of the raised pattern is greater than that of the recessed pattern, and the opening penetrates through the recessed pattern to expose a drain of the thin film transistor; forming a light-transmitting conductive layer so as to cover the raised pattern and the recessed pattern and fill the patterns in the opening; forming a flat layer to cover the light-transmitting conductive layer; and removing part of flat layer positioned on the raised pattern, part of light-transmitting conductive layer and part of flat layer in the opening so as to form a pixel electrode pattern on the light-transmitting conductive layer. The invention also provides the pixel structure manufactured by the method.
Description
Technical field
The invention relates to a kind of image element structure and preparation method thereof, and particularly about a kind of image element structure that uses half mode light shield processing procedure and preparation method thereof.
Background technology
Social now multimedia technology is quite flourishing, is indebted to the progress of semiconductor element and display unit mostly.With regard to display, have that high image quality, space utilization efficient are good, the Thin Film Transistor-LCD of low consumpting power, advantageous characteristic such as radiationless becomes the main flow in market gradually.Generally speaking, Thin Film Transistor-LCD mainly is to be made up of thin-film transistor array base-plate, colored filter substrate and the liquid crystal layer that is sandwiched between this two substrates.
Known thin-film transistor array base-plate comprises multi-strip scanning line, many data lines and a plurality of image element structure.Say that at length each image element structure comprises thin-film transistor and pixel electrode.Thin-film transistor comprises the gate that electrically connects with scan line, be positioned at channel layer on the gate, be positioned at source electrode and drain on the channel layer.Source electrode and data line electrically connect.Drain and pixel electrode electrically connect.
In known technology, when making image element structure must be deposited on the substrate rete respectively patterning to form required element.Say that further known image element structure is patterned in order and is formed by the first metal layer, first insulating barrier, semiconductor layer, second metal level, second insulating barrier and transparency conducting layer haply.In detail, after the first metal layer is patterned, form scan line and gate.After semiconductor layer is patterned, form channel layer.After second metal level is patterned, the source electrode and the drain that form data line and cover the relative both sides of channel layer.After second metal level was patterned, second insulating barrier was formed on data line, source electrode and drain top.Afterwards, second insulating barrier is patterned to form opening.This opening runs through second insulating barrier and exposes drain of film transistor.Then, transparency conducting layer is formed on second insulating barrier.At last, patterned transparent conductive layer is to form the pixel electrode pattern, and wherein the pixel electrode pattern sees through described opening and drain of film transistor electric connection.
Because above-mentioned a plurality of retes (being the first metal layer, semiconductor layer, second metal level, second insulating barrier and transparency conducting layer) must be patterned respectively, so the making of known image element structure need be used multiple tracks light shield processing procedure.Yet each road light shield processing procedure all need expend time in and money, so under the considering of time and cost, how to reduce light shield quantity, desires most ardently one of problem of solution for present research staff in fact.
Summary of the invention
The present invention provides a kind of manufacture method of image element structure, and it has the advantage that reduces light shield quantity and reduce manufacturing cost.
The present invention provides a kind of image element structure, its low cost of manufacture.
The present invention provides a kind of manufacture method of image element structure, comprises the following steps.Substrate is provided, and on substrate, forms thin-film transistor.On substrate, form insulating barrier again, with covered substrate and thin-film transistor.Then, utilize half mode mask pattern insulating barrier, with the opening that forms raised design, the recess patterns that is connected with raised design and be arranged in recess patterns.The thickness of raised design is greater than the thickness of recess patterns.Opening runs through recess patterns and exposes drain of film transistor.Then, on substrate, form light transmission conductive layer, to cover raised design, recess patterns and to insert opening.Then, form flatness layer, to cover light transmission conductive layer.At last, remove the part flatness layer of the part flatness layer, part light transmission conductive layer and the opening that are arranged on the raised design, and make light transmission conductive layer form a pixel electrode pattern.
The present invention provides a kind of image element structure, comprises substrate, thin-film transistor, insulating barrier and pixel electrode pattern.Thin-film transistor is configured on the substrate.Insulating barrier cover film transistor.Insulating barrier comprises raised design and the recess patterns that is connected with raised design.The thickness of raised design is greater than the thickness of recess patterns.Recess patterns has opening.This opening exposes drain of film transistor.The pixel electrode pattern arrangement is on insulating barrier and insert in the opening, and electrically connects with drain of film transistor.
In one embodiment of this invention, aforesaid part flatness layer and the part light transmission conductive layer that is positioned on the raised design that remove comprises the following steps and make light transmission conductive layer form the pixel electrode method of patterning.Remove the part flatness layer that is positioned on the raised design, to expose the part light transmission conductive layer.Remove the part light transmission conductive layer that is exposed by flatness layer, and form the pixel electrode pattern.
In one embodiment of this invention, the aforesaid part flatness layer that is positioned on the raised design that removes comprises with the step that exposes the part light transmission conductive layer: flatness layer is carried out ashing (Ashing) processing procedure.
In one embodiment of this invention, aforesaid is on substrate, to form insulating barrier with comprehensive ground covered substrate and thin-film transistor forming the step of insulating barrier with covered substrate and thin-film transistor on the substrate.
In one embodiment of this invention, aforesaid insulating barrier has opposite first and second surface, and the first surface of insulating barrier contacts with thin-film transistor, and the second surface of insulating barrier is essentially the plane parallel with substrate.
In one embodiment of this invention, the material of aforesaid insulating barrier comprises organic photoresistance.
In one embodiment of this invention, aforesaidly comprise with the step that covers raised design, recess patterns and insert opening forming light transmission conductive layer on the substrate: on substrate, form light transmission conductive layer with comprehensive covering raised design, recess patterns and opening.
In one embodiment of this invention, aforesaid formation flatness layer comprises that with the step that covers light transmission conductive layer the formation flatness layer is with comprehensive covering light transmission conductive layer.
In one embodiment of this invention, aforesaid flatness layer has an opposite first and a second surface, and the first surface of flatness layer contacts with light transmission conductive layer, and the second surface of flatness layer is essentially the plane parallel with substrate.
In one embodiment of this invention, aforesaid pixel electrode pattern covers recess patterns and do not cover raised design.
In one embodiment of this invention, aforesaid pixel electrode pattern overlaps in fact with the orthographic projection of recess patterns on substrate in the orthographic projection on the substrate.
In one embodiment of this invention, the transistorized channel layer of aforesaid raised design cover film, and transistorized drain of recess patterns cover film and the transistorized channel layer of cover film not.
In one embodiment of this invention, aforesaid image element structure more comprises data line interlaced with each other and scan line, and wherein the source electrode of data line and thin-film transistor electrically connects, and the gate of scan line and thin-film transistor electrically connects.
In one embodiment of this invention, the transistorized channel layer of aforesaid raised design cover film, data line and scan line.
Based on above-mentioned, in image element structure processing procedure of the present invention, utilize half mode mask pattern insulating barrier, have the raised design and the recess patterns of high low head with formation.Utilize described raised design and recess patterns definable to go out the pixel electrode pattern, and then the required light shield quantity of making image element structure of the present invention can be reduced.Thus, the cost of manufacture of image element structure of the present invention just can reduce effectively.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and cooperates appended graphic elaborating as follows.
Description of drawings
Figure 1A to Figure 12 A looks sketch map on the making flow process of image element structure of one embodiment of the invention.
Figure 1B to Figure 12 B is respectively the hatching line A-A ' generalized section of corresponding Figure 1A to Figure 12 A.
Among the figure: 100 image element structures, 110 substrates, 120 thin-film transistors, 121 scan lines, 121a gate, 122 lock insulating barriers; 124 channel layers, 126a drain, 126b source electrode, 126c data line, 130 insulating barriers, 130a, 160a first surface; 130b, 160b second surface, 132 raised designs, 134 recess patterns, 140a, 140b, 140c pattern, 150 light transmission conductive layer; 150 ' pixel electrode pattern, 160 flatness layers, W opening, H1, H1 ', H2 thickness, A-A ' hatching line.
Embodiment
The making flow process of image element structure
Figure 1A to Figure 12 A looks sketch map on the making flow process of image element structure of one embodiment of the invention.Figure 1B to Figure 12 B is respectively the generalized section of corresponding Figure 1A to Figure 12 A along hatching line A-A '.Be noted that in Figure 1A to Figure 12 A, if the border of rete when overlapping, only indicates the rete that is positioned at the superiors with other retes in fact in the top view.Therefore, Figure 1A to Figure 12 A has omitted the sign of partial component, so please be simultaneously with reference to corresponding generalized section (being Figure 1B to Figure 12 B).Below will cooperate Figure 1A to Figure 12 A and 1B to Figure 12 B to specify the making flow process of the image element structure of one embodiment of the invention.
Please, at first, on substrate 110, form the first metal layer (not illustrating) earlier with reference to Figure 1A and Figure 1B.Then, the scan line 121 of this first metal layer of patterning to form gate 121a and to electrically connect with gate 121a.In the present embodiment, gate 121a can be the some of scan line 121.Yet the present invention is as limit, and in other embodiments, gate 121a also can be for by scan line 121 outward extending branches.In the present embodiment, scan line 121 generally is to use metal material with gate 121a.Yet, the invention is not restricted to this, according to other embodiment, scan line 121 also can use other electric conducting materials with gate 121a.For example: the nitrogen oxide of the nitride of alloy, metal material, the oxide of metal material, metal material or the stack layer of metal material and other electric conducting material.
Please, then, form lock insulating barrier 122 on substrate 110 with reference to Fig. 2 A and Fig. 2 B.In the present embodiment, lock insulating barrier 122 for example is comprehensive ground covered substrate 110, gate 121a and scan line 121.In the present embodiment, the material of lock insulating barrier 122 (for example: the stack layer of silica, silicon nitride, silicon oxynitride or above-mentioned at least two kinds of materials), organic material or above-mentioned combination can be inorganic material.
Please, then, on lock insulating barrier 122, form semiconductor layer (not illustrating) with reference to Fig. 3 A and Fig. 3 B.Then, this semiconductor layer of patterning is to form channel layer 124.Channel layer 124 is overlapping with gate 121a.The material of channel layer 124 can be the material of crystal silicon, amorphous silicon, polysilicon, oxide etc.
Please, then, form second metal level (not illustrating) to cover channel layer 124 and substrate 110 with reference to Fig. 4 A and Fig. 4 B.Then, the data line 126c of this second metal level of patterning to form source electrode 126b, drain 126a and to electrically connect with source electrode 126b.So far, thin-film transistor 120 just tentatively completes.What need explanation is, the method for above-mentioned formation thin-film transistor 120 is to be example with the method that forms end gate (bottom gate) thin-film transistor.Yet, the invention is not restricted to this, in other embodiments, thin-film transistor 120 also can be top gate (top gate) thin-film transistor or other forms of thin-film transistor.The method that forms top gate (top gate) thin-film transistor or other forms of thin-film transistor field for this reason has common knowledge and knows, in this just detailed description no longer.
Please then, form an insulating barrier 130 simultaneously with reference to Fig. 5 A and Fig. 5 B with covered substrate 110 and thin-film transistor 120.In the present embodiment, comprehensive ground covered substrate 110 and thin-film transistor 120 of insulating barrier 130.In detail; Insulating barrier 130 has a relative first surface 130a and a second surface 130b; Wherein the first surface 130a of insulating barrier 130 contacts with thin-film transistor 120, and the second surface 130b of insulating barrier 130 can be in fact the plane parallel with substrate 110.In the present embodiment, the material of insulating barrier 130 can be organic photoresistance, and this organic photoresistance can be the eurymeric photoresistance.Yet, the invention is not restricted to this, in other embodiments, organic photoresistance also can be the minus photoresistance.In addition, the thickness H1 of insulating barrier 130 for example is 2 microns to 3 microns.
Please, utilize this insulating barrier 130 of half mode light shield, 140 patternings with reference to Fig. 6 A and Fig. 6 B.In the present embodiment particularly, this half mode light shield 140 for example has pattern 140a, pattern 140b and the pattern 140c of three kinds of different printing opacity degree, and wherein the light transmittance of pattern 140b for example is between pattern 140a and pattern 140c.Say that further pattern 140a for example is complete printing opacity, pattern 140c for example is light tight, and the printing opacity degree of pattern 140b for example is in the middle of pattern 140a and the pattern 140c.
Please with reference to Fig. 7 A and Fig. 7 B; After being used in 130 exposures of 140 pairs of insulating barriers of half mode light shield; The engineering of developing is so that the opening W that insulating barrier 130 forms raised designs 132, the recess patterns 134 that is connected with raised design 132 and is arranged in recess patterns 134, and its split shed W runs through recess patterns 134 and exposes the drain 126a of thin-film transistor 120.In more detail, in the present embodiment, the pattern 140a that opening W light transmittance capable of using is the highest forms, and recess patterns 134 light transmittances capable of using time high pattern 140b forms, and the minimum pattern 140c of raised design 132 light transmittances capable of using forms.In the present embodiment, the channel layer 124 of raised design 132 cover film transistors 120, data line 126b and scan line 121.The drain 126a of recess patterns 134 cover film transistors 120 and the channel layer 124 of cover film transistor 120 not.In addition, the thickness H1 of raised design 132 is greater than the thickness H1 ' of recess patterns 134.
Please, then, on substrate 110, form light transmission conductive layer 150 to cover raised design 132, recess patterns 134 and to insert among the opening W with reference to Fig. 8 A and Fig. 8 B.In the present embodiment, light transmission conductive layer 150 for example is comprehensive covering raised design 132, recess patterns 134 and opening W.In the present embodiment; The material of light transmission conductive layer 150 can be metal oxide, for example indium tin oxide, indium-zinc oxide, aluminium tin-oxide, aluminium zinc oxide, indium germanium zinc oxide or other suitable oxide or the above-mentioned stack layer of the two at least.
Please then, on substrate 110, form a flatness layer 160, to cover light transmission conductive layer 150 simultaneously with reference to Fig. 9 A and Fig. 9 B.In the present embodiment, flatness layer 160 comprehensive covering light transmission conductive layer 150.The material of the flatness layer 160 of present embodiment for example is inorganic photoresistance, that is known technology be used for patterning the first metal layer and second metal level with the photoresistance that forms gate and source electrode, drain respectively but the present invention not as limit.In addition, flatness layer 160 for example is comprehensive covering light transmission conductive layer 150.Particularly, flatness layer 160 has an opposite first 160a and a second surface 160b.The first surface 160a of flatness layer 160 contacts with light transmission conductive layer 150, and the second surface 160b of flatness layer 160 can be and is essentially a plane parallel with substrate 110.In the present embodiment, the thickness H2 of flatness layer 160 can be between for example being 1 micron to 2.2 microns.
Please then, can carry out the removal step of above-mentioned inorganic photoresistance simultaneously with reference to Figure 10 A and Figure 10 B.In the present embodiment, the method for the inorganic photoresistance of above-mentioned removal for example is that flatness layer 160 is carried out an ashing (Ashing) processing procedure.In detail, in the present embodiment, in the electric paste etching capable of using (Plasma Etching), the method for ion bombardment (ion-bombardment) removes to remove the first half of flatness layer 160.After removing the first half of flatness layer 160, the part flatness layer 160 that is positioned on the raised design 132 is removed, and exposes part light transmission conductive layer 150.On the other hand, residual fraction flatness layer 160 still then on the recess patterns 134.
Please, then, remove the part light transmission conductive layer 150 that is exposed by flatness layer 160, and make light transmission conductive layer 150 form pixel electrode pattern 150 ' with reference to Figure 11 A and Figure 11 B.In the present embodiment, can remove part light transmission conductive layer 150 by etching mode.Above-mentioned etching mode is not limited to dry ecthing or wet etching.In addition, because this moment, the part light transmission conductive layer 150 on the raised design 132 was removed, so expose raised design 132.
Please, follow with reference to Figure 12 A and Figure 12 B, the removable flatness layer 160 that remains in the part among recess patterns 134 and the opening W, and expose pixel electrode pattern 150 '.In detail, in the present embodiment, photoresistance stripping capable of using (photo resist stripping) agent removes the part flatness layer 160 that remains among recess patterns 134 and the opening W.In this, the image element structure 100 of present embodiment just completes.
What deserves to be mentioned is, in image element structure 100 processing procedures of present embodiment, utilize half mode light shield, 140 patterned insulation layers 130, have the raised design 132 and recess patterns 134 of high low head with formation.And utilize recess patterns 134 to define pixel electrode pattern 150 ', and then the image element structure 100 required light shield quantity of making present embodiment are reduced.Thus, the cost of manufacture of the image element structure 100 of present embodiment just can reduce effectively.In addition; The above-mentioned method that defines pixel electrode pattern 150 ' with raised design 132 with high low head and recess patterns 134 also can be applicable in any structure that needs insulating barrier and pixel electrode, for example in the processing procedure of contact panel, semi-penetration semi-reflective panel, IPS panel or FFS panel.
Please with reference to Figure 12 A and Figure 12 B, the image element structure 100 of present embodiment comprises substrate 110, thin-film transistor 120, insulating barrier 130 and pixel electrode pattern 150 '.Thin-film transistor 120 is configured on the substrate 110.Thin-film transistor 120 comprises gate 121a, lock insulating barrier 122, channel layer 124, source electrode 126b and drain 126a.
Shown in Figure 12 A, the image element structure 100 of present embodiment can further comprise data line 126c and scan line 121.The source electrode 126b of data line 126c and thin-film transistor 120 electrically connects.Scan line 121 electrically connects with the gate 121a of thin-film transistor 120.
The insulating barrier 130 cover film transistors 120 of present embodiment.Say that further insulating barrier 130 comprises raised design 132 and recess patterns 134.Recess patterns 134 is connected with raised design 132.Raised design 132 has the drain 126a that exposes thin-film transistor 120.In more detail, the channel layer 124 of raised design 132 cover film transistors 120, data line 126c and scan line 121.The drain 126a of recess patterns 134 cover film transistors 120 and the channel layer 124 of cover film transistor 120 not.In addition, the thickness H1 of raised design 132 is greater than the thickness H1 ' of recess patterns 134.
The pixel electrode pattern 150 ' of present embodiment is configured on the insulating barrier 130 and inserts among the opening W, so that the drain 126a of pixel electrode pattern 150 ' and thin-film transistor 120 electrically connects.It should be noted that pixel electrode pattern 150 ' covering recess patterns 134 and do not cover raised design 132.In addition, pixel electrode pattern 150 ' overlaps in fact with the orthographic projection of recess patterns 134 on substrate 110 in the orthographic projection on the substrate 110.In the processing procedure of the image element structure 100 of present embodiment, the raised design 132 with high low head capable of using defines pixel electrode pattern 150 ' with recess patterns 134, so the image element structure 100 required light shield quantity of making present embodiment can reduce.In other words, the image element structure 100 of present embodiment has the advantage of low cost of manufacture.
In sum, in the image element structure processing procedure of one embodiment of the invention, utilize half mode mask pattern insulating barrier, have the raised design and the recess patterns of high low head with formation.Utilize described raised design and recess patterns definable to go out the pixel electrode pattern, and then the required light shield quantity of image element structure of making one embodiment of the invention can be reduced.Thus, the cost of manufacture of the image element structure of one embodiment of the invention just can reduce effectively.In addition, the image element structure made from the method also has the advantage of low cost of manufacture.
Though the present invention discloses as above with execution mode; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (16)
1. the manufacture method of an image element structure is characterized in that, comprising:
One substrate is provided;
On this substrate, form a thin-film transistor;
On this substrate, form an insulating barrier, to cover this substrate and this thin-film transistor;
Utilize half this insulating barrier of mode mask patternization; With an opening that forms a raised design, a recess patterns that is connected with this raised design and be arranged in this recess patterns; Wherein the thickness of this raised design is greater than the thickness of this recess patterns, and this opening runs through this recess patterns and exposes a drain of this thin-film transistor;
On this substrate, form a light transmission conductive layer, to cover this raised design, this recess patterns and to insert this opening;
Form a flatness layer, to cover this light transmission conductive layer; And
Remove the part flatness layer of this flatness layer of part, this light transmission conductive layer of part and this opening that are arranged on this raised design, and make this light transmission conductive layer form a pixel electrode pattern.
2. the manufacture method of image element structure according to claim 1 is characterized in that, remove this flatness layer of part and this light transmission conductive layer of part of being positioned on this raised design, and the step that makes this light transmission conductive layer form this pixel electrode pattern comprises:
Remove this flatness layer of part that is positioned on this raised design, to expose the part light transmission conductive layer; And
Remove this part light transmission conductive layer that is exposed by this flatness layer, and form this pixel electrode pattern.
3. the manufacture method of image element structure according to claim 2 is characterized in that, removes this flatness layer of part that is positioned on this raised design, comprises with the step that exposes the part light transmission conductive layer: this flatness layer is carried out an ashing processing procedure.
4. the manufacture method of image element structure according to claim 1 is characterized in that: on this substrate, form this insulating barrier and comprise with the step that covers this substrate and this thin-film transistor:
On this substrate, form this insulating barrier to cover this substrate and this thin-film transistor comprehensively.
5. the manufacture method of image element structure according to claim 1; It is characterized in that: this insulating barrier has a relative first surface and a second surface; This first surface of this insulating barrier contacts with this thin-film transistor, and this second surface of this insulating barrier is essentially a plane parallel with this substrate.
6. the manufacture method of image element structure according to claim 1 is characterized in that, the material of this insulating barrier comprises: an organic photoresistance.
7. the manufacture method of image element structure according to claim 1 is characterized in that: this raised design covers a channel layer of this thin-film transistor, and this recess patterns covers a drain of this thin-film transistor and do not cover this channel layer of this thin-film transistor.
8. the manufacture method of image element structure according to claim 1 is characterized in that: on this substrate, form this light transmission conductive layer and comprise with the step that covers this raised design, this recess patterns and insert this opening:
On this substrate, form this light transmission conductive layer with this raised design of comprehensive covering, this recess patterns and this opening.
9. the manufacture method of image element structure according to claim 1 is characterized in that: form this flatness layer and comprise with the step that covers this light transmission conductive layer:
Form this flatness layer with this light transmission conductive layer of comprehensive covering.
10. the manufacture method of image element structure according to claim 9; It is characterized in that: this flatness layer has an opposite first and a second surface; This first surface of this flatness layer contacts with this light transmission conductive layer, and this second surface of this flatness layer is essentially a plane parallel with this substrate.
11. an image element structure is characterized in that, comprising:
One substrate;
One thin-film transistor is configured on this substrate;
One insulating barrier covers this thin-film transistor, and this insulating barrier comprises:
One raised design; And
One recess patterns is connected with this raised design, and wherein the thickness of this raised design is greater than the thickness of this recess patterns, and this recess patterns has an opening, and this opening exposes a drain of this thin-film transistor; And
One pixel electrode pattern is configured on this insulating barrier and inserts in this opening, and electrically connects with this drain of this thin-film transistor.
12. image element structure according to claim 11 is characterized in that: this this recess patterns of pixel electrode pattern covers and do not cover this raised design.
13. image element structure according to claim 11 is characterized in that: this pixel electrode pattern overlaps in fact with the orthographic projection of this recess patterns on this substrate in the orthographic projection on this substrate.
14. image element structure according to claim 11 is characterized in that: this raised design covers a channel layer of this thin-film transistor, and this recess patterns covers a drain of this thin-film transistor and do not cover this channel layer of this thin-film transistor.
15. image element structure according to claim 11; It is characterized in that; More comprise: a data line interlaced with each other and one scan line, wherein the one source pole of this data line and this thin-film transistor electrically connects, and a gate of this scan line and this thin-film transistor electrically connects.
16. image element structure according to claim 15 is characterized in that: this this raised design covers a channel layer, this data line and this scan line of this thin-film transistor.
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| US10228787B2 (en) | 2015-06-05 | 2019-03-12 | Innolux Corporation | Display device |
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