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CN102567560A - Method and system for estimating service life of MOS (Metal Oxide Semiconductor) device - Google Patents

Method and system for estimating service life of MOS (Metal Oxide Semiconductor) device Download PDF

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CN102567560A
CN102567560A CN2010106217945A CN201010621794A CN102567560A CN 102567560 A CN102567560 A CN 102567560A CN 2010106217945 A CN2010106217945 A CN 2010106217945A CN 201010621794 A CN201010621794 A CN 201010621794A CN 102567560 A CN102567560 A CN 102567560A
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mrow
degradation
msub
failure
service life
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王群勇
阳辉
钟征宇
陈冬梅
白桦
刘燕芳
吴文章
陈宇
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BEIJING SAN-TALKING TESTING ENGINEERING ACADEMY Co Ltd
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BEIJING SAN-TALKING TESTING ENGINEERING ACADEMY Co Ltd
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Abstract

The invention discloses a method for estimating service life of an MOS (Metal Oxide Semiconductor) device. The method comprises the steps of: analyzing the relevance of a physical failure mechanism and a device macroparameter degradation, constructing a device macroparameter degradation model based on the physical failure mechanism; carrying out reliability analog simulation on a device, analyzing the sensitivity of the device macroparameter degradation to the physical failure mechanism; selecting a stress applying mode, carrying out a parameter degradation service life-based test on the device and obtaining reliability test data; analyzing the reliability test data, establishing a parameter degradation-based service life estimating computing model; and obtaining a service life estimating result of the device according to the service life estimating computing model. By using the method, the problems of accuracy and maneuverability of the traditional device service life predicting method under the novel technical conditions are solved, the quantity of test samples is reduced, the testing cost is lowered, and the accuracy of predicting the testing result is improved.

Description

Method and system for predicting service life of MOS (Metal oxide semiconductor) device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method and a system for predicting the service life of an MOS (Metal oxide semiconductor) device.
Background
The high-reliability and long-life integrated circuit in China also faces the challenges in the aspects of reliability and test while the leap-type progress of design and production is realized following the development of the international semiconductor technology. The adaptability and stability of the high-reliability and long-life MOS device under different environments, particularly the adaptability between the high-reliability and long-life MOS device and the high-reliability and long-life MOS device have strict requirements, so that the high-reliability and long-life MOS device has higher requirements on quality and reliability.
On the other hand, with the progress of the technology, the failure rate of the MOS device, particularly a large-scale digital integrated circuit, is remarkably reduced compared with the past, the device hardly fails in the traditional life assessment method based on time-failure, and the research and development unit is difficult to obtain the reliability information of the device through tests, so that the technical attack of the MOS device with long service life is restricted.
The performance index, environmental adaptability and reliability requirements of the future high-reliability and long-life MOS device are greatly improved, the traditional technologies such as a life test, an aging screening test and the like cannot meet the requirements, a test evaluation method matched with the development of the MOS device needs to be researched, and the problem of the long-life reliability test evaluation method is solved.
MOS device failure mechanisms, which typically include Electromigration (EM), Hot Carrier Injection (HCI), gate oxide time dependent breakdown (TDDB), Negative Bias Temperature Instability (NBTI), and the like, dominate the lifetime and reliability of the MOS device. The shrinking device dimensions and the use of new materials have also created a need for the study and analysis of device failure mechanisms and failure modes. Reliability problems of MOS devices include HCI, NBTI, EM, TDDB, etc., requiring complete testing, evaluation, and method modifications to these new reliability problems, as well as failure mechanisms and failure modes.
Under the application of a new process and a new material, such as Cu interconnection, high-k and low-k materials, SOI and the like, technical support is provided for the reliability evaluation and long-life prediction of MOS devices, and the accuracy of long-life tests and reliability evaluation results is improved. For example, the use of high-k materials in the process helps to solve the leakage problem of ultra-thin gate dielectric layers, but the use of high-k materials is prone to new reliability problems, such as the NBTI effect is often accelerated to deteriorate and the threshold voltage and flat band voltage (flat band) deviation phenomenon is caused when a fixed charge density is formed at the polysilicon/high-k dielectric interface. As another example, in order to reduce the parasitic RC delay associated with metal interconnects, the conventional aluminum interconnect technology line is shifted to copper interconnects, and although the sheet resistivity of Cu-based metal interconnects may reach half of that of Al-based metal systems, Cu interconnects require new process steps and present some new reliability risks associated therewith, such as problems of metal shorts caused by silicon nitride peeling due to stress transfer in copper damascene processes.
Therefore, for the MOS device, a set of service life prediction method based on failure mechanism parameter degradation is urgently needed, and support is provided for the development and the examination of the MOS device with high reliability and long service life.
Disclosure of Invention
The invention aims to provide a method for predicting the service life of a MOS device based on failure mechanism parameter degradation.
To achieve the above object, there is provided a method for predicting a lifetime of a MOS device according to an embodiment of the present invention, including the steps of:
s1, analyzing the correlation between the physical failure mechanism of the device and the macroscopic parameter degradation of the device, and constructing a macroscopic parameter degradation model of the device based on the physical failure mechanism;
s2, performing reliability simulation on the device, and analyzing the sensitivity of macroscopic parameter degradation of the device to a physical failure mechanism;
s3, selecting a stress applying mode, performing parameter-based degradation life test on the device and acquiring reliability test data;
s4, analyzing the reliability test data, and establishing a life prediction calculation model based on parameter degradation;
and S5, obtaining the life prediction result of the device according to the life prediction calculation model.
Preferably, the physical failure mechanism in step S1 includes hot carrier injection, time-dependent dielectric breakdown, negative bias instability and/or electromigration.
Preferably, the reliability test data in step S3 includes data of the variation of the sensitive parameters of the device with time and hard failure data of the device.
Preferably, in step S3, the stress application manner is determined by using an arrhenius model, an E model, an allin model, or a combination thereof.
Preferably, the step S4 includes: the distribution of the various single failure modes of the device and the correlation between the various single failure modes are analyzed.
The invention finally forms a life prediction method of parameter degradation based on the failure mechanism by analyzing the failure mechanism and the failure mode of the MOS device. The method solves the problems of accuracy and operability of the traditional device life prediction method under the new technical condition, reduces the number of test samples, reduces the test cost, improves the accuracy of the predicted test result, provides theoretical basis for the test result, helps research personnel and designers to effectively improve the service life of the device aiming at the failure mechanism of the MOS device, reduces the test period and accelerates the product to be on the market.
Drawings
FIG. 1 is a method flow diagram of a method of predicting MOS device lifetime in accordance with an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating the effect of transistor degradation on the circuit of a MOS device lifetime prediction method according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of reliability simulation by using a reliability simulation analysis tool in the method for predicting the lifetime of a MOS device according to the embodiment of the present invention;
FIG. 4 is a graph of time degradation of a MOS device failure in a prior art method of predicting a lifetime of a MOS device;
fig. 5 is a graph of accelerated test versus concave degradation at different temperatures in a method for predicting lifetime of a MOS device according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
The embodiment of the invention aims at the main MOS device physical failure mechanism: HCI, TDDB, EM, NBTI and the like, analyzing the MOS device failure mechanism and the relevance of device parameter degradation, and sorting out a MOS device macroscopic parameter degradation model based on physical failure; the technical experience and advanced software and hardware technical equipment in the field of integrated circuit testing and experiment are utilized to design a high-precision and high-stability testing and testing platform, the testing and testing platform is combined with a high-reliability and long-life integrated circuit design unit to select and process a proper MOS device and structure, design and implement a test, and a test stress application method and parameter degradation sensitivity are analyzed to form an effective parameter degradation life testing method; selecting a proper sample and a proper test scheme, and collecting data through designing a series of verification tests; the latest international data mining and exploratory data analysis technology, the technology of analysis degradation data pattern recognition, data fitting and extrapolation technology and the like are adopted to establish a parameter degradation life prediction method based on a failure mechanism for an MOS device. As shown in fig. 1, the detailed steps of the method of the present invention are as follows:
the method comprises the following steps: analysis of MOS device failure mechanism
The method mainly analyzes the physical failure mechanism of the MOS device: HCI, TDDB, EM, NBTI and the like, analyzes the correlation between the MOS device failure mechanism and the device parameter degradation, and constructs an MOS device macroscopic parameter degradation model based on the physical failure mechanism.
Step two: establishing the relationship between performance degradation sensitive parameters and device failure
Taking the HCI model of MaCRO as an example, in MaCRO, the enhancement value Delta R of series resistance is caused by hot carriersdTo reflect the effect of HCI-induced transistor degradation on the circuit, as shown in fig. 2.
Hot carriers injected into the gate oxide layer can cause the generation of interface states and oxide layer charges, which in turn leads to variations in channel mobility, threshold voltage, transconductance and saturation leakage current. These effects are determined by Δ R, which is determined by the following formuladThe values are as follows:
<math> <mrow> <msub> <mi>&Delta;R</mi> <mi>d</mi> </msub> <mo>=</mo> <mfrac> <mrow> <mn>1</mn> <mo>+</mo> <mi>&alpha;&Delta;N</mi> </mrow> <msub> <mi>I</mi> <mrow> <mi>ds</mi> <mn>0</mn> </mrow> </msub> </mfrac> <msub> <mi>V</mi> <mi>Rd</mi> </msub> </mrow> </math>
in the above formula,. DELTA.RdThe drain end series resistance variation of the MOS transistor caused by the hot carrier effect; vRdIs Δ RdA pressure drop across; Δ N is the sum of the interface state areal density and the oxide layer charge areal density due to the hot carrier effect; α is a process-related constant; i isds0Is the drain current before the degradation of the hot carrier effect of the MOS transistor.
Therefore, the influence of the HCI on the whole circuit can be adjusted by artificially changing the value of the model parameter, so that the sensitive parameter set can be determined more conveniently and accurately. Similar methods can also be used to help determine the set of sensitivity parameters for the effects of TDDB, NBTI, and EM, thus creating a mapping between physical failure degradation and device parameters.
For different types of MOS devices, finding out macroscopic parameters which are directly related to device failure and can be directly measured at a device level to form a macroscopic parameter set. The reliability simulation analysis tool of the existing MOS integrated circuit is utilized to carry out reliability simulation on the MOS circuit and find device-level sensitive parameters related to a physical failure mechanism. Detailed flow is as shown in the attached figure 3 of the specification, firstly, the most sensitive module related to failure is proposed, the most sensitive module is described in a network level mode to reflect failure characteristics more accurately, and for insensitive modules, the most sensitive module is described in a behavior level mode; then, circuit behavior simulation is carried out, direct current analysis, alternating current analysis, transient analysis and other analysis are carried out, working points of circuit direct current, power (I, V, f, T, P and the like) and the like are determined, and electric and thermal stress environments where each module of each transistor is located are determined; and finally, extracting parameters of the failure model by using the actually measured degradation test data, and substituting the parameters into the degradation model to simulate the failure rate.
In the step, because only the sensitivity of the device-level parameters to the microscopic failure mechanism needs to be qualitatively analyzed, model parameters in a transistor degradation model do not need to be extracted very accurately; and the influence of different failure mechanisms (HCI, TDDB, NBTI and EM) on the whole circuit can be artificially amplified or reduced by adjusting the values of relevant model parameters in the transistor degradation model, and the sensitivity of each parameter in the sensitive parameters to different microscopic failure mechanisms can be determined by using the method.
Step three: determination of test stress selection technique
The device under test is under test conditions, and the change data of the sensitive parameters of the device along with time is detected and collected by continuously applying stress to the tested device. The conditions of the test stress are different, and the degradation condition of the device is also different. For example, generally, the higher the test temperature, the faster the degradation rate of the device. The degradation of the device can also be accelerated by increasing the input of the voltage, current and frequency of the tested device. For complex digital devices, the application of experimental electrical stress is important to study so that as many cells as possible are electrically stressed. There are various methods for selecting the test stress for accelerated degradation testing. For example, the arrhenius model is commonly used for this, assuming that the failure mechanism is due to thermal activation. For the case where there is a single failure mechanism, the usual method is to plot ln (failure rate) against the inverse 1/T of temperature on a graph to give a straight line (or an exponential regression fit may be used); for the case where the failure mechanism is triggered by electrical stimulation, such as TDDB, a common model is the "E-model". If ln (failure rate) is proportional to the electric field gradient (Δ V/tox). Plotting ln (failure rate) and (Δ V/tox) will result in a line (or using an exponential regression fit); it is assumed that the failure is caused by two different stresses. For example, TDDB is sensitive to temperature and voltage. The key to the design strategy is that assuming the allin model is fully functional (separable stress), a two-dimensional coordinate "space" can be constructed (temperature is one axis and voltage is another axis), and the constrained region in the space is detected by using factor design to determine the stress condition.
Step four: determination of life prediction model of MOS device
Multiple failure modes may result in MOS device failure, which are governed by different physical failure mechanisms. In the actual degradation life test data, a large amount of information about the reliability of the device is included, for example, degradation data of a plurality of sensitive parameters of the device and data of hard failure of the device during degradation. The MOS device service life prediction model is to comprehensively analyze the reliability test data, establish a service life prediction calculation model based on parameter degradation and obtain a service life prediction result of the device.
From the existing outcome analysis, most failures can trace back a degradation process track. These degradation trajectories can be represented as three temporal degradation curves: straight (linear), concave (concave) and convex (concave) lines, as shown in fig. 4, with the abscissa representing time and the ordinate representing degradation of the sensitive parameter, and the dashed line in the figure being the failure location. The straight line mainly represents the constant degradation rate; for a concave line, the degradation onset rate is faster, then slowly reaches saturation and approaches the failure point; the convex line is different, and is initially slow and rapidly degrades as the point of failure is approached.
For the accelerated degradation test, the degradation curve is a function of the acceleration stress in addition to the time. In order to obtain an extrapolation of the accelerated life test results to normal operating life, the effect of the accelerated stress needs to be taken into account. For example, for a temperature-accelerated concave degradation curve, if the temperature-reactivity acceleration equation is the arrhenius equation, the expression for the reactivity is:
R(T)=B*exp[-Ea/kB(T+273.15)]
in the above formula, T is temperature, kB is Boltzmann constant, Ea is activation energy, B represents a constant related to a device, and different values of B are different for different devices.
The expression of the acceleration factor AF is AF (T) ═ AF (T, T)0,Ea)=R(T)/R(T0) Wherein, T0Representing the original temperature compared to T. The expression of the degradation curve D (T, T) is D (T, T) ═ D ∞ {1-exp [ - { R (T)0)*AF(T)}*t]}. The graph of accelerated test versus concave degradation at different temperatures is shown in fig. 5. The abscissa in the graph represents time, the ordinate represents change of sensitive parameters, and curves in the graph are respectively a graph of an accelerated test versus concave degradation curve at 80 ℃, 150 ℃, 195 ℃ and 237 ℃ from top to bottom.
To build a life prediction model, the distribution of the individual failure modes and the correlation between the individual failure modes are analyzed first, and the distribution of the individual failure mechanisms is known second. When the failure rate of each failure mode is constant, the relationship between the total reliability R, the cumulative distribution function F and the total failure rate h of the components and the reliability, the distribution function and the failure rate of each single failure mechanism is shown as the following formula, wherein the subscript i in the formula is represented as the ith single failure mechanism, Ri(t) reliability of the ith single failure mechanism, Fi(t) distribution function, h, representing the ith single failure mechanismi(t) denotes the ith singleFailure rate of failure mechanism.
<math> <mrow> <mi>R</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> <mo>=</mo> <munderover> <mi>&Pi;</mi> <mrow> <mi>i</mi> <mo>=</mo> <mn>1</mn> </mrow> <mi>k</mi> </munderover> <msub> <mi>R</mi> <mi>i</mi> </msub> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> </mrow> </math>
<math> <mrow> <mi>F</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> <mo>=</mo> <mn>1</mn> <mo>-</mo> <munderover> <mi>&Pi;</mi> <mrow> <mi>i</mi> <mo>=</mo> <mn>1</mn> </mrow> <mi>k</mi> </munderover> <mrow> <mo>(</mo> <mn>1</mn> <mo>-</mo> <msub> <mi>F</mi> <mi>i</mi> </msub> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> <mo>)</mo> </mrow> </mrow> </math>
<math> <mrow> <mi>h</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> <mo>=</mo> <munderover> <mi>&Sigma;</mi> <mrow> <mi>i</mi> <mo>=</mo> <mn>1</mn> </mrow> <mi>k</mi> </munderover> <msub> <mi>h</mi> <mi>i</mi> </msub> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> </mrow> </math>
The competitive risk model establishes a life prediction model through the following three steps: observing life distribution data; determining the service life distribution of the failures caused by different failure modes; and establishing a life prediction model.
The competition risk model is based on a service life prediction model which is used more in the parameter degradation service life test, has higher accuracy, and can deal with the condition that a plurality of failure modes simultaneously act. All failure mechanisms work, looking at which failure mechanism leads to device failure first. In this competition, the failure mechanisms are not related to each other, and they simply progress along their respective paths, with the failure mechanism "reached" first causing the device to fail.
Examples are as follows: assume that the tested device has 2 competing failure modes: the first failure mode is a soft failure caused by the degradation of the parameter y (t); the second failure mode is a hard failure due to the termination of the function of the component.
The degradation mode is linear degradation with the degradation rate being a constant mu; the measurement error distribution is random, so the parameter degradation y (t) can be described by the following model:
Y(t)=Y0+σW(t-t0)+μ(t-t0),t≥t0
wherein W (t) is the standard Brownian equation of motion. For a given failure point S. The lifetime TS is the time Y (t) first reaches S. For Y0< S, the lifetime TS follows the inverse Gaussian distribution described by the Legesgne equation.
<math> <mrow> <msub> <mi>f</mi> <mi>TS</mi> </msub> <mo>=</mo> <mfrac> <mrow> <mi>S</mi> <mo>-</mo> <msub> <mi>Y</mi> <mn>0</mn> </msub> </mrow> <msqrt> <msup> <mrow> <mn>2</mn> <mi>&pi;&sigma;</mi> </mrow> <mn>2</mn> </msup> <msup> <mrow> <mo>(</mo> <mi>t</mi> <mo>-</mo> <msub> <mi>t</mi> <mn>0</mn> </msub> <mo>)</mo> </mrow> <mn>3</mn> </msup> </msqrt> </mfrac> <mi>exp</mi> <mrow> <mo>(</mo> <mo>-</mo> <mfrac> <msup> <mrow> <mo>(</mo> <mi>S</mi> <mo>-</mo> <msub> <mi>Y</mi> <mn>0</mn> </msub> <mo>-</mo> <mi>&mu;</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>-</mo> <msub> <mi>t</mi> <mn>0</mn> </msub> <mo>)</mo> </mrow> <mo>)</mo> </mrow> <mn>2</mn> </msup> <mrow> <msup> <mrow> <mn>2</mn> <mi>&sigma;</mi> </mrow> <mn>2</mn> </msup> <mrow> <mo>(</mo> <mi>t</mi> <mo>-</mo> <msub> <mi>t</mi> <mn>0</mn> </msub> <mo>)</mo> </mrow> </mrow> </mfrac> <mo>)</mo> </mrow> <mi>I</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>></mo> <msub> <mi>t</mi> <mn>0</mn> </msub> <mo>)</mo> </mrow> </mrow> </math>
Since the surviving device under test does not reach the failure point S during testing, in order to obtain the likelihood equation, a probability density function that truncates the Wiener process must be found. Suppose Yj-1,YjIs tj-1And tjDegradation value at time, for tj-1≤τ≤tjAnd Y (t) probability density distribution of Y (τ) < S is:
Figure BSA00000409171600082
on the other hand, for hard failure data, hard failures yield a weibull distribution based on EDA analysis, and the probability density function f (t) is defined as follows:
<math> <mrow> <mi>f</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> <mo>=</mo> <mfrac> <mi>&beta;</mi> <mi>&eta;</mi> </mfrac> <msup> <mrow> <mo>(</mo> <mfrac> <mi>t</mi> <mi>&eta;</mi> </mfrac> <mo>)</mo> </mrow> <mrow> <mi>&beta;</mi> <mo>-</mo> <mn>1</mn> </mrow> </msup> <msup> <mi>e</mi> <mrow> <mo>-</mo> <msup> <mrow> <mo>(</mo> <mfrac> <mi>t</mi> <mi>&eta;</mi> </mfrac> <mo>)</mo> </mrow> <mi>&beta;</mi> </msup> </mrow> </msup> </mrow> </math>
the invention uses the likelihood method to obtain the parameters in the competition risk model, and the service life of the tested device can be predicted by solving the likelihood equation through the test data, wherein the likelihood equation is as follows:
<math> <mrow> <mi>L</mi> <mrow> <mo>(</mo> <mi>x</mi> <mo>,</mo> <mi>&theta;</mi> <mo>)</mo> </mrow> <mo>=</mo> <mfenced open='' close=''> <mtable> <mtr> <mtd> <munderover> <mi>&Pi;</mi> <mrow> <mi>i</mi> <mo>=</mo> <mn>1</mn> </mrow> <mi>n</mi> </munderover> <mo>{</mo> <munderover> <mi>&Pi;</mi> <mrow> <mi>j</mi> <mo>=</mo> <mn>1</mn> </mrow> <msub> <mi>M</mi> <mi>i</mi> </msub> </munderover> <mo>[</mo> <mfrac> <mn>1</mn> <mrow> <mi>&sigma;</mi> <msqrt> <msub> <mi>t</mi> <mi>ij</mi> </msub> <mo>-</mo> <msub> <mi>t</mi> <mrow> <mi>ij</mi> <mo>-</mo> <mn>1</mn> </mrow> </msub> </msqrt> </mrow> </mfrac> <mi>&phi;</mi> <mo>[</mo> <mfrac> <mrow> <mrow> <mo>(</mo> <msub> <mi>Y</mi> <mi>ij</mi> </msub> <mo>-</mo> <msub> <mi>Y</mi> <mrow> <mi>ij</mi> <mo>-</mo> <mn>1</mn> </mrow> </msub> <mo>)</mo> </mrow> <mo>-</mo> <mi>&mu;</mi> <mrow> <mo>(</mo> <msub> <mi>t</mi> <mi>ij</mi> </msub> <mo>-</mo> <msub> <mi>t</mi> <mrow> <mi>ij</mi> <mo>-</mo> <mn>1</mn> </mrow> </msub> <mo>)</mo> </mrow> </mrow> <mrow> <mi>&sigma;</mi> <msqrt> <msub> <mi>t</mi> <mi>ij</mi> </msub> <mo>-</mo> <msub> <mi>t</mi> <mrow> <mi>ij</mi> <mo>-</mo> <mn>1</mn> </mrow> </msub> </msqrt> </mrow> </mfrac> <mo>]</mo> </mtd> </mtr> <mtr> <mtd> <mo>&times;</mo> <mo>[</mo> <mn>1</mn> <mo>-</mo> <mi>exp</mi> <mo>{</mo> <mo>-</mo> <mfrac> <mrow> <mn>2</mn> <mrow> <mo>(</mo> <mi>S</mi> <mo>-</mo> <msub> <mi>Y</mi> <mrow> <mi>ij</mi> <mo>-</mo> <mn>1</mn> </mrow> </msub> <mo>)</mo> </mrow> <mrow> <mo>(</mo> <mi>S</mi> <mo>-</mo> <msub> <mi>Y</mi> <mi>ij</mi> </msub> <mo>)</mo> </mrow> </mrow> <mrow> <msup> <mi>&sigma;</mi> <mn>2</mn> </msup> <mrow> <mo>(</mo> <msub> <mi>t</mi> <mi>ij</mi> </msub> <mo>-</mo> <msub> <mi>t</mi> <mrow> <mi>ij</mi> <mo>-</mo> <mn>1</mn> </mrow> </msub> <mo>)</mo> </mrow> </mrow> </mfrac> <mo>}</mo> <mo>]</mo> </mtd> </mtr> </mtable> </mfenced> </mrow> </math>
<math> <mrow> <mo>&times;</mo> <msup> <mrow> <mo>[</mo> <mfrac> <mrow> <mi>S</mi> <mo>-</mo> <msub> <mi>Y</mi> <mi>iMi</mi> </msub> </mrow> <mrow> <mi>&sigma;</mi> <msqrt> <mrow> <mo>(</mo> <msub> <mi>&tau;</mi> <mi>i</mi> </msub> <mo>-</mo> <msub> <mi>t</mi> <mi>iMi</mi> </msub> <mo>)</mo> </mrow> </msqrt> </mrow> </mfrac> <mi>&phi;</mi> <mo>[</mo> <mfrac> <mrow> <mrow> <mo>(</mo> <mi>S</mi> <mo>-</mo> <msub> <mi>Y</mi> <mi>iMi</mi> </msub> <mo>)</mo> </mrow> <mo>-</mo> <mi>&mu;</mi> <mrow> <mo>(</mo> <msub> <mi>&tau;</mi> <mi>i</mi> </msub> <mo>-</mo> <msub> <mi>t</mi> <mi>iMi</mi> </msub> <mo>)</mo> </mrow> </mrow> <mrow> <mi>&sigma;</mi> <msqrt> <mrow> <mo>(</mo> <msub> <mi>&tau;</mi> <mi>i</mi> </msub> <mo>-</mo> <msub> <mi>t</mi> <mi>iMi</mi> </msub> <mo>)</mo> </mrow> </msqrt> </mrow> </mfrac> <mo>]</mo> <mo>]</mo> </mrow> <mrow> <msub> <mi>I</mi> <mrow> <mo>(</mo> <mi>Mi</mi> <mo>&lt;</mo> <mi>mi</mi> </mrow> </msub> <mo>)</mo> <mi>&delta;</mi> </mrow> </msup> <mo>&times;</mo> <msup> <mrow> <mo>[</mo> <mfrac> <mi>&beta;</mi> <mi>&eta;</mi> </mfrac> <msup> <mrow> <mo>(</mo> <mfrac> <msub> <mi>t</mi> <mi>iMi</mi> </msub> <mi>&eta;</mi> </mfrac> <mo>)</mo> </mrow> <mrow> <mi>&beta;</mi> <mo>-</mo> <mn>1</mn> </mrow> </msup> <msup> <mi>e</mi> <mrow> <mo>-</mo> <msup> <mrow> <mo>(</mo> <mfrac> <msub> <mi>t</mi> <mi>iMi</mi> </msub> <mi>&eta;</mi> </mfrac> <mo>)</mo> </mrow> <mi>&beta;</mi> </msup> </mrow> </msup> <mo>]</mo> </mrow> <mi>&delta;</mi> </msup> <msup> <mi>e</mi> <mrow> <mo>-</mo> <msup> <mrow> <mo>(</mo> <mfrac> <msub> <mi>t</mi> <mi>iMi</mi> </msub> <mi>&eta;</mi> </mfrac> <mo>)</mo> </mrow> <mi>&beta;</mi> </msup> </mrow> </msup> <mo>}</mo> </mrow> </math>
wherein,
Figure BSA00000409171600093
the competition risk model is a service life prediction model which is used more in parameter-based degradation service life tests at present, and obtains higher accuracy in service life prediction of electronic components. The competitive risk mode is a component reliability model constructed from each single failure mode in a bottom-up mode. The main idea of the competitive risk model is that all failure mechanisms work, looking at which failure mechanism leads to device failure first. In this competition, the failure mechanisms are not related to each other, and they simply progress along their respective paths, with the failure mechanism "reached" first causing the device to fail. In this case, component reliability is the product of various failure mode reliabilities, and component failure rate is the sum of the failure mode failure rates.
The invention finally forms a life prediction method of the MOS device based on the parameter degradation of the failure mechanism by analyzing the failure mechanism and the failure mode of the MOS device. The invention provides a new method for predicting the service life of the MOS device, solves the problems of accuracy and operability of the traditional device service life prediction method under new technical conditions, reduces the number of test samples, reduces the test cost, improves the accuracy of the predicted test result, provides theoretical basis for the test result, helps extensive research personnel, designers and the like to effectively improve the service life of the device aiming at the failure mechanism of the MOS device, reduces the test period and accelerates the product to come into the market.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims (5)

1. A method for predicting lifetime of a MOS device, the method comprising:
s1, analyzing the correlation between the physical failure mechanism of the device and the macroscopic parameter degradation of the device, and constructing a macroscopic parameter degradation model of the device based on the physical failure mechanism;
s2, performing reliability simulation on the device, and analyzing the sensitivity of macroscopic parameter degradation of the device to a physical failure mechanism;
s3, selecting a stress applying mode, performing parameter-based degradation life test on the device and acquiring reliability test data;
s4, analyzing the reliability test data, and establishing a life prediction calculation model based on parameter degradation;
and S5, obtaining the life prediction result of the device according to the life prediction calculation model.
2. The method of claim 1, wherein the physical failure mechanism in step S1 includes hot carrier injection, time dependent dielectric breakdown, negative bias instability and/or electromigration.
3. The MOS device lifetime prediction method of claim 1, wherein the reliability test data in the step S3 includes data of variation of sensitive parameters of the device with time and data of hard failure of the device.
4. The method of predicting the lifetime of a MOS device as set forth in claim 1, wherein in the step S3, the stress applying manner is determined by using an arrhenius model, an E model, an allin model, or a combination thereof.
5. The MOS device lifetime prediction method of claim 1, wherein the step S4 includes: the distribution of the various single failure modes of the device and the correlation between the various single failure modes are analyzed.
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Application publication date: 20120711