CN102567149B - SOC system Authentication method - Google Patents
SOC system Authentication method Download PDFInfo
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- CN102567149B CN102567149B CN201010581661.XA CN201010581661A CN102567149B CN 102567149 B CN102567149 B CN 102567149B CN 201010581661 A CN201010581661 A CN 201010581661A CN 102567149 B CN102567149 B CN 102567149B
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Abstract
The invention discloses a kind of SOC system Authentication method, when module level is verified, the input/output port of processor in definition SOC system, by the operation of all about processor, call a unique system task, operated by described port, set up the mirror registers of module, maintenance image register value; When subsystem is verified, multiplexing described port describes, and after the operation about processor being integrated, still uses unique system task to operate; When whole-system verification, using described port as a bus monitoring, when executive software, synchronous mirror register, realizes verification environment multiplexing.The present invention can make module level verification environment as a subenvironment of whole-system verification substantially, realizes whole-system verification environment and module level verification environment is multiplexing.
Description
Technical field
The present invention relates to a kind of SOC system Authentication method, being applicable to general take central processing unit as SOC (systemonchip system on a chip) system verification of core.
Background technology
SOC checking is often from module to system, and module level checking is only for single peripheral module, and mostly the operation of processor to it is that register is read and write, and general checking carrys out read-write register by analog processor sequential, and checking emphasis is peripheral module function.Whole system can be integrated by subsystem level verification, but still carrys out read-write register by verification environment analog processor sequential, and checking emphasis is system architecture.Whole-system verification can be put into processor and read in software code, and checking emphasis is the cooperation of software and hardware.
Module level checking establishes the verification environment of complete complexity, after verifying, again according to system architecture reconstructing system level verification environment when entering system verification.If whole-system verification environment can Multiplexing module level verification environment can direct elevator system verification efficiency.This just needs a kind of verification method to carry out provisioning modules level verification environment, can be multiplexing by more whole-system verification environment.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of SOC system Authentication method, and module level verification environment can be made substantially as a subenvironment of whole-system verification, realizes whole-system verification environment and module level verification environment is multiplexing.
For solving the problems of the technologies described above, SOC system Authentication method of the present invention adopts following technical scheme to realize:
Define the input/output port of processor in SOC system when module level is verified, when module level is verified by the operation of all about processor, call a unique system task, operated by described port; The mirror registers of module is set up, maintenance image register value when module level is verified;
When subsystem level verification, multiplexing described port describes, and after the operation about processor being integrated, still uses unique system task to operate;
When whole-system verification, using described port as a bus monitoring, when executive software, synchronous mirror register, realizes verification environment multiplexing.
Method of the present invention focuses on multiplexing to whole-system verification environment of module level verification environment, the interface definition of whole-system verification is just carried out in module level checking, mirror registers, and module level checking subenvironment, multiplexing by interface and behavior model, just easier can build subsystem level verification environment and whole-system verification environment, realize whole-system verification environment and module level verification environment is multiplexing.
Traditional whole-system verification method, often will spend the time being equal to and even exceeding module level checking when whole-system verification.
Method of the present invention, owing to achieving the multiplexing of module level verification environment and whole-system verification environment, can allow whole-system verification environment fast construction on module level verification environment basis, shorten the chip system proving time, better ensure chip functions; There is higher efficiency and confidence level.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is module level verification environment schematic diagram;
Fig. 2 is subsystem level verification environment schematic;
Fig. 3 is whole-system verification environment schematic.
Embodiment
This method mainly proposes a kind of method authenticating to the multiplexing verification environment of whole-system verification from module level.
Shown in Figure 1, before module level checking, definition processor port (or claiming interface) 100, this interface is all drive singal of processor, from module level to system-level, any for signal level, other is operated the interface that all can be defined by this group and drives, and so just effectively reduces change.Call analog processor by a system task (processor tasks namely shown in Fig. 1) 110 to read and write the register of module to be measured.In order to multiplexing, all registers all use macro definition to describe, to register manipulation for register name instead of register address; Because whole-system verification exists address maps, can module level verification environment still can be worked in whole-system verification environment by replacing macro definition.By all functional modes for module to be measured, temporal model, Self-adaptive, data self-inspection is all encapsulated in module level checking subenvironment 120, and module level checking subenvironment 120 is connected with processor tasks 110 by passage 130; The read-write of all registers is all packaged as a data class, by passage 130, carrys out decryption class and analog processor is read and write register by processor tasks 110.In addition, if the function port of module to be measured is connected system module instead of chip exterior interface when whole-system verification, then subenvironment 120 monitors module operation result to be measured module level can be allowed to verify by the data of observing on interface 140.
When setting up module level verification environment 150, also must set up all register image, mirror registers state can be preserved, here district in two kinds of situation, if the register controlled by processor merely, when module level is verified, read operation by reading mirror registers state, can obtain the state of current module to be measured; After write operation, upgrade register value.If by the mirror registers of software and hardware co-controlling, actual inside modules value to be measured must be read by processor tasks 110.So just distinguish the mirror registers mode of operation of module level checking and whole-system verification.
When subsystem level verification, because the function of module is constant, so module level checking subenvironment 120 still can use, can multiple module level checking subenvironment be merged in a sub-whole-system verification environment 200, as module level checking subenvironment (1) 210 in Fig. 2, module verification subenvironment (2) 220.Shown in composition graphs 2, comprise processor bus 230 in subsystem to be measured, needed address maps, the register macro definition of the register macro definition replacement module level verification of subsystem level verification can have been used.Processor is not had to get involved in subsystem verification environment, also need analog processor behavior read-write register, read-write operation is Depending module level verification environment still, need the processor tasks 110 of module level to merge into a subsystem processor task 240, module level is verified that the read-write register passage 250,260 of subenvironment 210,220 is all connected to subsystem processor task 240 simultaneously.
Shown in composition graphs 3, when whole-system verification, whole-system verification environment 300 can multiplexing subsystem level verification environment, because whole subsystem level verification environment is all fixed, the difference of subsystem level verification environment and whole-system verification environment is only, whole-system verification uses real processor and software, and namely mirror registers read-write operation does not need verification environment to simulate but directly completed by processor software 310.So the difference of verification environment is that subsystem processor task 240 can also read and write bus, and system processor task 320 is merely able to observe the data in bus and can not write data.
The read-write operation observed all is recorded and is kept in queue by system processor task 320, then the value of mirror registers is upgraded, here two kinds of situations are divided into equally, if by the mirror registers of software control, as long as the value that whole-system verification environment 300 reads mirror registers just can meet the state judging module to be measured.If by the mirror registers of software and hardware co-treatment, when whole-system verification environment 300 sends write operation, system processor task 320 will wait for the operation newly entering queue, and search in software operation the write operation whether having address date to mate, if the write operation failing to find coupling in queue can be waited for always, until after obtaining matching operation, the write operation of system verification environment completes.When whole-system verification environment 300 sends read operation, system processor task 320 waits for the read operation newly entering queue, and search the read operation of matching addresses, if the read operation failing to find coupling in queue can be waited for always, until there is matching operation, and the data that this operation obtains are returned to system environments.
Realize above behavior and must have certain verification environment and the interoperation of software, but the most basic framework that instructs is set up, thereupon just according to the adjustment of detailed programs, as long as the operation processing mirror registers comparatively speaking just can the checking of completion system level software and hardware.
Adopt method of the present invention, the structure of module level verification environment is kept down by major part, by amendment system task, coordinates software upgrading mirror registers, just can realize the multiplexing of whole-system verification environment and module level verification environment.
Above by embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (6)
1. a SOC system Authentication method, is characterized in that:
When module level is verified, in definition SOC system, the input/output port of processor, by unique for the operation calls of all about processor system task, is operated by described port; Set up the mirror registers of module, maintenance image register value;
When subsystem is verified, multiplexing described port describes, and after the operation about processor being integrated, still uses unique system task to operate;
When whole-system verification, using described port as a bus monitoring, when executive software, synchronous mirror register, realizes verification environment multiplexing.
2. the method for claim 1, it is characterized in that: in described definition SOC system, the input/output port of processor refers to, processor for the SOC system core defines unique input/output port, in module level checking and whole-system verification, all call this port.
3. the method for claim 1, is characterized in that: the described mirror registers setting up module refers to, establish mirror image register preservation state, distinguishes and treats mirror registers reading manner, so that whole-system verification environment is multiplexing.
4. method as claimed in claim 3, is characterized in that: described differentiation is treated mirror registers reading manner and referred to,
If the register controlled by processor merely, when module level is verified, read operation is by reading mirror registers state, obtains the state of current module to be measured; After write operation, upgrade the value of mirror registers;
If by the mirror registers of software and hardware co-controlling, the intrinsic value of actual module to be measured must be read by system task.
5. the method for claim 1, it is characterized in that: described unique for the operation calls of all about processor system task to be referred to, all processor behaviors are operated by a unique system task, mirror registers configuration is directly completed when module level is verified, address maps analysis need be carried out to mirror registers when subsystem is verified, during whole-system verification, then by software execution result synchronous mirror register value.
6. the method for claim 1, is characterized in that: described using described port as a bus monitoring, when executive software, synchronous mirror register refers to,
System processor task is merely able to the data in observation processor bus and can not writes data;
The read-write operation observed all is recorded and is kept in queue by system processor task, then upgrades the value of mirror registers;
If by the mirror registers of software control, as long as the value reading mirror registers just can judge the state of module to be measured; If by the mirror registers of software and hardware co-treatment, when whole-system verification sends write operation, system processor task will wait for the operation newly entering queue, and search in software operation the write operation whether having address date to mate, if fail to find the write operation of coupling in queue, wait for, until the write operation of system verification environment completes after obtaining matching operation always;
When whole-system verification sends read operation, system processor task is waited for and is newly entered the read operation of queue, and searches the read operation of matching addresses, if fail to find the read operation of coupling in queue, waits for always, until there is matching operation, and the data that this operation obtains are returned to system environments.
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| CN201010581661.XA CN102567149B (en) | 2010-12-09 | 2010-12-09 | SOC system Authentication method |
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| CN201010581661.XA CN102567149B (en) | 2010-12-09 | 2010-12-09 | SOC system Authentication method |
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| CN102567149B true CN102567149B (en) | 2016-03-23 |
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| CN104461909B (en) * | 2015-01-06 | 2018-05-04 | 浪潮(北京)电子信息产业有限公司 | A kind of accidental validation appraisal procedure and system |
| CN105158681A (en) * | 2015-08-07 | 2015-12-16 | 广州中大微电子有限公司 | Radio frequency identification reader chip verification method and system |
| CN105512418A (en) * | 2015-12-18 | 2016-04-20 | 山东海量信息技术研究院 | Method for realizing block level verification through multiplexing system level model verification environment |
| CN106599343B (en) * | 2016-11-01 | 2020-10-20 | 深圳国微技术有限公司 | SOC system verification method and device for improving simulation efficiency |
| US11907088B2 (en) | 2021-12-15 | 2024-02-20 | Synopsys, Inc. | Testing of hardware queue systems using on device test generation |
| CN114417780B (en) * | 2021-12-16 | 2022-11-01 | 北京百度网讯科技有限公司 | State synchronization method and device, electronic equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1637737A (en) * | 2003-11-03 | 2005-07-13 | 旺宏电子股份有限公司 | In-circuit configuration structure with configuration initialization function |
| CN101063979A (en) * | 2006-04-28 | 2007-10-31 | 中国科学院计算技术研究所 | MPU FPGA verification device supporting stochastic instruction testing |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7036106B1 (en) * | 2000-02-17 | 2006-04-25 | Tensilica, Inc. | Automated processor generation system for designing a configurable processor and method for the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1637737A (en) * | 2003-11-03 | 2005-07-13 | 旺宏电子股份有限公司 | In-circuit configuration structure with configuration initialization function |
| CN101063979A (en) * | 2006-04-28 | 2007-10-31 | 中国科学院计算技术研究所 | MPU FPGA verification device supporting stochastic instruction testing |
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