CN102546071A - Clock synchronization method and system - Google Patents
Clock synchronization method and system Download PDFInfo
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- CN102546071A CN102546071A CN2011104392304A CN201110439230A CN102546071A CN 102546071 A CN102546071 A CN 102546071A CN 2011104392304 A CN2011104392304 A CN 2011104392304A CN 201110439230 A CN201110439230 A CN 201110439230A CN 102546071 A CN102546071 A CN 102546071A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0697—Synchronisation in a packet node
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Abstract
An embodiment of the invention provides a clock synchronization method, which includes of acquiring the transmission time T1 of synchronous messages after receiving the synchronous messages; recording the clock count T2 of a local crystal oscillator when the synchronous messages arrive; sending delay correction application messages, recording the clock count T3 of the local crystal oscillator when in sending of the delay correction application messages and starting counting of a synchronous Ethernet clock; receiving the time T4 for main clock equipment to receive the delay correction application messages after receiving delay correction application response messages; computing transmission delay according to the T1, the T2, the T3 and the T4, and computing the main clock equivalence of the T3 according to the T1, the T2, the T3 and the transmission delay; summing the main clock equivalence of the T3 and the current counting value of the synchronous Ethernet clock, and finally regulating clock output according to the summing results. The invention further provides a clock synchronization system. By the clock synchronization method and the clock synchronization system in the technical scheme, complexity of clock synchronization is reduced, convergence rate is increased and cost is saved.
Description
Technical field
The present invention relates to wireless communication technology field, relate in particular to a kind of clock synchronizing method and system of wireless communication system.
Background technology
Clock Synchronization Technology is the basic fundamental of communication system.The purpose of clock synchronization is that the time of guaranteeing transmitting terminal and receiving terminal acts in agreement, to realize correct, reliable communication.Along with the development of information technology, to time synchronized require increasingly high.Current most of TDD (Time Division Duplexing; Time division duplex) communication technology of pattern; Like TD-SCDMA, CDMA2000, WiMAX etc., and the LTE system that is is researching and developing and disposing, often need the whole network to keep precise time or Phase synchronization between eating dishes without rice or wine; Usually frequency stability requires within ± 0.05ppm, and phase accuracy is at least in ± 5 μ s scopes.For realizing clock synchronization, the common practice of prior art is to adopt based on GPS and OCXO (the base station clock extracting mode of OCXO (OvenControlled Crystal Oscillator, constant-temperature crystal oscillator oscillator).This mode receives the clock signal of satellite transmission through the gps signal receiving system that is installed in each base station; Carry out the reaction type regression algorithm in base station side then; 1pps signal and OCXO output base station synchronization signal to the original output of GPS carry out the high frequency phase demodulation, carry out realizing that the whole network is synchronous behind the statistical filtering.Yet, need set up and safeguard gps antenna and corresponding indoor forwarding unit based on the base station clock extracting mode of GPS and OCXO, the base station clock plate adopts high-precision voltage-controlled OCXO, and whole clock synchronization process is complicated, convergence rate is slow, and cost is higher.In addition,, under the harsh weather situation, cause step-out between system base-station easily, higher cutting off rate occurs because the gps signal effect receives weather effect bigger.
Summary of the invention
Because the problem that the clock synchronizing method of prior art exists; The goal of the invention of the embodiment of the invention is to provide a kind of new clock synchronizing method and system, with the complexity of the clock synchronization process that reduces prior art, improve that synchronous convergence rate is slow, the workout cost problem of higher.
The clock synchronizing method that the embodiment of the invention provides comprises:
Receive the synchronization message that clock equipment is sent, resolve synchronization message, obtain the synchronization message transmitting time T1 that synchronization message comprises; The clock count T2 of local crystal oscillator when the record synchronization message arrives;
Proofread and correct solicitation message to the clock equipment forward delay interval, the clock count T3 of local crystal oscillator when record sends this application message, and start counting to synchronous Ethernet clock;
Receive time delay is proofreaied and correct the application response message, and resolution response message is obtained the clock equipment that response message comprises and received the time T 4 that solicitation message is proofreaied and correct in time-delay;
According to T1, T2, T3 and T4 calculated transmission delay, calculate the master clock equivalence value of T3 according to T1, T2, T3 and transmission delay;
The master clock equivalence value of T3 and the count value of synchronous Ethernet clock are carried out summation operation, adjust clock output according to the summation operation result.
Preferably, specifically comprise according to T1, T2, T3 and T4 calculated transmission delay: deduct T1 and T3 sum with T2 and T4 sum, with subtract each other the result divided by 2 to obtain transmission delay; The master clock equivalence value that calculates T3 according to T1, T2, T3 and transmission delay specifically comprises: the difference that adds T3 and T2 with T1 and transmission delay sum is to obtain the master clock equivalence value of T3.
Preferably; Calculate the frequency difference coefficient according to adjacent twice T1 and T2; Multiply by T2 and/or T3 respectively revising T2 and/or T3 with this frequency difference coefficient, saidly calculate the frequency difference coefficient according to adjacent twice T1 and T2 and specifically comprise: with the difference of adjacent twice T1 divided by the difference of adjacent twice T2 with acquisition frequency difference coefficient.
Preferably, when receiving the synchronization message of clock equipment transmission, start timer, when timer reaches Preset Time, proofread and correct solicitation message to the clock equipment forward delay interval.
Further preferably, said Preset Time scope is 2
MTo 2
M+1, said M is that clock equipment is proofreaied and correct the solicitation message Desired Min Tx Interval according to the time-delay of its data disposal ability indication.
The embodiment of the invention also provides a kind of clock system.This system comprises: first acquiring unit, first record cell, second record cell, clock count unit, second acquisition unit, first computing unit and adjustment unit, wherein:
Said first acquiring unit is used for after the synchronization message that receives the clock equipment transmission, resolving synchronization message, obtains the synchronization message transmitting time T1 that synchronization message comprises;
Said first record cell, the clock count T2 of local crystal oscillator when being used to write down synchronization message arrival;
Said second record cell is used at the clock count T3 that when the clock equipment forward delay interval is proofreaied and correct solicitation message, writes down local crystal oscillator;
Said clock count unit is used for when the clock equipment forward delay interval is proofreaied and correct solicitation message, starting the counting to synchronous Ethernet clock;
Said second acquisition unit is used for resolution response message after receive time delay is proofreaied and correct the application response message, obtains the clock equipment that response message comprises and receives the time T 4 that solicitation message is proofreaied and correct in time-delay;
Said first computing unit is used for according to T1, T2, T3 and T4 calculated transmission delay, calculates the master clock equivalence value of T3 according to T1, T2, T3 and transmission delay;
Said adjustment unit is used for exporting with the current count value sum adjustment clock to synchronous Ethernet clock according to the master clock equivalence value of T3.
Preferably, said first computing unit deducts T1 and T3 sum with T2 and T4 sum, with subtract each other the result divided by 2 to obtain transmission delay; The difference that adds T3 and T2 with T1 and transmission delay sum is to obtain the master clock equivalence value of T3.
Preferably, said system also comprises second computing unit and amending unit, and second computing unit is used for calculating the frequency difference coefficient according to adjacent twice T1 and T2; Said amending unit is used for the frequency difference coefficient multiply by T2 and/or T3 respectively revising T2 and/or T3, said second computing unit with the difference of adjacent twice T1 divided by the difference of adjacent twice T2 with acquisition frequency difference coefficient.
Preferably, said system also comprises timer, and this timer starts when receiving the synchronization message of clock equipment transmission, when timer reaches Preset Time, proofreaies and correct solicitation message to the clock equipment forward delay interval.
Preferably, the scope of said Preset Time is 2
MTo 2
M+1, said M is that clock equipment is proofreaied and correct the solicitation message Desired Min Tx Interval according to the time-delay of its data disposal ability indication.
The embodiment of the invention is proofreaied and correct the application response message from synchronization message and time-delay respectively and is parsed T1, T4;, synchronization message writes down the clock count T2 of local crystal oscillator when arriving;, writes down forward delay interval the clock count T3 of local crystal oscillator when proofreading and correct solicitation message; And enabling counting when sending solicitation message, through the master clock equivalence value that T1, T2, T3 and T4 calculate T3, export according to this equivalence value and synchronous Ethernet clock current count value sum adjustment clock.Compared with prior art; The embodiment of the invention in conjunction with local crystal oscillator counting, obtains the master clock equivalence value of T3 through simple operation after synchronization message and time-delay are applied for obtaining the corresponding time the response message; Export clock according to the clock count sum adjustment of equivalence value and synchronous ethernet then; Thereby realized clock synchronization, owing to avoided loaded down with trivial details calculating, the convergence rate of clock synchronization is accelerated.And the embodiment of the invention utilizes existing synchronous ethernet that clock is provided, and does not need to build in advance a large amount of gps antennas and indoor forwarding unit, need not carry out particular restriction to crystal oscillator equipment, has saved the GPS of operator deployment cost, thereby has reduced cost.In addition, the embodiment of the invention is utilized synchronous ethernet and is not adopted GPS, has the place of network can transmit clock, and the clock synchronization process no longer receives weather effect, has solved under the harsh weather situation between system base-station step-out easily, the problem of high cutting off rate occurred.
Description of drawings
Fig. 1 is the schematic diagram of the clock synchronization of prior art;
Fig. 2 is the flow chart of a method embodiment of the present invention;
Fig. 3 (a) is the flow chart of the instance of the said embodiment of Fig. 2;
Fig. 3 (b) is the hardware module figure of the said instance of Fig. 3;
Fig. 4 is the composition frame chart of system embodiment of the present invention.
Embodiment
The embodiment of the invention provides a kind of new clock synchronizing method and corresponding system; This method and system is proofreaied and correct the application response message from synchronization message and time-delay and is parsed T1, T4;, synchronization message writes down the clock count T2 of local crystal oscillator when arriving; When forward delay interval is proofreaied and correct solicitation message, write down the clock count T3 of local crystal oscillator, and enabling counting when sending solicitation message, calculate the master clock equivalence value of T3 through T1, T2, T3 and T4; According to this equivalence value and the output of synchronous Ethernet clock current count value sum adjustment clock; Thereby realized the clock synchronization process through simple calculating,, improved the convergence rate of clock synchronization owing to avoided loaded down with trivial details computing; Owing to do not adopt GPS and OCXO, need not carry out antenna installation and indoor equipment is purchased, reduced cost, the clock synchronization process no longer receives weather effect.
For ease of understanding technical scheme of the present invention and technical characterictic, below the principle of clock synchronization of first brief prior art, combine accompanying drawing of the present invention and embodiment that the present invention is described in detail then.
IEEE-USA (IEEE) began in 2000 to standard synchronous protocol exact time synchronization agreement (the Precision Time Protocol of commercial measurement with the control application; Be called for short the PTP agreement; Claim 1588 agreements again) develop; Be used to satisfy the specific demand of applications such as commercial measurement and control, like distributed environment, microsecond or submicrosecond precision, application such as Unsupervised.Growing along with from other application synchronisation requirement, IEEE has developed the enhanced characteristic version on the 1588v1 basis of issue in 2002, and promptly IEEE 1588TM-2008 is called for short 1588v2.1588v2 can satisfy and comprises measurement and various fields such as control, industrial automation, military affairs and the telecommunication system demand to frequency and time synchronized.The master-slave mode topological structure is adopted in 1588 networkings, for being in terminal base station, only realizes that the ordinary clock (ordinary clock) of slave pattern in the agreement gets final product usually.
Referring to accompanying drawing 1, the figure shows the principle of clock synchronization.Time synchronization process is mutual through the PTP protocol message, slave (from) end calculates transmission delay (Delay) and the time migration (Offset) with respect to master clock, utilizes this transmission delay and time migration to revise local clock gradually, finally approaches master clock.The system of PTP agreement clock synchronization mechanism comprises a master clock and a plurality of from clock; Time synchronized is mainly through beating timestamp in transmit leg and recipient, comprising the information of time, and realizes in the time-delay of transmission through network according to time deviation and the temporal information that timestamp calculates master clock the recipient.The PTP protocol definition four kinds of type of messages, comprise Sync (synchronization message), FollowUp (following message), DelayReq (solicitation message is proofreaied and correct in time-delay) and DelayResp (time delay adjustment application response message).The difference of principal and subordinate's clock mainly is made up of at the transmission delay Delay of network clock jitter Offset and packets of information.PTP agreement clock synchronization mechanism mainly is divided into two stages, offset correction and time-delay calibration phase.
In the offset correction stage, i.e. in the A stage among the figure, at first send Sync message constantly to from clock at T1 by master clock, in Sync message, comprise a timestamp, the scheduled time that data are sent has been described.Because what synchronization message comprised is to estimate to send the time rather than truly send the time, Sync message is sent measured back of time really by sending in the FollowUp message subsequently.From clock one side, note the real time of reception T2 of Sync message, can calculate from the time deviation T_ms:T_ms=T2-T1 of clock by T1 and T2 with respect to master clock.Can proofread and correct from clock by this time deviation, but the result who calculates thus includes the time-delay that temporal information causes in transmission through network the correction of therefore also need delaying time.
In time-delay calibration phase, i.e. B stage among the figure.At first by sending DelayReq information from clock to master clock; Send time T 3 down from clock log; Master clock is noted the correct time T4 of reception, and should turn back to from clock through DelayResp the time, goes out network delay T_sm=T4-T3 from clock through these two Time Calculation.Obtain offset=(T_ms-T_sm)/2, Delay=(T_ms+T_sm)/2 thus.Can revise local clock time in view of the above after calculating offset and Delay.
As aforementioned said, for realizing clock synchronization, prior art is carried out clock synchronization based on above-mentioned principle by GPS and OCXO, and there are many shortcomings in this mode.For this reason, the embodiment of the invention provides a kind of clock synchronizing method.Referring to accompanying drawing 2, the figure shows the flow chart of one embodiment of the present of invention, the clock synchronizing method of present embodiment comprises:
Step S201: receive the synchronization message that clock equipment is sent, resolve synchronization message, obtain the synchronization message transmitting time T1 that this synchronization message comprises; The clock count T2 of local crystal oscillator when the record synchronization message arrives;
For realizing clock synchronization, clock equipment can regularly or periodically be sent synchronization message, includes the transmitting time T1 that clock equipment is sent this synchronization message in the synchronization message, and this T1 is the standard time.After base station side receives synchronization message, synchronization message is resolved, obtain the T1 that synchronization message comprises.The clock count T2 of the local crystal oscillator of (when synchronization message reaches) record when base station side receives synchronization message, this T2 is from clock time, has skew with respect to master clock.Here need to prove: clock equipment no matter, still from clockwork, all through clock pulse is counted to get the time, T1, T2 exist with the form of clock pulse quantitative value.
Step S202: proofread and correct solicitation message to the clock equipment forward delay interval, the clock count T3 of local crystal oscillator when record sends this application message, and start counting to synchronous Ethernet clock;
After the base station receives synchronization message; To proofread and correct solicitation message to the clock equipment forward delay interval; Here it should be noted that forward delay interval proofreaies and correct solicitation message and can carry out in any moment after receiving synchronization message, but in practical application, in order to reserve the time-delay of relevant device existence itself; The present invention preferably sets a timer, and just forward delay interval is proofreaied and correct solicitation message when the Preset Time of timer arrives.When sending this application message, need carry out record, and start counting synchronous Ethernet clock to local crystal oscillator clock count T3.Here start and to carry out through the mode of interrupting, promptly when sending time-delay correction solicitation message, produce an interruption, carry out clock count by this interrupt notification to the ethernet clock counting.
Step S203: receive time delay is proofreaied and correct the application response message, resolves and obtains the clock equipment that this response message comprises and receive the time T 4 that solicitation message is proofreaied and correct in time-delay;
Base station side is after the clock equipment forward delay interval is proofreaied and correct solicitation message; Clock equipment will be proofreaied and correct the application response message to the base station side return time delay; This response message comprises the time T 4 that clock equipment receives the time delay adjustment application, and base station side obtains therefrom to parse this time T 4 behind the response message.
Step S204:, calculate the master clock equivalence value of T3 according to T1, T2, T3 and transmission delay according to T1, T2, T3 and T4 calculated transmission delay;
Obtain after T1, T2, T3 and the T4 according to abovementioned steps; Can be according to these four amount calculated transmission delay delay; The mode of concrete calculated transmission delay is a lot, only is the difference on the operational formula between the different modes, and the embodiment of the invention preferably deducts T1 and T3 sum with T2 and T4 sum; Again with the result that subtracts each other divided by 2 to obtain transmission delay delay, formula is: delay=[(T2+T4)-(T1+T3)]/2.Obtain transmission delay delay; Can be according to the master clock equivalence value that calculates T3 according to T1, T2, T3 and transmission delay; This master clock equivalence value is the standard time of corresponding master clock of the T3 moment; The concrete account form of equivalence value is also a lot, and the present invention preferably calculates according to following formula: T3 standard time=T1+delay+ (T3-T2) constantly.
Step S205: master clock equivalence value and the synchronous Ethernet clock current count value of T3 are carried out summation operation, adjust clock output according to the summation operation result.
In step S202, started counting, when calculating the master clock equivalence value of T3, can stop counting the ethernet clock pulse to synchronous Ethernet clock.Master clock equivalence value with T3 adds the synchronous Ethernet clock current count value then, and this summed result has reflected the synchronised clock with master clock.Because clock signal sends through the form of pulse, obtain above-mentioned summed result after, the outgoing position with this result adjusts pulse obtains precision clock thus.
Present embodiment parses T1, T4 from synchronization message and time delay adjustment application response message;, synchronization message writes down the clock count T2 of local crystal oscillator when arriving;, writes down forward delay interval the clock count T3 of local crystal oscillator when proofreading and correct solicitation message; And enabling counting when sending solicitation message, through the master clock equivalence value that T1, T2, T3 and T4 calculate T3, export according to this equivalence value and synchronous Ethernet clock current count value sum adjustment clock.Compared with prior art; Present embodiment obtains the corresponding time from synchronization message and DELAY RESPONSE message after,, can obtain the master clock equivalence value of T3 through simple operation in conjunction with local crystal oscillator counting; Export clock according to the clock count sum adjustment of equivalence value and synchronous ethernet then; Thereby realized clock synchronization, owing to avoided loaded down with trivial details calculating, the convergence rate of clock synchronization is accelerated.And present embodiment utilizes existing synchronous ethernet that clock is provided, and does not need to build in advance a large amount of gps antennas and indoor forwarding unit, adopts common crystals equipment, has saved the GPS of operator deployment cost, thereby has reduced cost.In addition, present embodiment utilizes synchronous ethernet and does not adopt GPS, has the place of network can transmit clock, and the clock synchronization process no longer receives weather effect, has solved under the harsh weather situation between system base-station step-out easily, the problem of high cutting off rate occurred.
T2, T3 write down through the clock count to local crystal oscillator to obtain in the foregoing description; In practical application; Because there is frequency difference in local crystal oscillator usually and between the synchronous ethernet recovered clock, and is more accurate in order to obtain the synchronised clock result, need compensate T2, T3; The mode of compensation is to calculate the frequency difference coefficient earlier, utilizes this frequency difference coefficient to revise as the former T2 of adjustment factor pair, T3.The frequency difference coefficient calculates according to following formula:
coeff_freq＝(T1
cur-T1
prev)/(T2
cur-T2
prev)
In the formula: coeff_freq is the frequency difference coefficient, T1
Cur, T2
CurBe current T1 that obtains and T2, T1
Prev, T2
PrevBe T1 and the T2 that last time obtained.Calculate and be multiplied by T2 respectively with this coefficient behind the frequency difference coefficient and T3 can realize the correction to T2, T3.Need to prove: normal conditions should all be revised T2 and T3, but only to wherein any one is adjusted and does not also hinder goal of the invention of the present invention.
After the foregoing description calculates frequency difference coefficient coeff_freq and transmission delay delay; Can directly be used to calculate T3 master clock equivalence value constantly, but in practical application, the present invention preferably carries out Filtering Processing to above-mentioned two amounts; So that level and smooth exceptional value, the temperature drift of compensation crystal oscillator.
The foregoing description is proofreaied and correct the unqualified time interval between the solicitation message in synchronization message that receives the clock equipment transmission and forward delay interval, and even now does not hinder the realization of goal of the invention of the present invention.But; In actual application; In view of the problem of implementation of base station-side hardware and the data-handling capacity of clock equipment, difficulty accomplishes after receiving synchronization message, to send solicitation message at once, and there is delay in the two usually; Even phase sequence seamless connection before and after two operations also may not be more accurate for the calculating of synchronised clock.Therefore, the present invention preferably sets a timer, and this timer starts when receiving the synchronization message of clock equipment transmission, and when the Preset Time of timer arrived, base station side was proofreaied and correct solicitation message to the clock equipment forward delay interval.The Preset Time here can rule of thumb be set, and also can set according to the indication of clock equipment.Clock equipment is according to the data-handling capacity of self; To sending Desired Min Tx Interval delay_req_interval (M) from clock; The DELAY RESPONSE message delay_resp that this delay_req_interval value is sent through clock equipment arrives from clockwork; At interval send adjustment according to this transmission from clockwork when the next transmission delay solicitation message, the Preset Time of timer is arranged on 2
Delay_req_intervalTo 2
Delay_req_interval+1Within the scope.
In order to be illustrated more clearly in time delay method for synchronous of the present invention, describe with an instantiation below.Referring to accompanying drawing 3 and Fig. 4, Fig. 3 shows the flow chart of this instance, and Fig. 4 shows the hardware module structure chart of this instance.The clock synchronization process of this instance specifically comprises:
Step S301: initialization PHY and PTP protocol process module.PHY refers to physical layer, and the bottom of OSI refers to the chip with the external signal interface here.
Step S302:PHY extracts synchronised clock from synchronous ethernet, and through PLL module (PhaseLocked Loop, phase-locked loop) the Ethernet synchronised clock that extracts is outputed to FPGA.
Whether step S303:PHY detects synchronization message Sync and arrives.
Step S304: if detect Sync message, the clock count T2 that then by PHY local crystal oscillator is produced is inserted into the extended field of Sync message packet, the message that is equipped with the T2 timestamp is submitted to the PTP protocol process module of CPU; When detecting Sync message, start timer.CUP is operation PTP agreement, to the functional unit that the PTP agreement is handled, this unit comprises a plurality of functional layers, the PTP protocol process module is the sub-module in the CPU.
Step S305:PTP protocol process module parses T1 and the laggard row cache of T2, and calculates t_ms and frequency difference coefficient coeff_freq, utilizes frequency difference coefficient correction T2.T_ms representes that master clock arrives the time delay from clock, t_ms=T2-T1: frequency difference coefficient coeff_freq=(T1
Cur-T1
Prev)/(T2
Cur-T2
Prev), T2 multiply by result behind the frequency difference coefficient as new T2 buffer memory.
Step S306: whether the Preset Time of judging timer arrives, if arrival, then execution in step S307;
Step S307:PHY calls the call back function forward delay interval that is registered to network driver and proofreaies and correct solicitation message delay_req; PHY produces interrupt notification FPGA when sending delay_req message, by FPGA synchronous Ethernet clock is counted.
After step S308:delay_req message is sent and accomplished, obtain to send the transmitting time T3 of delay_req message from the clock count that local crystal oscillator produces, T3 is delivered to the PTP protocol process module through call back function.
Step S309:PHY passes to the PTP protocol process module after detecting the time-delay calibration response message delay_resp message of master clock, from response message, parses the time T 4 that master clock receives delay_req message by this module;
Step S310:PTP protocol process module calculates t_sm according to T3 and T4, utilizes t_ms, t_sm to calculate propagation delay time delay and the corresponding constantly master clock equivalence value of T3.T_sm representes the time delay from the clock to the master clock, t_sm=T4-T3; T3 master clock equivalence value=T1+delay+ (T3-T2) constantly.Also can proofread and correct in this step T3.
Step S311: the T3 that calculates master clock equivalence value constantly is configured to FPGA, promptly is setup time: T1+ (T3-T2) * coeff_freq+Delay to FPGA;
Step S312: stop the FGPA counting, note the t_fpga of this moment, the T3 equivalence value that is configured to FGPA is added this count value t_fpga, the result after the addition is as the benchmark of 1pps output time.
Describe method embodiment of the present invention above in detail, correspondingly, the present invention also provides a kind of system of clock synchronization.Referring to accompanying drawing 4, native system embodiment 400 comprises: first acquiring unit 401, first record cell 402, second record cell 403, clock count unit 404, second acquisition unit 405, first computing unit 406 and adjustment unit 407, wherein:
Said first acquiring unit 401 is used for after the synchronization message that receives the clock equipment transmission, resolving synchronization message, obtains the synchronization message transmitting time T1 that synchronization message comprises;
Said first record cell 402, the clock count T2 of local crystal oscillator when being used to write down synchronization message arrival;
Said second record cell 403 is used at the clock count T3 that when the clock equipment forward delay interval is proofreaied and correct solicitation message, writes down local crystal oscillator;
Said clock count unit 404 is used for when the clock equipment forward delay interval is proofreaied and correct solicitation message, starting the counting to synchronous Ethernet clock;
Said second acquisition unit 405 is used for resolution response message after receive time delay is proofreaied and correct the application response message, obtains the clock equipment that response message comprises and receives the time T 4 that solicitation message is proofreaied and correct in time-delay;
Said first computing unit 406 is used for according to T1, T2, T3 and T4 calculated transmission delay, calculates the master clock equivalence value of T3 according to T1, T2, T3 and transmission delay;
Said adjustment unit 407 is used for the summation adjustment clock output according to master clock equivalence value and the synchronous Ethernet clock current count value of T3.
The course of work of native system embodiment is: first acquiring unit 401 resolves and obtains the synchronization message transmitting time T1 that this synchronization message comprises after the synchronization message that receives the clock equipment transmission; The clock count T2 of local crystal oscillator when first record cell, 402 record synchronization messages arrive; When the clock equipment forward delay interval is proofreaied and correct solicitation message,, and trigger the counting that clock count unit 404 starts synchronous Ethernet clock then by the clock count T3 of the local crystal oscillator of second record cell, 403 records; After receive time delay is proofreaied and correct the application response message, resolve and obtain the clock equipment that this response message comprises by second acquisition unit 405 and receive the time T 4 that solicitation message is proofreaied and correct in time-delay; Next, first computing unit 406 calculates the master clock equivalence value of T3 according to T1, T2, T3 and T4 calculated transmission delay according to T1, T2, T3 and transmission delay; Adjustment unit 407 is according to the summation adjustment clock output of master clock equivalence value and the synchronous Ethernet clock current count value of T3.
Native system embodiment parses T1, T4 from synchronization message and time delay adjustment application response message;, synchronization message writes down the clock count T2 of local crystal oscillator when arriving;, writes down forward delay interval the clock count T3 of local crystal oscillator when proofreading and correct solicitation message; And enabling counting when sending solicitation message, through the master clock equivalence value that T1, T2, T3 and T4 calculate T3, export according to this equivalence value and synchronous Ethernet clock current count value sum adjustment clock.Compared with prior art; Native system embodiment obtains the corresponding time from synchronization message and DELAY RESPONSE message after,, can obtain the master clock equivalence value of T3 through simple operation in conjunction with local crystal oscillator counting; Export clock according to the clock count sum adjustment of equivalence value and synchronous ethernet then; Thereby realized clock synchronization, owing to avoided loaded down with trivial details calculating, the convergence rate of clock synchronization is accelerated.And present embodiment utilizes existing synchronous ethernet that clock is provided, and does not need to build in advance a large amount of gps antennas and indoor forwarding unit, adopts common crystals equipment, has saved the GPS of operator deployment cost, thereby has reduced cost.In addition, present embodiment utilizes synchronous ethernet and does not adopt GPS, has the place of network can transmit clock, and the clock synchronization process no longer receives weather effect, has solved under the harsh weather situation between system base-station step-out easily, the problem of high cutting off rate occurred.
First computing unit of said system embodiment can calculate according to following mode: deduct T1 and T3 sum with T2 and T4 sum, with subtract each other the result divided by 2 to obtain transmission delay; The difference that deducts T3 and T2 with T1 and transmission delay sum is to obtain the master clock equivalence value of T3.
Said system embodiment can also comprise second computing unit and amending unit, and second computing unit is used for calculating the frequency difference coefficient according to adjacent twice T1 and T2; Said amending unit is used for the frequency difference coefficient multiply by T2 and/or T3 respectively revising T2 and/or T3, said second computing unit with the difference of adjacent twice T1 divided by the difference of adjacent twice T2 with acquisition frequency difference coefficient.Can realize the correction to T2, T3 through these two unit, the frequency difference between compensation synchronous ethernet recovered clock and the local crystal oscillator helps realizing more accurately clock synchronization.
Said system embodiment can also comprise timer, and this timer starts when receiving the synchronization message of clock equipment transmission, when timer reaches Preset Time, proofreaies and correct solicitation message to the clock equipment forward delay interval.The general span of the Preset Time here is 2
MTo 2
M+1, said M is that clock equipment is proofreaied and correct the solicitation message Desired Min Tx Interval according to the time-delay of its data disposal ability indication.Can regulate the interval that receives between synchronization message and the forward delay interval correction solicitation message through this timer, satisfy the needs of practical application.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being done, is equal to replacement, improvement etc., all should be included within the protection range of invention.
Claims (10)
1. a clock synchronizing method is characterized in that, this method comprises:
Receive the synchronization message that clock equipment is sent, resolve synchronization message, obtain the synchronization message transmitting time T1 that synchronization message comprises; The clock count T2 of local crystal oscillator when the record synchronization message arrives;
Proofread and correct solicitation message to the clock equipment forward delay interval, the clock count T3 of local crystal oscillator when record sends this application message, and start counting to synchronous Ethernet clock;
Receive time-delay and proofread and correct the application response message, resolution response message is obtained the clock equipment that response message comprises and is received the time T 4 that solicitation message is proofreaied and correct in time-delay;
According to T1, T2, T3 and T4 calculated transmission delay, calculate the master clock equivalence value of T3 according to T1, T2, T3 and transmission delay;
The master clock equivalence value of T3 and current count value to synchronous Ethernet clock are carried out summation operation, adjust clock output according to the summation operation result.
2. method according to claim 1 is characterized in that, specifically comprises according to T1, T2, T3 and T4 calculated transmission delay: deduct T1 and T3 sum with T2 and T4 sum, with subtract each other the result divided by 2 to obtain transmission delay; The master clock equivalence value that calculates T3 according to T1, T2, T3 and transmission delay specifically comprises: the difference that adds T3 and T2 with T1 and transmission delay sum is to obtain the master clock equivalence value of T3.
3. method according to claim 1; It is characterized in that; Calculate the frequency difference coefficient according to adjacent twice T1 and T2; Multiply by T2 and/or T3 respectively revising T2 and/or T3 with this frequency difference coefficient, saidly calculate the frequency difference coefficient according to adjacent twice T1 and T2 and specifically comprise: with the difference of adjacent twice T1 divided by the difference of adjacent twice T2 with acquisition frequency difference coefficient.
4. according to any one described method in the claim 1 to 3, it is characterized in that, when receiving the synchronization message of clock equipment transmission, start timer, when timer reaches Preset Time, proofread and correct solicitation message to the clock equipment forward delay interval.
5. method according to claim 4 is characterized in that, said Preset Time scope is 2
MTo 2
M+1, said M is that clock equipment is proofreaied and correct the solicitation message Desired Min Tx Interval according to the time-delay of its data disposal ability indication.
6. a clock system is characterized in that, this system comprises: first acquiring unit, first record cell, second record cell, clock count unit, second acquisition unit, first computing unit and adjustment unit, wherein:
Said first acquiring unit is used for after the synchronization message that receives the clock equipment transmission, resolving synchronization message, obtains the synchronization message transmitting time T1 that synchronization message comprises;
Said first record cell, the clock count T2 of local crystal oscillator when being used to write down synchronization message arrival;
Said second record cell is used at the clock count T3 that when the clock equipment forward delay interval is proofreaied and correct solicitation message, writes down local crystal oscillator;
Said clock count unit is used for when the clock equipment forward delay interval is proofreaied and correct solicitation message, starting the counting to synchronous Ethernet clock;
Said second acquisition unit is used for resolution response message after receive time delay is proofreaied and correct the application response message, obtains the clock equipment that response message comprises and receives the time T 4 that solicitation message is proofreaied and correct in time-delay;
Said first computing unit is used for according to T1, T2, T3 and T4 calculated transmission delay, calculates the master clock equivalence value of T3 according to T1, T2, T3 and transmission delay;
Said adjustment unit is used for exporting with the current count value sum adjustment clock to synchronous Ethernet clock according to the master clock equivalence value of T3.
7. system according to claim 6 is characterized in that, said first computing unit deducts T1 and T3 sum with T2 and T4 sum, with subtract each other the result divided by 2 to obtain transmission delay; The difference that adds T3 and T2 with T1 and transmission delay sum is to obtain the master clock equivalence value of T3.
8. system according to claim 6 is characterized in that said system also comprises second computing unit and amending unit, and second computing unit is used for calculating the frequency difference coefficient according to adjacent twice T1 and T2; Said amending unit is used for the frequency difference coefficient multiply by T2 and/or T3 respectively revising T2 and/or T3, said second computing unit with the difference of adjacent twice T1 divided by the difference of adjacent twice T2 with acquisition frequency difference coefficient.
9. according to any one described system in the claim 6 to 8; It is characterized in that; Said system also comprises timer, and this timer starts when receiving the synchronization message of clock equipment transmission, when timer reaches Preset Time, proofreaies and correct solicitation message to the clock equipment forward delay interval.
10. system according to claim 9 is characterized in that, the scope of said Preset Time is 2
MTo 2
M+1, said M is that clock equipment is proofreaied and correct the solicitation message Desired Min Tx Interval according to the time-delay of its data disposal ability indication.
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