CN102522402A - On-chip transformer structure of novel substrate shielding layer - Google Patents

Abstract

The invention relates to an on-chip transformer structure of a novel substrate shielding layer. The structure comprises an on-chip transformer. Multilayer substrate shielding layers are arranged right below the on-chip transformer. The substrate shielding layer is formed by a rectangular metal strip and a plurality of metal gate strips with a same shape. The metal gate strips are vertical to the rectangular metal strip. The metal gate strips are parallelly arranged with an equal interval. By using the on-chip transformer structure of the novel substrate shielding layer of the invention, good substrate isolation can be realized; substrate loss can be reduced and a capacitor function can be realized through the substrate shielding layers.

Description

A Novel On-Chip Transformer Structure with Substrate Shielding Layer

technical field

The invention belongs to the field of microwave technology, and relates to a novel on-chip transformer structure of a substrate shielding layer.

Background technique

In recent years, research on the possibility of applying CMOS technology to radio frequency technology has increased a lot, especially deep submicron CMOS technology has been able to compete with traditional GaAs microdevices in some fields below 10GHz, which undoubtedly promotes development of CMOS circuits. Using CMOS standard technology to realize the integration of digital, analog and some radio frequency parts on one chip can not only greatly reduce the manufacturing cost, but also realize various functions. This also caters to the rapid development of the global communication market, and the wireless communication system requires reducing chip size, reducing production costs and shortening the R&D cycle. Therefore, in recent years, microwave monolithic integrated circuits used in communication systems have achieved unprecedented rapid development, and transformers, as extremely important passive devices in RFICs and MMICs, are usually used in low-noise amplifiers, voltage-controlled oscillators, dual In circuits such as balanced mixers and power amplifiers, impedance matching, differential and single-ended signal conversion, AC coupling and increased bandwidth can be achieved.

Unlike digital ICs and low-frequency circuits, RF ICs make extensive use of passive components. Due to the limitations of the process, the performance of integrated passive components is much lower than that of discrete components, and for radio frequency integrated circuits, circuit performance is largely limited by passive components. Therefore, if the process allows, it is particularly important for radio frequency integrated circuits to improve the performance of integrated passive components through size or layout design.

Especially in recent decades, the operating voltage of digital integrated circuits has been decreasing according to Moore's law, which limits the operating voltage of analog and radio frequency circuits. Some people also use multiple operating voltage systems to alleviate this problem, but this will increase the power consumption and complexity of the circuit. Therefore, in order to adapt to today's low-voltage working environment, the on-chip transformer based on the magnetic field coupling between windings plays an increasingly important role in the system on chip, and its role in the RF front-end circuit is even more irreplaceable.

The application of on-chip transformers can increase the compactness of RF circuits and achieve high circuit performance. Transformers are effective for impedance matching, stability, and DC biasing. Different from the traditional RF circuit with single-ended structure, the circuit with differential structure can make good use of the advantages of on-chip transformer coupling, and can achieve 3dB higher output power than the single-ended structure with the same area. Due to its own resistance, coupling coefficient and inherent impedance, the transformer basically does not require additional structures to improve stability. Matching with a transformer can simplify the circuit structure, and the bias and matching can be directly performed through the transformer without additional choke inductance.

However, as the frequency of radio frequency communication continues to increase, the conductive silicon-based substrate of the on-chip transformer will introduce more and more parasitic coupling phenomena. The quality factor of the on-chip transformer realized by standard CMOS process is low, generally below 10. This is caused by various non-ideal factors in the on-chip devices, including the loss caused by the limited conductivity of the microstrip line. At high frequencies, this loss is more serious due to the skin effect and other magnetic field effects; The loss caused by the electromagnetic field interaction between the non-insulated substrate and the microstrip line; the parasitic capacitance between the metal layer and the substrate and the fringe capacitance between the metal lines.

Similar to the on-chip inductor, in order to reduce the influence of the substrate, the thickness of the oxide layer between the transformer and the substrate can be increased, a lightly doped substrate or an insulating substrate can be used (SOI process or the substrate under the transformer can be hollowed out separately) and filled with insulating material). These processes are not compatible with the standard CMOS process, which will increase the cost. A better way is to improve performance by optimizing the on-chip transformer with the support of standard CMOS technology, and use the bottom metal ground isolation layer under the transformer to isolate the transformer from the substrate and reduce substrate loss.

Contents of the invention

In order to overcome the influence of the substrate effect on the on-chip transformer, the object of the present invention is to provide a novel on-chip transformer structure of the substrate shielding layer.

The technical solution adopted by the present invention to solve technical problems:

An on-chip transformer structure of a novel substrate shielding layer includes an on-chip transformer, and a multi-layer substrate shielding layer is arranged directly below the on-chip transformer; the substrate shielding layer is composed of a rectangular metal strip and a plurality of metal grids with the same shape Composed of strips, the metal grid strips are arranged vertically to the rectangular metal strips, and the metal grid strips are arranged in parallel at equal intervals.

Preferably, the substrate shielding layer is one layer.

Beneficial effects of the present invention:

The on-chip transformer structure of the novel substrate shielding layer of the invention can realize better substrate isolation, reduce substrate loss, and realize capacitance function through multiple substrate shielding layers.

Description of drawings

Fig. 1 is a schematic diagram of the novel substrate shielding layer of the present invention.

Fig. 2 is a schematic perspective view of an on-chip transformer using the first layer of metal (M1) as a shielding layer according to the present invention.

Fig. 3 is a schematic cross-sectional view of the present invention using the first layer of metal (M1) and the second layer of metal (M2) as the shielding layer to realize the capacitive function.

Fig. 4 is a schematic cross-sectional view of the present invention using the first layer of metal (M1), the second layer of metal (M2) and the third layer of metal (M3) as shielding layers to realize the capacitive function.

Detailed ways

The novel substrate shielding layer of the present invention may be multi-layered, and preferably, the substrate shielding layer is one layer. As shown in Fig. 1 and Fig. 2, the present invention includes an on-chip transformer, and a substrate shielding layer is arranged directly below the on-chip transformer; the substrate shielding layer is composed of a rectangular metal strip and a plurality of metal grid strips with the same shape , the metal grid strips are arranged vertically to the rectangular metal strips, and the metal grid strips are arranged in parallel at equal intervals. The invention can effectively realize the isolation between the on-chip transformer and the substrate, so that the on-chip transformer magnetic field can be isolated from the substrate, avoiding eddy current loss in the isolation layer, reducing the substrate loss, and reducing the impact on adjacent devices. signal crosstalk.

FIG. 2 is a perspective view of an on-chip inductor using the first layer of metal (M1) as a shielding layer in the present invention. The radio frequency signal comes out from Port 1 (Port1) and Port 3 (Port3) of the primary coil of the transformer, and then comes out from Port 2 (Port2) and Port 4 (Port4) of the secondary coil after being coupled by a magnetic field. The isolation between the transformer and the substrate is realized through the shielding layer (such as the first layer of metal M1), which can avoid the eddy current loss in the isolation layer and reduce the substrate loss.

The present invention can realize the capacitive function through multiple substrate shielding layers. FIG. 3 is a schematic cross-sectional view of the present invention using the first layer of metal (M1) and the second layer of metal (M2) as shielding layers to realize the capacitive function. The specific implementation method is as follows: the shielding layer 2 (realized by the second layer of metal M2) is connected to the power supply terminal through a connection, and the shielding layer 1 (realized by the first layer of metal M1) is grounded through a connection. In this way, the capacitance C1 between the second layer metal (M2) and the substrate, the capacitance C2 between the first layer metal (M1) and the second layer metal (M2) can be formed, and the total capacitance C can be obtained as capacitance C1 and Parallel connection of capacitor C2.

If the capacitance value obtained by the two-layer substrate shielding layer shown in Figure 3 is not large enough, more layers of metal can be used to realize the shielding layer. For example, Figure 4 shows that the present invention utilizes the first layer of metal (M1), the second The layer metal (M2) and the third layer metal (M3) are used as the shielding layer to realize the capacitance function. The specific implementation method is as follows: the shielding layer 2 (the second layer of metal M2) is connected to the power supply terminal through a wire, and the shielding layer 1 (the first layer of metal M1) and the shielding layer 3 (the third layer of metal M3) are respectively grounded. In this way, the capacitance C1 between the second layer metal (M2) and the substrate, the capacitance C2 between the first layer metal (M1) and the second layer metal (M2), and the capacitance C2 between the third layer metal (M3) and the first layer metal (M3) can be obtained. The capacitance C2 between the two layers of metal (M2), the total capacitance C obtained is the parallel connection of the capacitance C1 and the capacitance C2.

Claims (2)

1. the on-chip transformer structure of a novel substrate shield layer is characterized in that: comprise on-chip transformer, under on-chip transformer, be provided with the MULTILAYER SUBSTRATE screen; Described substrate shield layer is made up of with the many identical metal grizzly bars of shape the rectangular metal bar, and described metal grizzly bar is provided with the rectangular metal bar is vertical, equidistantly laterally arranges between the metal grizzly bar.

2. on-chip transformer structure according to claim 1 is characterized in that: described substrate shield layer is one deck.

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