[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN102437063A - 一种液态凸点倒装芯片的制作方法 - Google Patents

一种液态凸点倒装芯片的制作方法 Download PDF

Info

Publication number
CN102437063A
CN102437063A CN201110382009XA CN201110382009A CN102437063A CN 102437063 A CN102437063 A CN 102437063A CN 201110382009X A CN201110382009X A CN 201110382009XA CN 201110382009 A CN201110382009 A CN 201110382009A CN 102437063 A CN102437063 A CN 102437063A
Authority
CN
China
Prior art keywords
chip
liquid
dykes
dams
salient point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201110382009XA
Other languages
English (en)
Inventor
金鹏
李宁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guo feng
Original Assignee
Peking University Shenzhen Graduate School
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Peking University Shenzhen Graduate School filed Critical Peking University Shenzhen Graduate School
Priority to CN201110382009XA priority Critical patent/CN102437063A/zh
Publication of CN102437063A publication Critical patent/CN102437063A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125Reinforcing structures
    • H01L2224/10126Bump collar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • H01L2224/1148Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849Reflowing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13012Shape in top view
    • H01L2224/13014Shape in top view being circular or elliptic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13105Gallium [Ga] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81141Guiding structures both on and outside the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

本发明涉及一种液态凸点倒装芯片的制作方法,该方法包括:在芯片电极周围生长堤坝;在堤坝围绕的区域内形成常温液态Ga-In凸点;在一定的温度和压力下将芯片凸点与布线板电极精确对位压接;芯片与布线板之间填充底充胶并固化。本发明由于堤坝圈定了凸点的范围,避免了传统倒装芯片结构在焊料熔化时相邻凸点容易出现短路的现象;不需要高温环境,能有效避免因高温而造成的器件失效现象;常温下凸点为液态形式,具有流动张力,产生应力小,有较高的电气和机械性能,不会造成机械损伤;液态凸点与电极接触良好,有很高的导电、导热能力。

Description

一种液态凸点倒装芯片的制作方法
技术领域
本发明涉及一种倒装芯片封装的方法,更具体地涉及在芯片电极周围生成堤坝,在其界定区域内用常温液态合金Ga-In形成凸点,在一定温度和压力下压接到布线板电极上,进行芯片下填充并固化的倒装芯片制作方法。 
背景技术
倒装芯片工艺是指在芯片的连接焊盘上形成凸点并直接连接到PCB基板的工艺。其技术有封装密度高、电热性能良好、可靠性好、成本低等优点。近年来,随着电子设备的小型化,特别是便携通信系统的普及,对高密度封装的要求越来越迫切,从而采用各类凸点的倒装芯片技术将大有用武之地。 
图2所示为传统倒装芯片凸点的结构,其组成包括:芯片1、钝化层2、铝焊盘3、凸点下金属层UBM(Under-Bump Metallurgy)4、凸点5。凸点5即是在芯片铝电极焊区上形成的凸起电极,通过该电极使芯片实装在PCB等封装基板上。为达到凸点金属5与铝焊盘3及钝化层2良好的粘附性,又要防止凸点金属5与铝焊盘3生成不希望有的金属间化合物,一般应先在凸点金属下制备有粘附层、扩散阻挡层和导电层的多层金属化层4。典型的粘附金属有Cr、Ti、Ni、TiN等,扩散阻挡层金属有W、Mo、Ni等,导电金属则常用Au、Cu、Pb/Sn等,这种多种金属化层常采用溅射、蒸发、化学镀、电镀等方法来完成。凸点金属5的制作材料多为Au、Cu、Pb/Sn、In或它们的组合。形成凸点5的方法主要有电镀法、化学镀法、钉头凸点形成法、模板印刷焊料法及热注射焊料法等。在这些凸点中,Pb/Sn焊料凸点因具有突出优点而备受重视。由于它是半球形,在倒装焊时随着焊料熔化可自对准定位,能控制Pb/Sn焊料的塌陷程度及凸点高度,所以又称为可控塌陷芯片连接技术(C4)。金凸点主要用于LCD驱动元件的TAB(tape automated bonding)和COG(chip on glass)实装,前者通过金凸点与电镀锡的引脚实现金属间键合,后者通过各向异性导电膜(ACF)实现Au凸点与LCD的ITO膜的连接。传统的倒装芯片结构在焊料熔化,相邻凸点键合时,彼此容易出现短路现象,因此凸点的大小及间距受到限制。 
目前,柔性封装以其配线密度高、配线空间限制少、可折叠、灵活度高等优点广泛用在空间狭小、可移动、可折叠等应用领域。随着产品的步步优化,对器件的电气和机械性能的要求也越来越高。液态凸点的出现将更好的保证器件电气和机械性能的可靠性。由于封装材料和芯片之间热膨胀系数的不匹配,容易导致外界温度变化时的应力释放对芯片造成损伤。液态凸点的应用,减小封装部件在温度变化的过程中的内应力,从而减小芯片的损伤。 
发明内容
为解决上述问题,本发明的目的是提供一种倒装芯片方法,该方法可以有效的解决凸点键合时容易产生短路现象的问题,并实现较小的压点节距。 
本发明的另一个目的是为倒装芯片的凸点提供一种新型材料,该金属材料在常温下是液态,其流动张力能够保证可靠的电气及机械连接,产生应力小且不会造成机械损伤。在倒装片压接互联的过程中不需要很高温度,从而避免芯片受高温损伤。 
为达到上述目的,本发明通过下面的实施方式实现。 
本发明的实施方式包括:用在芯片上生长围绕电极的堤坝,在堤坝围绕的区域内形成常温液态合金Ga-In凸点,合金成分的摩尔比例范围为In 8%-16%,Ga 92%-84%,该成分合金的熔点范围为15℃-20℃,在常温下为液态。在低于所用成分的Ga-In熔点温度的条件下适当加热,将芯片凸点与布线板电极精确对 位,施以一定压力,实现其粘附。芯片与布线板之间填充底充胶并固化。 
附图说明
图1为Ga-In二元相图; 
图2为传统倒装芯片凸点的结构示意图; 
图3为本发明的倒装芯片实施方法的流程图; 
图4为布有电极的芯片的剖视图; 
图5为在芯片上生成堤坝的剖视图和堤坝分布的俯视图; 
图6为在堤坝围绕的区域内生成常温液态Ga-In凸点的剖视图; 
图7为芯片凸点与布线板电极对位压接的剖视图; 
图8为芯片与布线板之间填充底充胶并固化的剖视图。 
具体实施方式
下面结合附图对本发明的技术方案作进一步描述。 
图1为Ga-In二元相图,本发明所用为AB段相图曲线。 
图3为本发明的倒装芯片实施方法的流程图。如图3所示,本发明的倒装芯片实施方法包括:在芯片电极周围生成堤坝(S11),在堤坝围绕的范围形成常温液态Ga-In凸点(S12),将芯片凸点与布线板电极精确对位压接(S13),芯片与布线板之间填充底充胶并固化(S14)。 
图4为芯片6上布有电极7的剖视图,电极的节距可以最低达到25-50μm。 
图5左图为在芯片6上生成堤坝8(S11)的剖视图,堤坝8的制作方法有蒸发沉积、电镀、模板印刷等工艺,堤坝8的制作材料有硅胶、AB胶、黑胶等。这些高分子材料的优点在于它们有很强的粘附能力。堤坝8将作为接下来倒装芯片制作过程中凸点材料的阻挡装置,用于界定凸点9的成型区域。其中,堤 坝8的宽度和高度以及堤坝8的间距可以根据芯片电极7而改变。图5右图为芯片上堤坝8分布的俯视图。堤坝8的平面形状可以是圆形、方形、多边形等。 
图6为在堤坝围绕的区域内生成常温液态Ga-In凸点9(S12)的剖视图。Ga-In合金成分的摩尔比例范围为In 8%-16%,Ga 92%-84%,该成分合金的熔点范围为15℃-20℃,在常温下为液态。将常温液态Ga-In以相同剂量滴灌到堤坝围绕的区域,形成凸点。Ga-In易被氧化,因此S12、S14中任一步骤都要在保护气体中进行操作。压接过程为了避免产生气泡,所以S13要在真空条件下进行操作。 
图7为布线板10的电极11与芯片6的凸点9对位压接(S13)的剖视图。在低于所用成分的Ga-In熔点温度的条件下适当加热,此时凸点为固态。将芯片凸点9与布线板电极11精确对位,施以压力,实现其粘附,一个例子是对每个芯片施加2-10kg的压力,持续时间10-20秒。 
图8为芯片6与布线板10之间填充底充胶12并固化(S14)的剖视图。在堤坝与堤坝之间填充底充胶12,底充胶12的材料包括树脂、硅胶等,填充的方法有滴灌法、浇口注入、浸渍法等。随后进行固化,固化的方法有紫外光照射、加热等。 
以上内容是结合具体的实施方式对本发明所作的进一步详细说明,不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干简单推演或替换,都应当视为属于本发明的保护范围。 

Claims (9)

1.一种液态凸点倒装芯片的制作方法,其特征在于包括:在芯片上生长围绕电极的堤坝;在堤坝围绕的区域内形成常温液态Ga-In凸点;在一定温度和压力下将芯片凸点与布线板电极精确对位压接;芯片与布线板之间填充底充胶并固化,从而实现倒装芯片的封装。
2.如权利要求1所述的方法,其特征在于,在芯片上生长堤坝的方法包括:蒸发沉积、电镀、丝网印刷等,所述堤坝的制作材料是高分子材料,包括硅胶、AB胶、黑胶等。
3.如权利要求1所述的方法,其特征在于,所述堤坝的形状包括圆形、方形和多边形等。
4.如权利要求1所述的方法,其特征在于,生成凸点下金属层UBM的方法包括:溅射、蒸发、化学镀、电镀等。
5.如权利要求1所述的方法,其特征在于,图1为Ga-In二元相图,如图所示,Ga-In中两种金属成分的摩尔比例范围为:In 8%16%,Ga 92%84%,该成分合金的熔点范围为15℃-20℃,在常温下为液态。
6.如权利要求1、5所述的方法,其特征在于,将常温液态Ga-In合金滴灌到堤坝围绕的范围内,形成常温液态凸点。
7.如权利要求1所述的方法,其特征在于,在低于所用成分的Ga-In熔点温度的条件下适当加热,此时凸点为固态,将芯片凸点与布线板电极精确对位,对每个芯片应力,实现其粘附,一个例子是2-10kg的压力,持续时间5-20秒。
8.如权利要求1所述的方法,其特征在于,进行芯片下填充,填充的物质有树脂、硅胶等。填充的方法包括:滴灌法、浇口注入、浸渍法等。随后进行固化,固化的方法包括:紫外光照射、加热等。
9.如权利要求7所述的方法,其特征在于,操作要在真空环境中进行。
CN201110382009XA 2011-11-25 2011-11-25 一种液态凸点倒装芯片的制作方法 Pending CN102437063A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201110382009XA CN102437063A (zh) 2011-11-25 2011-11-25 一种液态凸点倒装芯片的制作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110382009XA CN102437063A (zh) 2011-11-25 2011-11-25 一种液态凸点倒装芯片的制作方法

Publications (1)

Publication Number Publication Date
CN102437063A true CN102437063A (zh) 2012-05-02

Family

ID=45985057

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110382009XA Pending CN102437063A (zh) 2011-11-25 2011-11-25 一种液态凸点倒装芯片的制作方法

Country Status (1)

Country Link
CN (1) CN102437063A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336829A (zh) * 2015-09-28 2016-02-17 厦门市三安光电科技有限公司 倒装发光二极管结构及其制作方法
CN105489727A (zh) * 2016-01-18 2016-04-13 厦门市三安光电科技有限公司 倒装led芯片的键合电极结构及制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000088883A (ja) * 1998-09-09 2000-03-31 Micronics Japan Co Ltd 電子部品用電気的接続装置及びその製造方法
US20020100973A1 (en) * 2000-06-08 2002-08-01 Salman Akram Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same
CN101194373A (zh) * 2005-06-09 2008-06-04 飞利浦拉米尔德斯照明设备有限责任公司 移除半导体发光器件的生长基板的方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000088883A (ja) * 1998-09-09 2000-03-31 Micronics Japan Co Ltd 電子部品用電気的接続装置及びその製造方法
US20020100973A1 (en) * 2000-06-08 2002-08-01 Salman Akram Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same
CN101194373A (zh) * 2005-06-09 2008-06-04 飞利浦拉米尔德斯照明设备有限责任公司 移除半导体发光器件的生长基板的方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336829A (zh) * 2015-09-28 2016-02-17 厦门市三安光电科技有限公司 倒装发光二极管结构及其制作方法
WO2017054612A1 (zh) * 2015-09-28 2017-04-06 厦门市三安光电科技有限公司 倒装发光二极管结构及其制作方法
CN105336829B (zh) * 2015-09-28 2018-09-11 厦门市三安光电科技有限公司 倒装发光二极管结构及其制作方法
US10205057B2 (en) 2015-09-28 2019-02-12 Xiamen Sanan Optoelectronics Technology Co., Ltd. Flip-chip light emitting diode and fabrication method
CN105489727A (zh) * 2016-01-18 2016-04-13 厦门市三安光电科技有限公司 倒装led芯片的键合电极结构及制作方法
CN105489727B (zh) * 2016-01-18 2018-06-19 厦门市三安光电科技有限公司 倒装led芯片的键合电极结构及制作方法

Similar Documents

Publication Publication Date Title
JP5952523B2 (ja) 半導体素子およびフリップチップ相互接続構造を形成する方法
US7799607B2 (en) Process for forming bumps and solder bump
JP6013705B2 (ja) 部分パット上にバンプを有するフリップチップ相互接続構造を形成する半導体デバイスおよびその方法
US7537961B2 (en) Conductive resin composition, connection method between electrodes using the same, and electric connection method between electronic component and circuit substrate using the same
US20170098627A1 (en) Interconnect structures for fine pitch assembly of semiconductor structures
US20080165518A1 (en) Flip Clip Mounting Process And Bump-Forming Process Using Electrically-Conductive Particles
JP4401411B2 (ja) 半導体チップを備えた実装体およびその製造方法
EP1796156A1 (en) Flip chip mounting method and flip chip mounting element
JP5967489B2 (ja) 実装構造体
US20040235221A1 (en) Electronic device and method for manufacturing the same
CN101958298A (zh) 半导体器件及其制造方法
EP1830399A1 (en) Resin composition for flip-chip packaging and resin composition for forming bump
CN103098191B (zh) 电子元器件安装体、电子元器件及基板
US20090017582A1 (en) Method for manufacturing semiconductor device
KR102006637B1 (ko) 범프의 형성 방법 및 이를 포함하는 반도체 소자의 형성방법
CN102208358A (zh) 一种在基板上焊接倒装芯片的方法及封装器件
US20100167466A1 (en) Semiconductor package substrate with metal bumps
CN102543908A (zh) 倒装芯片封装件及其制造方法
CN102437063A (zh) 一种液态凸点倒装芯片的制作方法
CN107248539B (zh) 一种led封装工艺
JP2003100809A (ja) フリップチップ実装方法
TW201526199A (zh) 半導體封裝件及其製法
US7727805B2 (en) Reducing stress in a flip chip assembly
CN103107104A (zh) 一种倒装芯片的制作方法
CN100483699C (zh) 使用自傲互连材料的半导体器件封装

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
ASS Succession or assignment of patent right

Owner name: GUO FENG

Free format text: FORMER OWNER: SHENZHEN GRADUATE SCHOOL OF PEKING UNIVERSITY

Effective date: 20130107

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 518055 SHENZHEN, GUANGDONG PROVINCE TO: 511400 GUANGZHOU, GUANGDONG PROVINCE

TA01 Transfer of patent application right

Effective date of registration: 20130107

Address after: 511400 Guangdong city of Guangzhou province Panyu District agile Yahu in Building 1, No. 602

Applicant after: Guo Feng

Address before: 518055 Guangdong city in Shenzhen Province, Nanshan District City Xili Shenzhen University North Campus

Applicant before: Shenzhen Graduate School of Peking University

C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20120502