CN102420620A - Method and device for processing DC (Direct Current) leakage - Google Patents

Abstract

The invention discloses a method and device for processing DC (Direct Current) leakage. The method comprises the following steps of: obtaining receiving signals of an I path and a Q path in a period of time; respectively calculating even of signal amplitudes of the I path and the Q path in the period of time; and taking the even of the I path as a DC leakage rate of the I path, and the even of the Q path as a DC leakage rate of the Q path. The invention can be used for effectively removing the drifting of DC signals and is suitable for receivers of a TD-SCDMA (Time Division-Synchronization Code Division Multiple Access) system and a TD-LET (TD-SCDMA Long Term Evolution) system.

Description

A kind of processing method of direct current leakage and device

Technical field

The present invention relates to Wireless Telecom Equipment, particularly a kind of processing unit of direct current leakage.

Background technology

Modern wireless receiver; No matter be broadcast receiver or mobile TV machine; Almost without exception, what we saw is the circuit structure of a kind of being known as " superhet " formula: faint high frequency radio signal must just can remove the interference of other channel and obtain enough gains earlier through one-level or what mixting circuit; Required information is taken out in final completion demodulation.Every through single-conversion, the frequency of signal reduces, amplitude increases, and the interference of other channel and frequency range is then progressively filtered out.

This structure is generally adopted reason is arranged.It has been generally acknowledged that; The signal frequency that antenna receives is very high and channel width is very little; If directly leach required channel, the Q value of filter will be an astronomical figure, add the problem of high-frequency circuit at aspects such as gain, precision and stability; It is unpractical directly signal being carried out demodulation at high frequency, and present at least technical merit also can't satisfy this requirement.Carry out channel filtering again after using frequency mixer to move high-frequency signal to a much lower IF-FRE, amplify to conciliate and reconcile the difficulty that the high-frequency signal processing is run into of having determined; But introduced another serious problem again; So-called image frequency that Here it is is disturbed: when the absolute value of frequency and local oscillator (LO) the signal frequency difference of two signals equates still opposite in sign; They are symmetrically located at the both sides of local oscillation signal on frequency axis in other words, all will be shifted to same IF-FRE through these two signals after the mixing so.If one of them is a useful signal, another is an interference signal, and the frequency at interference signal place just is called image frequency so, and the interference phenomenon after the mixing of this process is commonly called image frequency and disturbs.Disturb in order to suppress image frequency, the method that generally adopts is to utilize the filter filtering image frequency composition of antenna back.Because this filter is operated in high frequency, its filter effect depends on the distance between image frequency frequency and the signal frequency, depends on the height of IF-FRE in other words but likewise.If IF-FRE is high, signal and image frequency apart from each other, the image frequency composition just receives bigger inhibition so; Otherwise if IF-FRE is lower, signal and image frequency are separated by not far, and the effect of filtering is just relatively poor.But then, because channel is chosen in intermediate frequency and carries out, based on same reason, higher IF-FRE is also higher to the requirement of channel selection filter.So image frequency suppresses to select to have formed a pair of contradiction with channel, and IF-FRE be selected to this key of balance to contradiction.In the higher application of ask for something, usually use twice or three frequency conversions obtain better compromise.

Rely on considerate IF-FRE to select and high-quality radio frequency (mirror image inhibition) and intermediate frequency (channel selection) filter; A well-designed superheterodyne receiver can reach very high sensitivity, selectivity and dynamic range, therefore becomes actual unique selection for a long time.

Someone feels dissatisfied to selecting IF-FRE and Filter Design mode.Greatly after super-heterodyne architecture occurs for many years, the someone has proposed a kind ofly to be set as local frequency identical with signal frequency, high-frequency signal is directly moved the receiver structure of zero frequency through frequency conversion.Compare with superheterodyne receiver, this be called as Direct Conversion (Direct-Conversion) or zero intermediate frequency (ZIF, structure Zero-IF) has two advantages at least: (1) IF-FRE is zero, does not have the mirror image interference problem; (2) channel is chosen in low frequency and carries out, and only needs to use low pass filter.Yet, possibly be to have run into failure repeatedly, our pioneers do not realize the ideal of zero intermediate frequency, in one very long period, this structure all nobody shows any interest in.Because the designer need utilize integrated circuit technique as far as possible, circuit element is made in chip internal, just improve the integrated level of circuit.

But for superheterodyne receiver, having two elements at least is up to the present can't be integrated into chips, Here it is its image frequency rejects trap and channel selection filter.Moreover, in order to improve selectivity, channel selects also possibly use some comparatively expensive device such as SAW (Surface Acoustic Wave, surface acoustic wave) filters.At this moment, the someone has expected zero intermediate frequency reciver again.We know that there is not the image frequency problem in zero intermediate frequency reciver (1); (2) as long as come selective channel with low pass filter, and the integrated technology of low pass filter is very ripe, even the difficulty of being integrated with also can realize with the electric capacity and the inductance of cheapness.With this 2 point, can only reach high integrated level with few sheet external component.

The introducing of 3G, 4G technology, in the face of the surging tide of personal mobile communication, the zero-if architecture glamour highlights, and the zero intermediate frequency architecture design becomes the problem of a technical research again for this reason, and people begin to attempt it is used in the mobile phone.

The operation principle of zero intermediate frequency reciver is the zero intermediate frequency signals I and the Q that produce two quadratures after high-frequency signal process pair of orthogonal frequency mixer (Quadrature Mixer) frequency conversion that receives; These two signals are amplified by LPF and amplitude limit subsequently; I/Q is respectively by ADC (Analogue-to-Digital Converter then; Analog to digital converter) sampling becomes digital signal, gives Base-Band Processing after the down-conversion.Fig. 1 is that receiver direct current leakage and mirror image produce sketch map, has illustrated the principle (sampling respectively after the quadrature demodulation) that zero intermediate frequency is handled among the figure, if ω _USB(perhaps ω _LSB) be that we hope the signal that obtains, the relative Q channel of I channel is because quadrature (90 degree skew), thereby can eliminate at ω _LSB(perhaps ω _USB) mirror image that is in.But because the I/Q channel amplitude is uneven and unbalance in phase makes mirror image effectively to eliminate; The existence of direct current offset causes dc shift serious, and a large amount of research and practice show that all direct current leakage (drift) becomes a practical difficult problem of restriction zero intermediate frequency reciver.

Describe in the face of dc shift (DC Offset) down.

The most basic problem of zero-if architecture is that signal is shifted to the direct current frequency range at the very start; Be easy to integratedly simultaneously though can save a lot of expensive elements, signal does not also have enough time to obtain enough gains just by very strong low-frequency disturbance and noise " pollution ".The caused dc shift of leakage that the problem that is widely known by the people most is a local oscillation signal.Owing in circuit, always there are some parasitic elements, can not accomplish between signal and the signal to isolate fully, always some signal can leak.In the wireless receiver of a reality, local oscillation signal can drain to the RF signal input end of frequency mixer, and then arrives reception antenna through the limited low noise amplifier of isolation.On this path, the signal that a part is leaked can be reflected and be mingled in the useful signal that receives, and comes back to the input of frequency mixer, appears at the direct current frequency range through frequency spectrum shift again.Local oscillation signal after this leakage and local oscillation signal self phenomenon of mixing mutually is called as " self-mixing ".We see, because the frequency input signal of zero intermediate frequency reciver is identical with the local oscillation signal frequency, except needed zero intermediate frequency signals, have also mixed a unwanted DC component or dc shift at the medium frequency output end of frequency mixer.In order to make mixting circuit have certain gain, the amplitude of local oscillation signal or power all can select greatlyyer usually, even passed through the significantly decay on leakage and the reflection path, the last dc shift that causes still can flood useful signal easily.

The caused drift of self-mixing is not invariable, and the size of the leakage signal that the variation of receiver surrounding environment can cause being reflected rises and falls, and shows as the time variation of dc shift.The reason that causes dc shift also has the not matching property of circuit element and inferior by chance non-linear.The direct current that leaks As time goes on intensity and direction also is in drifting state.

For this reason, the elimination to dc shift becomes problem of needing solution badly of engineers and technicians.At present, common way has 3 points:

First: Digital Signal Processing.

In order to eliminate dc shift more accurately and efficiently, the way that has adopted baseband digital signal to handle is in some designs carried out real-time measurement and dynamic compensation through special algorithm to drift value.For example in a TDMA (Time Division Multiple Access, time division multiple access) system, receiver is measured in the intervals of business and is stored the dc shift amount as a reference, from signal, deducts this reference quantity during work again.This method can be removed the low-frequency noise of various dc shifts and part effectively, but because the reference drift value when needing a no input signal, its application in non-time-sharing system is comparatively difficult.

Second: the help that system design can provide.

Contrast paging and these two systems of mobile communication, we see if when system design, can consider near the centre frequency of signal, to reserve some bandwidth with the convenient dc shift of eliminating, with the design of simplifying zero intermediate frequency reciver greatly.Certainly, this requires the extremely valuable GSM of frequency spectrum resource is gone a bit too far, but at standard (IEEE 802.11a) and TD-LTE (TD-SCDMA Long Term Evolution, the TD-SCDMA Long Term Evolution of WLAN; TD-SCDMA:Time Division Synchronized Code Division Multiple Access, TD SDMA inserts) in but become reality, carrier information is not transmitted at the center of frequency.

The the 3rd: low intermediate frequency receiver.

High Q value intermediate-frequency filter is disturbed, need not in the improvement of receiver structure and innovation, no image frequency, and this is a why attractive basic reason of zero intermediate frequency reciver.In order both to obtain the zero intermediate frequency advantage, the shortcoming of avoiding not only intermediate frequency now but also the receiver structure of so-called Low Medium Frequency (Low IF) and class zero intermediate frequency arranged.

In order to reduce the influence of the requirement of intermediate-frequency filter being avoided dc shift and low-frequency noise simultaneously again as far as possible, can consider intermediate frequency is chosen on the frequency of lower but non-zero Here it is so-called low intermediate frequency receiver.Of preamble, the direct result that reduces IF-FRE is to have strengthened the inhibition difficulty of image frequency.The way of radio-frequency filter filtering image frequency of utilizing high Q value also is not-so-practical obviously against designer's original intention simultaneously.Therefore low intermediate frequency receiver has generally adopted the image frequency rejection mixer and the multiphase filter of quadrature, and the two all is to utilize signal and mirror image to disturb through the phase difference that exists after the mixing to distinguish signal and interference.The inhibition degree of image frequency is very responsive to the amplitude and the phase matched situation of two quadrature channels, and this has influenced the performance of receiver to a certain extent;

If used by real it is thus clear that want ZIF receiver technology, the direct current leakage of ZIF receiver is a problem that must solve.Through the method for digital processing, the correction of in the limited hardware resource, accomplishing DCOFFSET becomes the focus of a research of industry.

The deficiency of prior art is: existing receiver leaks owing to can't well eliminate DC when adopting the ZIF scheme, and DC leaks direction and size in drift constantly, makes eliminating that DC leaks become complicated more.If for example TD-SCDMA adopts small base station to adopt the ZIF receiver structure, near the carrier subscriber the zero-frequency can't insert at all.Though 15KHz does not have signal in the TD-LTE zero-frequency; But the direct current leakage that amplitude is high causes system at FFT (Fast Fourier Transform; FFT) time the have to precision of scattering and disappearing signal of calibration; For example the TD-LTE system adopts MIMO (Multiple Input Multiple Output, multiple-input, multiple-output) system index when carrying out SDM (Space Division Multiplex, space division multiplexing) can descend many.Leak so the top priority of system when receiving signal will try every possible means to eliminate DC exactly, do not solve this problem yet prior art has scheme.

Summary of the invention

The technical problem that the present invention solved has been to provide a kind of processing method and device of direct current leakage, in order to eliminate the direct current leakage in the zero intermediate frequency reciver.

A kind of processing method of direct current leakage is provided in the embodiment of the invention, has comprised the steps:

Obtain the reception signal on interior I road of a period of time and Q road;

I road and the Q road signal amplitude of this section in the time asked for average respectively;

With the average on I road direct current leakage amount, with the average on Q road direct current leakage amount as the Q road as the I road.

A kind of processing unit of direct current leakage is provided in the embodiment of the invention, has comprised:

Acquisition module is used to obtain the reception signal on interior I road of a period of time and Q road;

The average module is used for I road and the Q road signal amplitude of this section in the time asked for average respectively;

Leak determination module, be used for, with the average on Q road direct current leakage amount as the Q road with the average on I road direct current leakage amount as the I road.

Beneficial effect of the present invention is following:

Can very effectively eliminate the drift of direct current signal, and be applicable to the receiver of TD-SCDMA and TD-LTE system.

Description of drawings

Fig. 1 is receiver direct current leakage and a mirror image generation sketch map in the background technology;

Fig. 2 is a zero intermediate frequency reciver sketch map in the embodiment of the invention;

Fig. 3 is the processing method implementing procedure sketch map of direct current leakage in the embodiment of the invention;

Fig. 4 is the processing unit structural representation of direct current leakage in the embodiment of the invention;

Fig. 5 has the backward signal buffer memory dc shift of delay process to eliminate the apparatus structure sketch map in the embodiment of the invention;

Fig. 6 eliminates the apparatus structure sketch map for the forward signal buffer memory dc shift of no delay process in the embodiment of the invention;

Fig. 7 is tone signal frequency spectrum map before and after the direct current leakage correction in the embodiment of the invention;

Fig. 8 is TD signal frequency spectrum map before and after the direct current leakage correction in the embodiment of the invention;

Fig. 9 is TD-LTE signal frequency spectrum map before and after the direct current leakage correction in the embodiment of the invention.

Embodiment

The inventor notices in the invention process:

In order to make the ZIF receiver can be really be adopted, at first just need analyze the mirror image of ZIF receiver and the reason of direct current leakage generation by system.Fig. 2 is the zero intermediate frequency reciver sketch map; LNA is low noise amplifier (Low Noise Amplifier) among Fig. 2; DDC is digital data converter (Digital Data Converter), and DPD is digital pre-distortion (Digital PreDistortion), is zero intermediate frequency signals carrying out ADC before handling among Fig. 2; I and q represent i/q signal respectively, and exemplary process such as Fig. 2 of ZIF receiver are illustrated as:

Nonideal quadrature demodulator receives radiofrequency signal afe_rx (t), and after ADC handled, before carrying out ZIF direct current offset corrected Calculation and revising, it was following to generate i/q signal respectively at the DPD feedback path:

$g_i=1+\frac{\mathrm{\α}}{2},$ $g_q=1-\frac{\mathrm{\α}}{2}$

Wherein, g is gain, Be phase error, the t express time, then, if local frequency equals rf frequency: f _LO=f _RF, the center frequency point of i/q signal just all is shifted to zero-frequency like this, Here it is so-called zero intermediate frequency framework.Then Q signal is following:

Desirable quadrature modulator, tentatively think phase error The same g of gain _i=g _q=g,

But for direct current leakage Δ d _i(t) and Δ d _q(t) owing to the analog link that is two passages of I/Q causes, can't pass through low pass filter filters out.Thereby make the signal I road and the Q road that receive that direct current leakage Δ d separately all arranged _i(t) and Δ d _q(t), can find out from following formula:

And when the signal power that receives is very low; The direct current power of leaking might not reduce a lot; The direct current power that can cause like this leaking can be big more a lot of than signal power, and service signal power is submerged in below the direct current signal power, makes that customer service can't proper communication.

For the TD-SCDMA system, the carrier subscriber that the existence of direct current leakage problem causes being in zero-frequency can't insert at all, and the signal quality of other carrier waves also can be under some influence simultaneously,

For the TD-LTE system, when signal power was very little, direct current leakage caused in operation during FFT, calibrate unsaturatedly in order to consider highest order, had lost signal accuracy, made the decline of TD-LTE overall performance, and receiver sensitivity is received very big influence.

For this reason, eliminating direct current leakage becomes a problem of needing solution badly, and Given this, the processing scheme that provides the tributary to leak in the embodiment of the invention is in order to eliminate direct current leakage.

The processing method that comprises a kind of direct current leakage in the processing scheme that provides the tributary to leak in the embodiment of the invention; And a kind of processing unit of direct current leakage; The two is based on same inventive concept; Because the apparatus and method principle of dealing with problems is similar, so the enforcement of apparatus and method can cross-references, repeats part and repeats no more.For ease of understanding, below will be simultaneously the execution mode of the processing unit of the processing method of direct current leakage and direct current leakage be described simultaneously.

Fig. 3 is the processing method implementing procedure sketch map of direct current leakage, and is as shown in the figure, at first, in the direct current leakage processing procedure, when obtaining direct current leakage, can comprise the steps,

Step 301, obtain the reception signal on I road and Q road in a period of time;

Step 302, I road and the Q road signal amplitude of this section in the time asked for average respectively;

Step 303, with the average on I road direct current leakage amount, with the average on Q road direct current leakage amount as the Q road as the I road.

Concrete, in this scheme, all be modulation signal because the inventor notices that the 3G/4G system sends; It is at random that modulation signal is limit distribution mutually at 4, so a large amount of such signal stacks, its average is near zero; The signal of statistics is many more, average just more approaching zero.Therefore; Signal of communication I road/Q road average is vibration near zero; Through a period of time statistics to received signal, calculate the average of interior during this period of time I road/Q road signal, the average of this segment signal that just can in this programme, statistics be obtained is thought the size and Orientation of I road/Q paths direct current leakage; Deducting this direct current leakage with the signal of sampling then must revised signal, eliminates the purpose that DC leaks thereby reach.

Therefore, in the direct current leakage processing procedure, can further include:

Step 304, the sampled signal on the I road is revised, the sampled signal on the Q road is revised with the direct current leakage amount on said Q road with the direct current leakage amount on said I road.

The average that the signal of sampling deducts with this segment signal can be expressed as as the revised signal of direct current leakage:

$\mathrm{dc}\_\mathrm{ri}=\frac{\underset{k=1}{\overset{K}{\mathrm{\Σ}}}\mathrm{ri}\left(k\right)}{K},$ $\mathrm{dc}\_\mathrm{rq}=\frac{\underset{k=1}{\overset{K}{\mathrm{\Σ}}}\mathrm{rq}\left(k\right)}{K}$

ri(k)＝ri(k)-dc_ri k＝1…K

rq(k)＝rq(k)-dc_rq k＝1…K

Wherein, dc_ri, dc_rq are respectively the average of the signal of K data volume in I road, Q road the preceding paragraph time, and ri (k), ri (k) are respectively I road, Q road up-sampling signal.

Accordingly, a kind of possible hardware implement device is provided in the embodiment of the invention, has described below.

Fig. 4 is the processing unit structural representation of direct current leakage, and is as shown in the figure, can comprise in the device:

Acquisition module 401 is used to obtain the reception signal on interior I road of a period of time and Q road;

Average module 402 is used for I road and the Q road signal amplitude of this section in the time asked for average respectively;

Leak determination module 403, be used for, with the average on Q road direct current leakage amount as the Q road with the average on I road direct current leakage amount as the I road.

In the enforcement, can further include in the device:

Correcting module 404 is used for the direct current leakage amount on said I road the sampled signal on the I road being revised, and with the direct current leakage amount on said Q road the sampled signal on the Q road is revised.

But a problem that exists under this processing mode is: the amplitude of input signal is for TD-SCDMA or TD-LTE, and the dynamic range that receives signal is very big, causes the dc_ri and the dc_rq that revise to be in the continuous change procedure.The numerical value of direct current leakage skew also needs constantly to revise.Therefore; To adopt the real-time DC drift correction of self adaptation algorithm to overcome the problem that DC leaks in the embodiment of the invention; In concrete scheme, will adopt the mode that eliminates through sliding window+accumulator to overcome direct current leakage, and will overcome 3 following difficult points that in eliminating the direct current leakage process, exist at least at least:

First: resource and the processing delay of Digital Signal Processing direct current leakage when adopting like FPGA hardware such as (Field Programmable Gate Array, field programmable gate arrays) is limited.

Second: the size of direct current leakage changes along with the size of input signal;

The 3rd: direct current leakage is along with the time is drifting about, and just the size and Orientation of direct current leakage receives the influence of temperature and environment.

Following elder generation describes solving the limited problem of FPGA hardware resource.

In the direct current leakage processing procedure, in step 301 is obtained a period of time during the reception signal on I road and Q road; Specifically can for:

When obtaining signal, the reception signal on the data volume of L power power statistics I road and Q road by 2.

In the enforcement, L generally can get 10～15, need consider time delay and resource-constrained reason during value, if L is too big, needs data in buffer too many, and the space that causes like this opening up is too big.Can combine actual needs to confirm corresponding value in the concrete practice.

Accordingly, in the processing unit of the direct current leakage that provides in embodiments of the present invention, the average module can also be further used for by the data volume statistics I road of 2 L power power and the reception signal on Q road.

In the enforcement; Because these hardware need be used division when calculating direct current leakage; This makes like RRU (Radio Remote Unit; Remote Radio Unit) etc. equipment need consume the hardware division device when calculating direct current leakage, and resource consumption is bigger, provides the statistics input signal to adopt the mode of 2 L power power to solve the bigger problem of resource consumption in the embodiment of the invention for this reason.

For example; With FPGA is example, and the data volume of statistics can be more than 1024 points when realizing with FPGA, and (in the enforcement, the conclusion that draws according to emulation and test result of selecting for use of data volume is: generally select 1024 points; Otherwise the accuracy of calculating is not enough); Preferably available is 4096 sampled points, so just can save the resource because of adopting division arithmetic to consume, and processing formula can be following:

$\mathrm{dc}\_\mathrm{ri}=\left[\underset{k=1}{\overset{K}{\mathrm{\Σ}}}\mathrm{ri}\left(k\right)\right]>>L,2^L=K$

$\mathrm{dc}\_\mathrm{rq}=\left[\underset{k=1}{\overset{K}{\mathrm{\Σ}}}\mathrm{rq}\left(k\right)\right]>>L,2^L=K$

Wherein,＞＞implication be meant and move to right, just divided by 2 ^L, such as following formula signal 1024=2 ^L=K:

$\mathrm{dc}\_\mathrm{ri}=\frac{\left[\underset{k=1}{\overset{K}{\mathrm{\Σ}}}\mathrm{ri}\left(k\right)\right]}{2^L},2^L=K$

$\mathrm{dc}\_\mathrm{rq}=\frac{\left[\underset{k=1}{\overset{K}{\mathrm{\Σ}}}\mathrm{rq}\left(k\right)\right]}{2^L},2^L=K$

Because the data summation operation of input need be used buffer, therefore generally in the practical implementation of FPGA, can adopt FIFO (First In First Out, first in first out) register to preserve the signal of input.

Therefore, in the enforcement, by the reception signal on the data volume statistics I road of 2 L power power and Q road the time, can adopt fifo register to add up the data volume of the reception signal on I road and Q road.

Accordingly; In the processing unit of the direct current leakage that provides in embodiments of the present invention; The average module can also be further used for by the reception signal on the data volume statistics I road of 2 L power power and Q road the time, the data volume that the employing fifo register is added up the reception signal on I road and Q road.

Because the signal of input is all participated in the calculating of direct current leakage, the signal of buffer memory there is no need too much for this reason, generally adopts 1024 points to get final product.For f _sEqual 30.72MHZ, the buffer memory of the FIFO K=1024 that counts, time-delay only has Equal 33us, time-delay such for system can be tolerated.For the TDD system, for example all signals in each time slot of TD-SCDMA or TD-LTE are all participated in the calculating of DC-OFFSET, and use resource seldom just can the very effective precision that strengthens DC-OFFSET calculating like this.

1, backward signal buffer memory dc shift eliminates the scheme explanation.

To the system that can tolerate this reference time delay; To provide the signal after a kind of FIFO of utilization exports to deduct the mode that direct current offset obtains the revised signal of direct current in the embodiment of the invention; In the embodiment of the invention this mode is called: backward signal buffer memory dc shift eliminates scheme; Behind this scheme called after to being because the signal that direct current leakage is proofreaied and correct is the output signal of fifo register; So that distinguish with following forward scheme, eliminate in the scheme at forward signal buffer memory dc shift, the signal that direct current leakage is proofreaied and correct is the input signal of fifo register.Dealing with relationship between its signal can be found out by following formula:

$\mathrm{sum}\_i(t+1)={\mathrm{ri}}_t\left(0\right)+\left[\underset{k=1}{\overset{K}{\mathrm{\Σ}}}{\mathrm{ri}}_t\left(k\right)\right]-{\mathrm{ri}}_t(K+1)=\mathrm{sum}\_i\left(t\right)+{[\mathrm{ri}}_t\left(0\right)-{\mathrm{ri}}_t(K+1)]$

$\mathrm{sum}\_q(t+1)={\mathrm{rq}}_t\left(0\right)+\left[\underset{k=1}{\overset{K}{\mathrm{\Σ}}}{\mathrm{rq}}_t\left(k\right)\right]-{\mathrm{rq}}_t(K+1)=\mathrm{sum}\_q\left(t\right)+{[\mathrm{rq}}_t\left(0\right)-{\mathrm{rq}}_t(K+1)]$

dc_ri(t+1)＝sum_i(t+1)＞＞L 2 ^L＝K

dc_rq(t+1)＝sum_q(t+1)＞＞L 2 ^L＝K

ri(t+1-K)＝ri(t+1)-dc_ri(t+1)

rq(t+1-K)＝rq(t+1)-dc_rq(t+1)

Wherein, sum is meant and carries out summation operation.Only represent a sum_i as a result here.

Also be; Add up under the mode of data volume of reception signal on I road and Q road adopting fifo register; Then with the direct current leakage amount on said I road the sampled signal on the I road is revised in step 304; Sampled signal on the Q road is done can comprise in the process of correction with the direct current leakage amount on said Q road:

With the reception signal input fifo register on I road, with the reception signal input fifo register on Q road;

I road signal with the input fifo register deducts the signal of exporting fifo register, deducts the signal of output fifo register with the Q road signal of input fifo register;

The signal that the I road is subtracted each other the back acquisition adds up, and the signal that the Q road is subtracted each other the back acquisition adds up;

The signal that is added up in the I road after the cut position calculation process as the direct current leakage amount, the signal that is added up in the Q road after the cut position calculation process as the direct current leakage amount;

Direct current leakage amount with the I road is revised the signal of I road output fifo register, with the direct current leakage amount on Q road the signal of Q road output fifo register is revised.

Concrete, a kind of possible hardware implement device also is provided in the embodiment of the invention, describe below.

Fig. 5 has the backward signal buffer memory dc shift of delay process to eliminate the apparatus structure sketch map, and is as shown in the figure, can comprise in the device:

First fifo register 501, the I road that input input ADC gathers and first signal on Q road, output output secondary signal;

First adder 502, one ends link to each other with the input of first fifo register, and an end links to each other with the output of first fifo register, and an end links to each other with first accumulator, input first accumulator after deducting secondary signal with first signal to obtain the 3rd signal;

First accumulator, 503, one ends link to each other with first adder, an end links to each other with the first cut position arithmetic unit, and the 3rd signal of first adder input the 4th signal that the back obtains that adds up is imported the first cut position arithmetic unit;

The first cut position arithmetic unit, 504, one ends link to each other with first accumulator, an end links to each other with the first cut position arithmetic unit, and an end links to each other with first adder, the 4th signal are carried out the direct current leakage amount input second adder that obtains after the cut position calculation process;

Second adder 505, one ends link to each other with the first cut position arithmetic unit, and an end links to each other with the output of first fifo register, deducts the direct current leakage amount with secondary signal.

Among the figure ,+,-representative is sign, just plus sige or minus sign.

In the enforcement, the cut position computing is meant clips output result minimum L bit, and for example data are clipped minimum 3 bits if 8192, and the result is exactly 1024 so.This cut position computing can not consume any hardware resource in force the time.

Concrete, it is following that backward signal buffer memory dc shift eliminates the apparatus processes execution mode:

The signal Ri/Rq that ADC gathers gets in the fifo register, and the FIFO storage is null value during initialization, so in fact be exactly that the signal of importing adds up at incipient stage input signal and FIFO output signal subtraction; By the time after being added to K signal; Filled up the signal of input among the FIFO, the signal that has begun up-to-date input this moment deducts the signal of the terminal output of FIFO, joins in the accumulator; Form up-to-date SUM, obtain up-to-date dc_ri (t+1)/dc_rq (t+1) after the computing of SUM cut position.

It is thus clear that through above-mentioned processing, signal of every input is with regard to a level and smooth direct current leakage dc_ri (t+1)/dc_rq (t+1).Level and smooth in real time renewal of direct current signal made that the direct current calibration is more accurate, and the signal of last FIFO output deducts direct current leakage and has just obtained the revised input signal of final process.

Visible by above-mentioned analysis, through always when 1024 points that slide calculate DC-OFFSET, when hardware realizes that framework is as shown in Figure 5, can find out that this apparatus structure is simple, resource consumption is little.Have the calculating accurate and effective simultaneously, be easy to characteristics such as FPGA realization.

2, forward signal buffer memory dc shift eliminates the scheme explanation.

In the practice, if the delay process time 33us of direct current leakage still is difficult to receive concerning system, the embodiment of the invention also provides other a kind of scheme that eliminates direct current leakage, is called forward signal buffer memory dc shift among the embodiment and eliminates scheme.This kind scheme has no time-delay just can accomplish eliminating of direct current leakage to the signal of input.Eliminate scheme with respect to backward signal buffer memory dc shift, can use the signal of current input to deduct the numerical value of the direct current leakage that a K calculated signals in front obtains, system does not just have delay process like this.Forward signal buffer memory dc shift eliminates scheme, and dealing with relationship between its signal can be found out by following formula:

$\mathrm{sum}\_i(t+1)={\mathrm{ri}}_t\left(0\right)+\left[\underset{k=1}{\overset{K}{\mathrm{\Σ}}}{\mathrm{ri}}_t\left(k\right)\right]-{\mathrm{ri}}_t(K+1)=\mathrm{sum}\_i\left(t\right)+{\mathrm{ri}}_t\left(0\right)-{\mathrm{ri}}_t(K+1)$

$\mathrm{sum}\_q(t+1)={\mathrm{rq}}_t\left(0\right)+\left[\underset{k=1}{\overset{K}{\mathrm{\Σ}}}{\mathrm{rq}}_t\left(k\right)\right]-{\mathrm{rq}}_t(K+1)=\mathrm{sum}\_q\left(t\right)+{\mathrm{rq}}_t\left(0\right)-{\mathrm{rq}}_t(K+1)$

dc_ri(t+1)＝sum_i(t+1)＞＞L 2 ^L＝K

dc_rq(t+1)＝sum_q(t+1)＞＞L 2 ^L＝K

ri(t+1)＝ri(t+1)-dc_ri(t+1)

rq(t+1)＝rq(t+1)-dc_rq(t+1)

Also be; Add up under the mode of data volume of reception signal on I road and Q road adopting fifo register; Then with the direct current leakage amount on said I road the sampled signal on the I road is revised in step 304; Sampled signal on the Q road is done can comprise in the process of correction with the direct current leakage amount on said Q road:

With the reception signal input fifo register on I road, with the reception signal input fifo register on Q road;

I road signal with the input fifo register deducts the signal of exporting fifo register, deducts the signal of output fifo register with the Q road signal of input fifo register;

The signal that the I road is subtracted each other the back acquisition adds up, and the signal that the Q road is subtracted each other the back acquisition adds up;

The signal that is added up in the I road after the cut position calculation process as the direct current leakage amount, the signal that is added up in the Q road after the cut position calculation process as the direct current leakage amount;

Direct current leakage amount with the I road is revised the reception signal on I road, with the direct current leakage amount on Q road the reception signal on Q road is revised.

Concrete, a kind of possible hardware implement device also is provided in the embodiment of the invention, describe below.

Fig. 6 eliminates the apparatus structure sketch map for the forward signal buffer memory dc shift of no delay process, and is as shown in the figure, can comprise in the device:

Second fifo register 601, the I road that input input ADC gathers and first signal on Q road, output output secondary signal;

The 3rd adder 602, one ends link to each other with the input of second fifo register, and an end links to each other with the output of second fifo register, and an end links to each other with second accumulator, input second accumulator after deducting secondary signal with first signal to obtain the 3rd signal;

Second accumulator, 603, one ends link to each other with the 3rd adder, an end links to each other with the second cut position arithmetic unit, and the 3rd signal of the 3rd adder input the 4th signal that the back obtains that adds up is imported the second cut position arithmetic unit;

The second cut position arithmetic unit, 604, one ends link to each other with second accumulator, an end links to each other with the 4th adder, and the direct current leakage amount that the 4th signal carries out obtaining after the cut position calculation process is imported the 4th adder;

The 4th adder 605 links to each other with the second cut position arithmetic unit, deducts the direct current leakage amount with first signal.

Concrete, it is following that forward signal buffer memory dc shift eliminates the apparatus processes execution mode:

The signal Ri/Rq that ADC gathers gets in the fifo register, and the FIFO storage is null value during initialization, so in fact be exactly that the signal of importing adds up at incipient stage input signal and FIFO output signal subtraction; By the time after being added to K signal; Filled up the signal of input among the FIFO, the signal that has begun up-to-date input this moment deducts the signal of the terminal output of FIFO, joins in the accumulator; Form up-to-date SUM, obtain up-to-date dc_ri (t+1)/dc_rq (t+1) after the computing of SUM cut position.Import a direct current leakage dc_ri of signal smoothing (t+1)/dc_rq (t+1).

It is thus clear that, through above-mentioned processing, level and smooth in real time renewal of direct current signal being made that the direct current calibration is more accurate, the direct signal of importing at last deducts direct current leakage and has just obtained through revised input signal.Input signal directly deducts direct current leakage and need not any time-delay, and it is overcritical to the strictness of time-delay to satisfy GSM.

To eliminate the technological progress that resolution chart that scheme or forward signal buffer memory dc shift eliminate scheme is explained the technical scheme that inventive embodiments provides to adopt backward signal buffer memory dc shift below; Below signal all are hardware simulation results that signal that in fact the ZIF receiver is gathered carries out, its technological progress can be referring to illustrated effect comparison.Wherein:

Fig. 7 is tone signal frequency spectrum map before and after the direct current leakage correction, can obviously see direct current leakage among the figure and effectively eliminated.

Fig. 8 is TD signal frequency spectrum map before and after the direct current leakage correction, can obviously see direct current leakage among the figure and all eliminated.

Fig. 9 is TD-LTE signal frequency spectrum map before and after the direct current leakage correction, can obviously see direct current leakage among the figure and all eliminated.

Can find out from top design sketch; Carry out devices at full hardware emulation through gathering actual signal, no matter input signal is single-tone, TD-SCDMA carrier signal or TD-LTE signal; After the technical scheme that adopts the embodiment of the invention to provide, its direct current leakage can effectively eliminate.

Can know by the foregoing description, in the technical scheme that the embodiment of the invention provides, obtain the size of direct current leakage through amplitude averaged to received signal.

Also provide and stored certain data volume through a fifo shift register and carry out adding up and calculating of data, data quantity stored is added up according to 2 L power power, avoids division arithmetic, has reduced the resource of FPGA when the statistics direct current leakage.

Also provide backward signal buffer memory dc shift to eliminate processing scheme to be: the signal Ri/Rq that ADC gathers gets in the fifo register; The FIFO storage is null value during initialization; So after in fact incipient stage input signal and FIFO output signal subtraction are exactly that the signal of importing adds up, are added to K signal by the time, filled up the signal of input among the FIFO; The signal that has begun up-to-date input this moment deducts the signal of the terminal output of FIFO; Join in the accumulator, form up-to-date SUM, obtain up-to-date dc_ri (t+1)/dc_rq (t+1) after the computing of SUM cut position.Import a direct current leakage dc_ri of signal smoothing (t+1)/dc_rq (t+1).Level and smooth in real time renewal of direct current signal made that the direct current calibration is more accurate, and the signal of last FIFO output deducts direct current leakage and has just obtained the revised input signal of final process.

Also provide forward signal buffer memory dc shift to eliminate processing scheme to be: the signal Ri/Rq that ADC gathers gets in the fifo register; The FIFO storage is null value during initialization; So after in fact incipient stage input signal and FIFO output signal subtraction are exactly that the signal of importing adds up, are added to K signal by the time, filled up the signal of input among the FIFO; The signal that has begun up-to-date input this moment deducts the signal of the terminal output of FIFO; Join in the accumulator, form up-to-date SUM, obtain up-to-date dc_ri (t+1)/dc_rq (t+1) after the computing of SUM cut position.Import a direct current leakage dc_ri of signal smoothing (t+1)/dc_rq (t+1).Level and smooth in real time renewal of direct current signal made that the direct current calibration is more accurate, and the direct signal of importing at last deducts direct current leakage and has just obtained through revised input signal.Input signal directly deducts direct current leakage and need not any time-delay, and it is overcritical to the strictness of time-delay to satisfy GSM.

Eliminate scheme with respect to backward signal buffer memory dc shift, forward signal buffer memory dc shift eliminates device, and the signal of input need not to delay time and just can effectively eliminate the direct current offset of each input signal affix.

In sum, in the technical scheme that the embodiment of the invention provides, system just can effectively calculate DC-OFFSET behind level and smooth 1024 points, and hardware is realized simple, and resource consumption is little, delays time little or does not have time-delay.All signals of input are all participated in the calculating of dc shift, thereby can very effectively eliminate the drift of direct current signal, and are applicable to the receiver of TD-SCDMA and TD-LTE system.

Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.

Claims (12)

1. the processing method of a direct current leakage is characterized in that, comprises the steps:

Obtain the reception signal on interior I road of a period of time and Q road;

I road and the Q road signal amplitude of this section in the time asked for average respectively;

With the average on I road direct current leakage amount, with the average on Q road direct current leakage amount as the Q road as the I road.

2. the method for claim 1 is characterized in that, when obtaining the reception signal on I road and Q road in a period of time, and the reception signal on the data volume of L power power statistics I road and Q road by 2.

3. method as claimed in claim 2 is characterized in that, by the reception signal on the data volume statistics I road of 2 L power power and Q road the time, and the data volume that employing fifo fifo register is added up the reception signal on I road and Q road.

4. method as claimed in claim 3 is characterized in that, further comprises:

Direct current leakage amount with said I road is revised the sampled signal on the I road, with the direct current leakage amount on said Q road the sampled signal on the Q road is revised.

5. method as claimed in claim 4 is characterized in that, with the direct current leakage amount on said I road the sampled signal on the I road is revised, and with the direct current leakage amount on said Q road the sampled signal on the Q road is revised, and comprising:

With the reception signal input fifo register on I road, with the reception signal input fifo register on Q road;

I road signal with the input fifo register deducts the signal of exporting fifo register, deducts the signal of output fifo register with the Q road signal of input fifo register;

The signal that the I road is subtracted each other the back acquisition adds up, and the signal that the Q road is subtracted each other the back acquisition adds up;

The signal that is added up in the I road after the cut position calculation process as the direct current leakage amount, the signal that is added up in the Q road after the cut position calculation process as the direct current leakage amount;

Direct current leakage amount with the I road is revised the signal of I road output fifo register, with the direct current leakage amount on Q road the signal of Q road output fifo register is revised.

6. method as claimed in claim 4 is characterized in that, with the direct current leakage amount on said I road the sampled signal on the I road is revised, and with the direct current leakage amount on said Q road the sampled signal on the Q road is revised, and comprising:

With the reception signal input fifo register on I road, with the reception signal input fifo register on Q road;

I road signal with the input fifo register deducts the signal of exporting fifo register, deducts the signal of output fifo register with the Q road signal of input fifo register;

The signal that the I road is subtracted each other the back acquisition adds up, and the signal that the Q road is subtracted each other the back acquisition adds up;

The signal that is added up in the I road after the cut position calculation process as the direct current leakage amount, the signal that is added up in the Q road after the cut position calculation process as the direct current leakage amount;

Direct current leakage amount with the I road is revised the reception signal on I road, with the direct current leakage amount on Q road the reception signal on Q road is revised.

7. the processing unit of a direct current leakage is characterized in that, comprising:

Acquisition module is used to obtain the reception signal on interior I road of a period of time and Q road;

The average module is used for I road and the Q road signal amplitude of this section in the time asked for average respectively;

Leak determination module, be used for, with the average on Q road direct current leakage amount as the Q road with the average on I road direct current leakage amount as the I road.

8. device as claimed in claim 7 is characterized in that, the average module is further used for by the data volume statistics I road of 2 L power power and the reception signal on Q road.

9. device as claimed in claim 8 is characterized in that, the average module is further used for by the reception signal on the data volume statistics I road of 2 L power power and Q road the time, the data volume that the employing fifo register is added up the reception signal on I road and Q road.

10. device as claimed in claim 9 is characterized in that, further comprises:

Correcting module is used for the direct current leakage amount on said I road the sampled signal on the I road being revised, and with the direct current leakage amount on said Q road the sampled signal on the Q road is revised.

11. device as claimed in claim 9 is characterized in that, said average module is first fifo register, and said correcting module comprises first adder, first accumulator, the first cut position arithmetic unit, second adder, wherein:

First fifo register, the I road that input input ADC gathers and first signal on Q road, output output secondary signal;

First adder, an end links to each other with the input of first fifo register, and an end links to each other with the output of first fifo register, and an end links to each other with first accumulator, input first accumulator after deducting secondary signal with first signal to obtain the 3rd signal;

First accumulator, an end link to each other with first adder, an end links to each other with the first cut position arithmetic unit, and the 3rd signal of first adder input the 4th signal that the back obtains that adds up is imported the first cut position arithmetic unit;

The first cut position arithmetic unit, an end links to each other with first accumulator, an end links to each other with the first cut position arithmetic unit, and an end links to each other with first adder, the 4th signal is carried out the direct current leakage amount input second adder that obtains after the cut position calculation process;

Second adder, an end links to each other with the first cut position arithmetic unit, and an end links to each other with the output of first fifo register, deducts the direct current leakage amount with secondary signal.

12. device as claimed in claim 9 is characterized in that, said average module is second fifo register, and said correcting module comprises the 3rd adder, second accumulator, the second cut position arithmetic unit, the 4th adder, wherein:

Second fifo register, the I road that input input ADC gathers and first signal on Q road, output output secondary signal;

The 3rd adder, an end links to each other with the input of second fifo register, and an end links to each other with the output of second fifo register, and an end links to each other with second accumulator, input second accumulator after deducting secondary signal with first signal to obtain the 3rd signal;

Second accumulator, an end links to each other with the 3rd adder, an end links to each other with the second cut position arithmetic unit, and the 3rd signal of the 3rd adder input the 4th signal that the back obtains that adds up is imported the second cut position arithmetic unit;

The second cut position arithmetic unit, an end links to each other with second accumulator, an end links to each other with the 4th adder, and the direct current leakage amount that the 4th signal carries out obtaining after the cut position calculation process is imported the 4th adder;

The 4th adder links to each other with the second cut position arithmetic unit, deducts the direct current leakage amount with first signal.

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