CN102413036A - Real-time partial dynamic reconfigurable system - Google Patents
Real-time partial dynamic reconfigurable system Download PDFInfo
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- CN102413036A CN102413036A CN2011102414883A CN201110241488A CN102413036A CN 102413036 A CN102413036 A CN 102413036A CN 2011102414883 A CN2011102414883 A CN 2011102414883A CN 201110241488 A CN201110241488 A CN 201110241488A CN 102413036 A CN102413036 A CN 102413036A
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Abstract
The invention belongs to the technical field of design of reconfigurable circuit systems, and particularly relates to a partially dynamic reconfigurable system. The system is realized based on a configurable on-chip interconnection network structure, and specifically comprises a fine-grained reconfigurable IP, a coarse-grained reconfigurable IP, a reconfigurable special processor IP and the like, wherein all IPs are connected by adopting a hierarchical on-chip interconnection network. The on-chip interconnection network is provided with a configuration interface, so that any reconfigurable IP can be dynamically reconfigured in real time through the interconnection network. Thus, the real-time dynamic reconfiguration of partial reconfigurable IP, namely, the partial dynamic reconfiguration of the whole chip is realized. Compared with the traditional bus macro structure, the invention has the advantages of higher flexibility and simpler implementation method. The method has great significance for quickly constructing a high-performance partially dynamic reconfigurable system.
Description
Technical field
The invention belongs to reconfigurable circuit system design technical field, be specially a kind of partial dynamic reconfigurable system chip.
Background technology
Restructural calculates (Reconfigurable Computing) and is widely used in the design of Adaptable System, tolerant system etc.It utilizes the static of FPGA bit stream or dynamically changes static or dynamic change of realizing hardware circuit based on the flexibility of reconfigurable circuits such as FPGA.The restructural calculations incorporated characteristics of traditional asic technology and general processor technology, both had the flexibility of general processor, have high computational speed and the efficient of ASIC again.
(Partially and Dynamically Reconfigurable, PDR) system is meant that system can on-the-fly modify the part bit stream, to reach the purpose that on-the-fly modifies the partial circuit structure when operation to the partial dynamic restructural.The partial dynamic restructural becomes more fine-grained functional module with task division often, carries out according to the stage timesharing that task is carried out, and the corresponding partial circuit of reconstruct dynamically, and do not need the part of reconstruct not receive this process influence.
The PDR system adopts bus grand (Bus Macro) structure to realize that this method need use physical constraint to limit the grand position of bus usually, and method for using is inconvenience comparatively.In addition, add bus macrostructure, may reduce the performance of system.And in the partial dynamic reconfigurable system based on configurable on-chip interconnect network, each FPGA IP is divided for a reconfiguration unit naturally, and part reconstruct is reshuffling of part IP, and this makes that exploitation is very convenient.In addition, communicate through the on-chip interconnect network between each module, help the lifting of systematic function.
Summary of the invention
The object of the invention is to provide a kind of flexible, high performance partial dynamic reconfigurable system.
Partial dynamic reconfigurable system provided by the invention; It is a kind of partial dynamic reconfigurable system based on configurable on-chip interconnect network and reconfigurable I P nuclear; This system is made up of a plurality of reconfigurable I P nuclears and other special I P nuclear, and each IP kernel connects through configurable on-chip interconnect network; Router in the configurable on-chip interconnect network and the network interface of each IP are divided into two parts: general data interface and configuration interface; General data interface delivery network data are used for the communication between each IP kernel; Configuration interface is used for the configuration through the network control IP kernel; Special I P and part reconfigurable I P are set to the static circuit module, and another part reconfigurable I P is set to the dynamic circuit module, when moving in system, realize the partial dynamic restructural of system through configuration interface.System configuration is referring to shown in Figure 1.
Among the present invention; The described reconfigurable configurable on-chip interconnect network of partial dynamic that is suitable for; In the network interface of route and reconfigurable I P nuclear, add the configuration interface module that control reconfigurable I P configuration is arranged, and adding there is the control bit of distinguishing general data and configuration data in network packet.Referring to shown in Figure 2.Specifically, be provided with the general data transmission control module in the network interface, configuration bit flows down and carries control module.When network interface when route is received packet, is general data or configuration data through inquiry packet header specified data earlier, then according to data type, data passes is transmitted to corresponding general data interface or configuration interface.
Configurable on-chip interconnect network system of the present invention; Be in traditional network-on-a-chip; Added the configuration interface of configuration reconfigurable I P nuclear, the system that makes can dynamically dispose each reconfigurable I P through this configuration interface, provides the foundation for the reconstruct of high-performance partial dynamic is provided.
In order to support configuration interface, need in packet packet header, add control information, be general data or configuration data to distinguish data.In addition, network interface also must be divided into two parts, general data interface and configuration data interface.Through obtaining the configuration data in the network, configuration interface control reconfigurable I P reshuffles.
Among the present invention, reconfigurable I P comprises fine granularity reconfigurable I P (as based on fine granularity reconfigurable I P of SRAM LUT etc.), and coarseness reconfigurable I P, restructural application specific processor IP etc.System can also add all kinds of static IPs as required, and like CPU IP, special-purpose ASIC IP etc., these IP need not use configuration interface, only come Data transmission through the on-chip interconnect network.
The partial dynamic reconfigurable system is divided into static circuit and dynamic circuit when design.Static circuit can use static IP and reconfigurable I P, before system's operation, accomplishes configuration, and in whole system run duration fixed function.Dynamic circuit uses reconfigurable I P to realize that run duration dynamically changes in system, with the dynamic function of completion system needs.
Partial dynamic reconfigurable system chip based on configurable on-chip interconnect network and reconfigurable I P provided by the invention can simplified system be developed, and makes up high performance partial dynamic reconfigurable system fast.
Description of drawings
Fig. 1 is the partial dynamic reconfigurable system chip example based on configurable on-chip interconnect network and reconfigurable I P nuclear.
Fig. 2 is the signal of network enabled network configured interface structure.
Embodiment
In order to realize the partial dynamic restructural of system, need in system support sector's parallel circuit in the system reconfiguration function.This invention is supported in the partial circuit reconstruct of system through in network-on-chip, supporting the mode of the transmission of configuration data.
Whole system is shown in accompanying drawing 1.System mainly comprises the network-on-a-chip of supporting the configuration bit flow transmission; Transmission of control general data and configuration bit flow down and carry network interface; Support is in real time on the reconfigurable I P of system configuration nuclear power road, and other static function IP kernel circuit, like CPU IP, ASIC IP etc.
Accompanying drawing 2 has been illustrated the internal structure of network interface.Network interface mainly is divided into the general data transmission control module, and configuration bit flows down and carries control module.When network interface when route is received packet, is general data or configuration data through inquiry packet header specified data earlier, then according to data type, data passes is transmitted to the corresponding port.Such design also provides the ability through network configuration reconfigurable I P in the basic function that guarantees normal network-on-chip communication.
Come the partial dynamic restructural function of system is described with an instance below.Shown in accompanying drawing 1, chip is made up of the mesh network of 3x3, and 9 IP kernel circuit are arranged in the system, realizes that is supported the reconfigurable image filter circuit design of partial dynamic.
Because in the image filtering computing, some spot correlations around the calculating of each point is only followed are so can provide concurrency to the image filtering computing.In addition,, need to use the pictures different filter, can utilize the reconstruct performance so again along with the difference of picture noise.For example, when handling Gaussian noise, system adopts mean filter to carry out filtering.At this moment, polylith fine granularity or coarseness reconfigurable I P caryogamy are changed to mean filter, application specific processor IP is responsible for reading in output image data from external memory storage.So just can let the parallel processing of polylith filter circuit, accelerate operation.When handling salt-pepper noise, system adopts median filter.At this moment, CPU IP control is reconstructed into median filter with fine granularity or coarseness reconfigurable I P, and carries out parallel processing.
Workflow is following:
1, after system powered on, CPU started, and read the exterior storage bit stream and carried out initial configuration through network-on-chip control polylith fine granularity or coarseness reconfigurable I P, as be configured to mean filter;
2, during system's filtering Gaussian noise, CPU control application specific processor IP reads in view data, and lets a plurality of fine granularities or coarseness reconfigurable I P carry out parallel computation;
3, when needs filtering salt-pepper noise, CPU control fine granularity or coarseness reconfigurable I P reprovision are changed to median filter;
4, reshuffle completion after, CPU control application specific processor IP reads in view data, and lets a plurality of fine granularities or coarseness reconfigurable I P carry out concurrent operation.
Like this, system has just realized the partial dynamic restructural computing based on configurable on-chip interconnect network.
Claims (5)
1. partial dynamic reconfigurable system; It is characterized in that it being a kind of partial dynamic reconfigurable system based on configurable on-chip interconnect network and reconfigurable I P nuclear; This system is made up of a plurality of reconfigurable I P nuclears and other special I P nuclear, and each IP kernel connects through configurable on-chip interconnect network; Router in the configurable on-chip interconnect network and the network interface of each IP are divided into two parts: general data interface and configuration interface; General data interface delivery network data are used for the communication between each IP kernel; Configuration interface is used for the configuration through the network control IP kernel; Special I P and part reconfigurable I P are set to the static circuit module, and another part reconfigurable I P is set to the dynamic circuit module, when moving in system, realize the partial dynamic restructural of system through configuration interface.
2. partial dynamic reconfigurable system according to claim 1; It is characterized in that described configurable on-chip interconnect network; Be the configuration interface module that has added control reconfigurable I P configuration in the network interface with route and reconfigurable I P nuclear, and in network packet, added the control bit of distinguishing general data and configuration data.
3. partial dynamic reconfigurable system according to claim 1 is characterized in that being provided with in the described configurable on-chip interconnect network of network interface general data transmission control module and configuration bit and flows down a year control module; When network interface when route is received packet, is general data or configuration data through inquiry packet header specified data earlier, then according to data type, data passes is transmitted to corresponding general data interface or configuration interface.
4. according to claim 1 or 3 described partial dynamic reconfigurable systems, it is characterized in that described reconfigurable I P comprises fine granularity reconfigurable I P, coarseness reconfigurable I P, restructural application specific processor IP.
5. partial dynamic reconfigurable system according to claim 4 is characterized in that system also adds all kinds of static IPs are arranged, and these static IPs are only through on-chip interconnect network delivery data.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105703948A (en) * | 2016-01-19 | 2016-06-22 | 河海大学常州校区 | On-chip network communication structure simulating and evaluating platform based on FPGA |
| CN107196792A (en) * | 2017-05-17 | 2017-09-22 | 南京大学 | The Reconfigurable Computation Configuration network system of expansible support partially dynamical reconfiguration |
| CN105393504B (en) * | 2014-07-02 | 2018-09-28 | 华为技术有限公司 | Computer system |
| CN113468102A (en) * | 2021-07-22 | 2021-10-01 | 无锡沐创集成电路设计有限公司 | Mixed-granularity computing circuit module and computing system |
| CN116737618A (en) * | 2023-08-14 | 2023-09-12 | 浪潮电子信息产业股份有限公司 | FPGA architecture, device, data processing method, system and storage medium |
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| CN101833368A (en) * | 2010-04-13 | 2010-09-15 | 杭州电子科技大学 | Method for managing energy of local dynamic reconfigurable system by coordinatively processing software and hardware |
| CN101977152A (en) * | 2010-11-12 | 2011-02-16 | 复旦大学 | High-performance network-on-chip system suitable for reconfiguration |
| CN102075578A (en) * | 2011-01-19 | 2011-05-25 | 南京大学 | Distributed storage unit-based hierarchical network on chip architecture |
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| US20090106341A1 (en) * | 2005-08-22 | 2009-04-23 | Adnan Al Adnani | Dynamically Reconfigurable Shared Baseband Engine |
| CN101630306A (en) * | 2009-08-14 | 2010-01-20 | 西北工业大学 | Dynamic reconfigurable device and method for carrying out dynamic reconfiguration thereby |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105393504B (en) * | 2014-07-02 | 2018-09-28 | 华为技术有限公司 | Computer system |
| CN105703948A (en) * | 2016-01-19 | 2016-06-22 | 河海大学常州校区 | On-chip network communication structure simulating and evaluating platform based on FPGA |
| CN107196792A (en) * | 2017-05-17 | 2017-09-22 | 南京大学 | The Reconfigurable Computation Configuration network system of expansible support partially dynamical reconfiguration |
| CN107196792B (en) * | 2017-05-17 | 2020-08-04 | 南京大学 | Expandable reconfigurable computing configuration network system supporting dynamic partial reconfiguration |
| CN113468102A (en) * | 2021-07-22 | 2021-10-01 | 无锡沐创集成电路设计有限公司 | Mixed-granularity computing circuit module and computing system |
| CN116737618A (en) * | 2023-08-14 | 2023-09-12 | 浪潮电子信息产业股份有限公司 | FPGA architecture, device, data processing method, system and storage medium |
| CN116737618B (en) * | 2023-08-14 | 2023-11-14 | 浪潮电子信息产业股份有限公司 | FPGA architecture, device, data processing method, system and storage medium |
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Application publication date: 20120411 |