CN102412296B - Super junction semiconductor device structure and manufacturing method thereof - Google Patents
Super junction semiconductor device structure and manufacturing method thereof Download PDFInfo
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- CN102412296B CN102412296B CN201110092102.7A CN201110092102A CN102412296B CN 102412296 B CN102412296 B CN 102412296B CN 201110092102 A CN201110092102 A CN 201110092102A CN 102412296 B CN102412296 B CN 102412296B
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Abstract
The invention discloses a super junction semiconductor device structure. The super junction semiconductor device structure comprise an N-type substrate, and a drain which is led out of the back of the N-type substrate; the space above the N-type substrate is divided into a cellular area and a terminal area; in the cellular area, an N-epitaxial layer is formed above the N-type substrate, a plurality of grooves are formed in the N-epitaxial layer, and a P-type epitaxial layer is formed in each groove; the N-type substrate in the terminal area is provided with an insulation oxidization layer which is provided with a second N-type substrate; and the second N-type substrate is provided with the N-epitaxial layer. The invention also discloses a manufacturing method for the device structure. The number of terminal rings in the super junction semiconductor device structure can be reduced and the chip occupying area of the super junction semiconductor device structure is reduced.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly relate to a kind of super-junction semiconductor device structure.The invention still further relates to a kind of manufacture method of super junction-semiconductor device.
Background technology
Super junction MOSFET (mos field effect transistor) has super-junction structures because of it, P type and the N-type silicon epitaxy post layer in Semiconductor substrate with alternative arrangement, make the PN junction in this device HeNXing district in p type island region under cut-off state produce depletion layer, thereby improve the withstand voltage of device.
In the design process of super junction-semiconductor device, except needs cellular region have sufficiently high withstand voltage, the design of its terminal area structure also plays a key effect to the withstand voltage height of super junction.Common terminal area structure is designed to the groove of a plurality of floating skies, and groove is inserted P type polysilicon, by these P type polysilicons and N-type epitaxial loayer, exhausts to reduce transverse electric field, and protection cellular region is not punctured by transverse electric field.This super-junction semiconductor device structure design is complicated above, and in addition, due to end ring quantity more (end ring is the groove of having filled P type epitaxial loayer in terminal area), its occupied chip area is also inevitable very large.
Summary of the invention
The technical problem that the present invention solves is to provide a kind of super-junction semiconductor device structure, can simplify the complexity of device structure design, reduces the quantity of groove, the area of the shared chip of reduction of device; For this reason, the present invention also will provide a kind of manufacture method of described super-junction semiconductor device structure.
For solving the problems of the technologies described above, super-junction semiconductor device structure of the present invention, comprising:
N-type substrate, the drain electrode of drawing from this N-type substrate back, described N-type substrate top is divided into cellular region and terminal area; In described cellular region, described N-type substrate upper end is provided with N-epitaxial loayer, in this N-epitaxial loayer, has a plurality of grooves, is filled with P type epitaxial loayer in described groove; It is characterized in that:
In described terminal area, described N-type substrate upper end has an insulating oxide, and this insulating oxide upper end has the second N-type substrate, and this second N-type substrate upper end has N-epitaxial loayer, in this N-epitaxial loayer, has a plurality of grooves.
The manufacture method of described super-junction semiconductor device structure, comprises the following steps:
Step 2, carry out etching, make insulating oxide after etching only be present in the terminal area of described device, insulating oxide in cellular region and the N-type substrate of top thereof are removed;
Step 3, on described N-type substrate deposit one deck N-epitaxial loayer;
N-epitaxial loayer described in step 4, etching, forms a plurality of grooves, forms P type epitaxial loayer in groove.
Adopt super-junction semiconductor device structure of the present invention and manufacture method, the terminal area of traditional super-junction semiconductor device structure is combined with silicon insulating process, the terminal area of super-junction structures is made on insulating oxide, the pressure drop of device drain terminal has quite a few to be born by this insulating oxide, required end ring quantity also can correspondingly reduce, therefore the entire area of device also can significantly dwindle like this, has simplified the complexity of super-junction semiconductor device structure design.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is structural representation of the present invention.
Fig. 2 A to Fig. 2 D is the preparation flow figure of manufacture method of the present invention.
Description of symbols in figure
1 is that P+ type diffusion region 2 is N+ type diffusion region (source electrode)
3 is that polysilicon gate (grid) 4 is gate oxide
5 is that N-epitaxial loayer 6 is P type epitaxial loayer
7 is that P trap 8 is N-type substrate (drain electrode)
9 is that insulating oxide 10 is cellular region
11 is that terminal area 12 is the second N-type substrate layer
Embodiment
As shown in Figure 1, described super-junction semiconductor device structure in one embodiment, comprises:
One N-type substrate 8, draws drain electrode from the back side (being the lower surface shown in Fig. 1) of N-type substrate 8, and the top of described N-type substrate 8 is divided into 10Yu terminal area, cellular region 11.
In cellular region 10, the top of described N-type substrate 8 is formed with one deck N-epitaxial loayer 5, in this N-epitaxial loayer 5, be formed with a plurality of grooves, in groove, be filled with P type epitaxial loayer 6, the top that is positioned at groove P type epitaxial loayer 6 is formed with P+ diffusion region 1, the two side ends that is positioned at groove in the upper end of N-epitaxial loayer 5 is formed with P trap 7, in P trap 7, form N+ diffusion region 2, by N+ diffusion region 2, draw source electrode, be positioned at adjacent 2 tops, two N+ diffusion regions and there is one deck gate oxide 4, upper end at gate oxide 4 forms polycrystalline silicon grid layer 3, by polycrystalline silicon grid layer 3, draws grid.
In described terminal area 11, described N-type substrate 8 upper ends have an insulating oxide 9, and these insulating oxide 9 upper ends have the second N-type substrate 12, and these the second N-type substrate 12 upper ends have N-epitaxial loayer 5, in this N-epitaxial loayer 5, have a plurality of grooves.
As shown in Fig. 2 A to Fig. 2 D, the manufacture method of described super-junction semiconductor device structure increases following steps in traditional super-junction semiconductor device structure manufacture method:
Step 2, carry out etching, make 9 of insulating oxides after etching be present in the terminal area 11 of described device, insulating oxide 9 in cellular region 10 and the N-type substrate 8 of top thereof are removed;
Step 3, on described N-type substrate 8 deposit one deck N-epitaxial loayer 5;
N-epitaxial loayer 5 described in step 4, etching, forms a plurality of grooves, forms P type epitaxial loayer 6 in groove.
Further improve described manufacture method, during implementation step four, make the quantity of groove of etching and the thickness of insulating oxide 9 be inverse ratio.
Further improve described manufacture method, during implementation step four, make the width of groove in terminal area 11 consistent with the width of groove in cellular region 10.
Further improve described manufacture method, during implementation step four, make the spacing of groove in terminal area 11 consistent with the spacing of groove in cellular region 10.
Further improve described manufacture method, during implementation step four, make in terminal area 11 etching groove to the surface of insulating oxide 9.
Further improve described manufacture method, during implementation step four, make the degree of depth of groove in cellular region 10 surpass the surface of described insulating oxide 9, and be no more than the bottom surface of insulating oxide 9.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (4)
1. a super-junction semiconductor device structure, comprising: N-type substrate, and the drain electrode of drawing from this N-type substrate back, described N-type substrate top is divided into cellular region and terminal area; In described cellular region, described N-type substrate upper end is provided with N-epitaxial loayer, in this N-epitaxial loayer, has a plurality of grooves, is filled with P type epitaxial loayer in described groove; It is characterized in that:
In described terminal area, described N-type substrate upper end has an insulating oxide, this insulating oxide upper end has the second N-type substrate, this the second N-type substrate upper end has N-epitaxial loayer, in this N-epitaxial loayer, there are a plurality of grooves, a plurality of channel portions in described terminal area are arranged in described the second N-type substrate, and form and contact with insulating oxide.
2. super-junction semiconductor device structure as claimed in claim 1, is characterized in that: the thickness of described groove number and insulating oxide is inverse ratio.
3. super-junction semiconductor device structure as claimed in claim 1, is characterized in that: in described terminal area, the width of groove is consistent with the width of groove in cellular region.
4. super-junction semiconductor device structure as claimed in claim 1, is characterized in that: in described terminal area, the spacing of groove is consistent with the spacing of groove in cellular region.
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| CN201110092102.7A CN102412296B (en) | 2011-04-13 | 2011-04-13 | Super junction semiconductor device structure and manufacturing method thereof |
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| CN201110092102.7A CN102412296B (en) | 2011-04-13 | 2011-04-13 | Super junction semiconductor device structure and manufacturing method thereof |
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| CN102412296A CN102412296A (en) | 2012-04-11 |
| CN102412296B true CN102412296B (en) | 2014-02-26 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7554155B2 (en) * | 2005-01-18 | 2009-06-30 | Kabushiki Kaisha Toshiba | Power semiconductor device and method of manufacturing the same |
| CN101552291A (en) * | 2009-03-30 | 2009-10-07 | 东南大学 | Semiconductor tube of hyperconjugation longitudinal double diffusion metal oxide with N channels |
| CN201673912U (en) * | 2010-05-04 | 2010-12-15 | 无锡新洁能功率半导体有限公司 | Semiconductor device with super-junction structure |
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| JP4289123B2 (en) * | 2003-10-29 | 2009-07-01 | 富士電機デバイステクノロジー株式会社 | Semiconductor device |
| JP5196766B2 (en) * | 2006-11-20 | 2013-05-15 | 株式会社東芝 | Semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7554155B2 (en) * | 2005-01-18 | 2009-06-30 | Kabushiki Kaisha Toshiba | Power semiconductor device and method of manufacturing the same |
| CN101552291A (en) * | 2009-03-30 | 2009-10-07 | 东南大学 | Semiconductor tube of hyperconjugation longitudinal double diffusion metal oxide with N channels |
| CN201673912U (en) * | 2010-05-04 | 2010-12-15 | 无锡新洁能功率半导体有限公司 | Semiconductor device with super-junction structure |
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