CN102419434A - Intermediate-frequency and radio-frequency universal target simulator for pulse pressure radar - Google Patents
Intermediate-frequency and radio-frequency universal target simulator for pulse pressure radar Download PDFInfo
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Abstract
The invention discloses an intermediate-frequency and radio-frequency universal target simulator for a pulse pressure radar. The target simulator comprises a power supply module, a reference source generating module, a control display module, an intermediate frequency analog signal generating module, an amplitude regulating module and a hybrid frequency filtering module; the amplitude regulating module is divided into amplitude regulating modules A and B; the hybrid frequency filtering module is divided into hybrid frequency filtering modules A and B; the power supply module is connected with other modules; the reference source generating module is respectively connected with the control display module and the intermediate frequency analog signal generating module; the control display module is respectively connected with the intermediate frequency analog signal generating module, the amplitude regulating module A and the amplitude regulating module B; the intermediate frequency analog signal generating module is respectively connected with the amplitude regulating module A and the amplitude regulating module B; the amplitude regulating module A is connected with the hybrid frequency filtering module A; and the amplitude regulating module B is connected with the hybrid frequency filtering module B. The target simulator provided by the invention has the advantages of simplified circuit, pure frequency spectrum, integrity of the intermediate frequency and the radio frequency, abundant functions, real data and strong pertinence.
Description
Technical field
The invention belongs to the radar engineering technical field, relate to a kind of signal generation device, specifically is intermediate frequency radio frequency general target simulator under a kind of Pulse-compression Radar system.
Background technology
Radar simulator is an analogue means of realizing target information in the radar echo signal, be used for product development and debug phase radar system front end still do not possess or situation based on saving experimentation cost under, the radar system rear end is assessed and is detected.
The radar target signal mainly comprises three kinds of effective informations: amplitude information, brought by factors vary such as target range, target reflection sectional area (RCS), antenna radiation pattern modulation; Frequency domain information, the i.e. Doppler shift (f that causes of moving target
d); Time-domain information, promptly moving target was delayed time apart from the echo time that change causes.
Various information more than the radar simulator simulation, its parameter are provided with need be flexible, and this demand makes that the mode of Digital Implementation is more suitable, and in all analog informations, the Doppler shift (f that the skimulated motion target causes
d) be key point.Have main four kinds of technology: DDS technology to realize at present in the industry, the FPGA technology realizes that realization of general-purpose computations machine technology and multi-purpose computer combine to realize with the DSP technology.
The DDS technology is the new technology along with the fast-developing tight step follow-up of digital technology; It adopts digital structure; Have advantages such as wide relative band, accurate frequency resolution, the frequency inverted speed that is exceedingly fast, low phase noise, therefore become the main flow mode of present radar simulator design.
The two class targets simulators that adopt the DDS technology to realize at present:
1, FPGA (field programmable logic array (FPLA))+DDS (Direct Digital frequency synthesis)+DQUC (directly quadrature up-conversion) circuit.This mode produces Doppler frequency f at video-frequency band utilization FPGA control DDS
d, f
dWith receiver difference frequency signal f
0Through the DQUC circuit, produce one and receive f
dThe analog echo signal f of modulation
0+ f
dOr f
0-f
dThe moving direction of both simulated targets, f
0+ f
dRepresentative " nearby ", f
0-f
dRepresentative " away from ".As shown in Figure 1; Though the signal of certain sideband has up and down been accomplished and chosen to the DQUC circuit; But still the carrier frequency that exists is revealed and unwanted sideband information is not inconsistent with reality, and the inconvenience of DQUC circuit debugging, is prone to the puzzlement that a target " is far gone " and " nearby " occurs simultaneously.
2, FPGA (field programmable logic array (FPLA))+two DDS (Direct Digital frequency synthesis)+mixing and filtering circuit.As shown in Figure 2, this mode produces the signal f of different frequency at two DDS of Mid Frequency utilization
1, f
2, respectively with Radar Local-oscillator signal F
LObtain two local oscillation signal F through upconverter
L1, F
L2Simultaneously simulator can receive a radiofrequency signal Fs, the Fs signal earlier with the FL1 down coversion, through controlled time delay circuit again with F
L2Up-conversion, utilize double conversion obtain one with Fs differ f
dRadiofrequency signal, f
dBe the Doppler frequency of simulation, its essence is the difference on the frequency f that two DDS produce
2-f
1, this mode utilize the intermediate frequency mixing and filtering thinking filtering cleverly the puzzlement of unwanted sideband, but the circuit of this mode crosses and is complicacy, increased volume and cost.
Therefore, studying the simple and simulator that can simulate present situation more truly of a kind of circuit is necessary.
Summary of the invention
Defective or deficiency to above-mentioned two analoglike devices exist the objective of the invention is to, and a kind of Pulse-compression Radar intermediate frequency radio frequency general target simulator is provided, this simulator simulation Doppler frequency f
dGeneration only accomplish with 1 FPGA and 1 DDS, need not DQUC circuit or more DDS chip and mixing and filtering circuit, simultaneously, simulator of the present invention can be simulated present situation more truly.
In order to realize above-mentioned functions, the present invention adopts following technical solution:
A kind of Pulse-compression Radar intermediate frequency radio frequency general target simulator is characterized in that, comprises power module, reference source generation module, control display module, analog intermediate frequency signal generation module, amplitude adjusting module and mixing and filtering module; Amplitude adjusting module is divided into A amplitude adjusting module and B amplitude adjusting module two sub-module; The mixing and filtering module is divided into A mixing and filtering module and B mixing and filtering module two sub-module; Wherein, Power module connects all the other each modules, and the reference source generation module connects control display module, analog intermediate frequency signal generation module respectively, and the control display module connects analog intermediate frequency signal generation module, A amplitude adjusting module, B amplitude adjusting module respectively; The output terminal of analog intermediate frequency signal generation module connects A amplitude adjusting module and B amplitude adjusting module respectively, and the output terminal of A amplitude adjusting module connects A mixing and filtering module, and the output terminal of B amplitude adjusting module connects B mixing and filtering module.
Described reference source generation module comprises constant-temperature crystal oscillator, first power splitter, first amplifier, second amplifier, the 3rd amplifier; Wherein, The output terminal of said constant-temperature crystal oscillator connects said first power splitter, and three road output terminals of first power splitter connect said first amplifier, second amplifier and the 3rd amplifier respectively;
Described control display module comprises control panel, FPGA and display screen, and said control panel, FPGA and display screen link to each other successively;
Described analog intermediate frequency signal generation module comprises the DDS chip and second power splitter; The output terminal of said DDS chip connects said second power splitter;
Said A amplitude adjusting module is by the 4th amplifier, first numerical-control attenuator, and the 3rd numerical-control attenuator links to each other successively and constitutes, and said B amplitude adjusting module is by the 5th amplifier, second numerical-control attenuator, and the 4th numerical-control attenuator links to each other successively and constitutes;
Said A mixing and filtering module is linked to each other successively with first wave filter by first frequency mixer, the 6th amplifier and constitutes; B mixing and filtering module is linked to each other successively with second wave filter by second frequency mixer, the 7th amplifier and constitutes;
Wherein, the output terminal of first amplifier is connected to outside signal processor as the outside output of reference signal, and the output terminal of second amplifier connects the FPGA of control display module; The output terminal of the 3rd amplifier connects the DDS of intermediate frequency simulated target signal generator module;
The output terminal of the FPGA of control display module connects the DDS of intermediate frequency simulated target signal generator module, first numerical-control attenuator of amplitude adjusting module respectively, the frequency synthesizer of the 3rd numerical-control attenuator, second numerical-control attenuator, the 4th numerical-control attenuator, outside and outside signal processor;
The output terminal of second power splitter of intermediate frequency simulated target signal generator module connects the 4th amplifier and the 5th amplifier in the amplitude adjusting module respectively;
The output terminal of the 3rd numerical-control attenuator of amplitude adjusting module connects the signal input end of intermediate frequency of first frequency mixer in the A mixing and filtering module, and the output terminal of the 4th numerical-control attenuator connects the signal input end of intermediate frequency of second frequency mixer in the B mixing and filtering module; In addition, the 3rd numerical-control attenuator, the 4th numerical-control attenuator connect outside signal processor respectively;
The output terminal of outside frequency synthesizer is connected respectively to first frequency mixer of mixing and filtering module and the RF signal input end of second frequency mixer; The output terminal of first wave filter and second wave filter is connected outside radar receiver respectively.
Described constant-temperature crystal oscillator is selected SOXO18-A100M for use, and first power splitter is selected AD4PS-1+ for use, and first amplifier, second amplifier, the 3rd amplifier are all selected HMC479MP86E for use.
Described FPGA adopts EP1C6T144I7N, and display screen adopts the monochromatic OLED screen of 128*64 pixel.
Described DDS chip is selected AD9854ASQ for use, and second power splitter is selected the power splitter of ADP-2-1W+ for use.
Described first numerical-control attenuator, second numerical-control attenuator, the 3rd numerical-control attenuator and the 4th numerical-control attenuator all adopt 6 figure place controlling attenuation device HMC542LP4E.
Described frequency mixer all adopts HMC175MS8E, and wave filter all adopts-BPF. of 1dB bandwidth 120MHz.
Pulse-compression Radar intermediate frequency radio frequency general target simulator of the present invention is compared with the conventional analogue device, has following characteristics:
1, removed traditional DQUC (directly quadrature up-conversion) circuit or more DDS chip, circuit reduction, debugging is convenient; Avoided I/Q two-way amplitude balance; Phase equilibrium, debug time has been saved in the debugging work of direct current biasing in the elimination Doppler frequency and the synchronous use of two DDS; Shorten the construction cycle, and thoroughly eliminated the interference of unwanted sideband and carrier frequency information.
2, in the intermediate frequency simulator, added the mixing and filtering module, make analog intermediate frequency signal can up-conversion to radio band, concentrate frequently with radio frequency in one, enriched the function of simulator, both exportable confession signal processor uses, and also can supply the radar receiver use.
3, saved traditional program design work of setting up antenna model, but more near the actual user mode of product.The measurement data of real dress antenna averaged process truth table, being tabled look-up in real time by control circuit writes the two-way numerical-control attenuator, utilizes the simulation that realizes target azimuth information than the principle of width of cloth angle measurement, and data are true, and frequency spectrum is pure, and is with strong points.
Description of drawings
Fig. 1 is prior art DQUC circuit theory and output spectrum characteristic, and wherein, Fig. 1 (a) is the DQUC schematic block circuit diagram, wherein, and f
0Be receiver difference frequency signal, f
0+ f
dBe the simulated target intermediate-freuqncy signal; Fig. 1 (b) is a DQUC circuit output spectrum characteristic.
Fig. 2 is an of the prior art pair of DDS frequency changer circuit theory diagram.
Fig. 3 is the output signal characteristic of intermediate frequency simulated target signal generator module, and wherein, Fig. 3 (a) is DDS output signal time domain specification, and Fig. 3 (b) is a DDS output spectrum broadband character, and Fig. 3 (c) is a DDS output spectrum narrow-band characteristic.
Fig. 4 is an intermediate frequency radio frequency general target simulator theory diagram.
Fig. 5 is each inside modules block diagram of the present invention, and wherein, Fig. 5 (a) is a reference source generation module block diagram; Fig. 5 (b) is control display module block diagram; Fig. 5 (c) is an analog intermediate frequency signal generation module block diagram, and Fig. 5 (d) is the amplitude adjusting module block diagram, and Fig. 5 (e) is the mixing and filtering module frame chart.
Fig. 6 is a numerical-control attenuator truth table composition;
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed description.
Embodiment
As shown in Figure 4, Pulse-compression Radar intermediate frequency radio frequency general target simulator of the present invention comprises power module 1, reference source generation module 2, control display module 3, analog intermediate frequency signal generation module 4, amplitude adjusting module and mixing and filtering module; Amplitude adjusting module is divided into A amplitude adjusting module 5-1 and B amplitude adjusting module 5-2 two sub-module; The mixing and filtering module is divided into A mixing and filtering module 6-1 and B mixing and filtering module 6-2 two sub-module; Wherein, Power module 1 connects all the other each modules, and reference source generation module 2 connects control display module 3, analog intermediate frequency signal generation module 4 respectively, and control display module 3 connects analog intermediate frequency signal generation module 4, A amplitude adjusting module 5-1, B amplitude adjusting module 5-2 respectively; The output terminal of analog intermediate frequency signal generation module 4 connects A amplitude adjusting module 5-1 and B amplitude adjusting module 5-2 respectively; The output terminal of A amplitude adjusting module 5-1 connects A mixing and filtering module 6-1, and the output terminal of B amplitude adjusting module 5-2 connects B mixing and filtering module 6-2.
Power module 1: be other module for power supply, comprise outside power supply adaptor and inner three terminal regulator.Power supply adaptor is in order to convert AC220V to DC7.5V, and rated current is 5A; Three terminal regulator is respectively MC7805BD2TG, SPX1117M3-3.3, SPX1117M3-1.5, produces the voltage output of 3 kinds of low Ripple Noise, is respectively 5V, 3.3V, 1.5V.
Reference source generation module 2: in order to producing sine wave signal, and this sine wave signal is assigned as 3 tunnel carries out processing and amplifying respectively, use to satisfy control display module 3, analog intermediate frequency signal generation module 4 and outside signal processor.
Shown in Fig. 5 (a); Reference source generation module 2 comprises constant-temperature crystal oscillator 21, first power splitter 22, first amplifier 23, second amplifier 24, the 3rd amplifier 25; Wherein, Three road output terminals that the output terminal of constant-temperature crystal oscillator connects first power splitter, 22, the first power splitters 22 connect first amplifier 23, second amplifier 24, the 3rd amplifier 25 respectively.
Wherein, constant-temperature crystal oscillator is selected the SOXO18-A100M of the proud company in sky, Chengdu for use, and its frequency is output as 100MHz, the about 13dBm of output amplitude, and the frequency temperature degree of stability is less than ± 7 * 10
-8, phase noise is less than-140dBc/100MHz.First power splitter 22 is selected the AD4PS-1+ of MINI company for use, inserts loss 0.55dB, the about 34dB of isolation.First amplifier 23, second amplifier 24, the 3rd amplifier 25 are all selected the HMC479MP86E of HITTITE company for use, and its noise figure is low, little encapsulation, and gain 15dB, the maximum output of 100MHz can reach 20dBm.
Control display module 3: with thinking that the user provides human-computer interaction interface and display interface, and intermediate frequency analogue signal generating module 4, amplitude adjusting module are carried out sequential control according to the parameter of user's setting;
Shown in Fig. 5 (b), control display module 3 comprises control panel 31, FPGA32 and display screen 33, and control panel 31, FPGA32 and display screen 33 link to each other successively.
Wherein, control panel 31 can be made as required, and FPGA32 adopts the EP1C6T144I7N of ALTERA company in order to accomplish the sequential control instruction, and is cheap, is simple and easy to use.Display screen 33 adopts the monochromatic OLED screen of 128*64 pixel.
Analog intermediate frequency signal generation module 4: in order to produce the Doppler shift f that simulated target causes
dWith the time delay difference t that causes of distance
rMedium-frequency pulse modulation signal f
p, and divide two-way (being signal 09-1,09-2) to output to amplitude adjusting module this signal merit.
Shown in Fig. 5 (c), analog intermediate frequency signal generation module 4 comprises the DDS chip 41 and second power splitter 42; The output terminal of DDS chip connects second power splitter 42.
Wherein, DDS chip 41 is selected the AD9854ASQ of ADI company for use.Second power splitter 42 is selected the ADP-2-1W+ of MINI company for use, inserts loss 0.18dB, the about 44dB of isolation.
The real-time change principle of generation of simulation Doppler frequency and range information is following:
Under the linear frequency modulation pattern, suppose that the radar emission signal is:
u
i(t)＝A×a(t)cos(2πFt+kπt
2) a(t)＝1?(0≤t≤τ) (1)
A is an amplitude in the formula (1), and F is a frequency of operation, and k is a chirp rate, and τ is the emission pulsewidth;
Antenna receives the intermediate frequency expression formula of echoed signal behind mixing and filtering:
s(t)＝A′×g(θ)a(t-t
r)cos[(2π(f
0+f
d)(t-t
r)+kπ(t-t
r)
2]?(2)
Wherein: t
r=2R/C (3)
A ' is an echo amplitude in formula (2), (3), f
0Be receiver difference frequency signal, t
rBe the exomonental relatively time-delay of echo, k is a chirp rate, f
dBe Doppler frequency, R is a target range, and C is the light velocity.
Other has f
d=2V
d/ λ (4)
V
dBe target radial speed, λ is the radar system operation wavelength
R＝V
dt (5)
R is a target range in the formula (5)
Can get by formula (3), (4) and (5):
δt
r＝2R
n/C-2R
n-1/C＝f
dλT/C (6)
R in the formula (6)
n, R
N-1Be the target range of two adjacent echo pulse signal reflections of n and n-1, δ t
rPoor for adjacent two echo pulse signal time delayses.
Can find out δ t by formula (6)
rValue is with f
dChange and change, after promptly the initial distance of simulated target is confirmed, utilize counter that each chirp pulse signal is a δ t who accordings to the fd value and exist
rAccumulate, can realize the auto correlation of simulated target variable in distance and Doppler frequency fd.Shown in figure three (a), because δ t
rExistence, two adjacent echo pulse signals are with respect to the time delay t of transponder pulse signal (RF)
R2With t
R1Variation has taken place, f
dFor on the occasion of, δ t
rBe on the occasion of, t
R2＜t
R1f
dBe negative value, δ t
rBe negative value, tr2＞tr1.
Simultaneously, visible by formula (2), every through a frequency modulation on pulse cycle T, the phase of received signal that is caused by Doppler frequency increases δ φ=2 π f
DT, therefore, on the linear frequency modulation basis of satisfying time-delay characteristics that produces, each linear frequency modulation cycle increases the function that a fixing phase value δ φ just can accomplish Doppler shift.Shown in Fig. 3 (a), because the existence of δ φ, through a frequency modulation on pulse cycle T, variation has taken place, f in the initial phase φ of echo pulse signal
dFor on the occasion of, initial phase φ reduces; f
dBe negative value, initial phase φ increases.
Fig. 3 (b), Fig. 3 (c) are the output spectrum characteristic of DDS chip 41, owing to adopt direct frequency synthesis f
0The method of+fd is not so difference frequency signal f can occur
0With unwanted sideband signal f
0The interference problem of-fd, the difference frequency signal f among the figure shown in the dotted line
0Only indicate, do not exist in the reality.
Amplitude adjusting module: medium-frequency pulse FM signal 09-1,09-2 in order to 4 outputs of analog intermediate frequency signal generation module carry out synchronous fading, add changes in amplitude and azimuth information that the simulated target distance causes, obtain adjusted analog intermediate frequency signal f
A, f
B
Amplitude adjusting module is divided into A amplitude adjusting module 5-1 and B amplitude adjusting module 5-2 two sub-module; Shown in Fig. 5 (d), the 4th amplifier 51-1, the first numerical-control attenuator 52-1, the 3rd numerical-control attenuator 53-1 link to each other successively and constitute A amplitude adjusting module 5-1; The 5th amplifier 51-2, the second numerical-control attenuator 52-2, the 4th numerical-control attenuator 53-2 link to each other successively and constitute B amplitude adjusting module 5-2.
Wherein, numerical-control attenuator all adopts 6 figure place controlling attenuation device HMC542LP4E of HITTITE company, and stepping is 0.5dB; The first numerical-control attenuator 52-1, the second numerical-control attenuator 52-2 are used for simulated range and change the influence to echoed signal intensity, and the 3rd numerical-control attenuator 53-1, the 4th numerical-control attenuator 53-2 utilize and than the width of cloth angle measuring principle target azimuth information simulated.
The mixing and filtering module: this module is in order to adjusted intermediate frequency target simulation signal f
A, f
BUp-conversion to radio frequency target simulation signal F
A, F
B
The mixing and filtering module comprises A mixing and filtering module 6-1 and B mixing and filtering module 6-2 two sub-module; Shown in Fig. 5 (e), the first frequency mixer 61-1, the 6th amplifier 62-1 and the first wave filter 63-1 link to each other successively and constitute A mixing and filtering module 6-1; The second frequency mixer 61-2, the 7th amplifier 62-2 and the second wave filter 63-2 link to each other successively and constitute B mixing and filtering module 6-2.
Wherein, frequency mixer all adopts the HMC175MS8E of HITTITE company, conversion loss 8dB, and isolation is not less than 30dB.Wave filter all adopts-1dB bandwidth 120MHz, the outer BPF. that suppresses greater than 70dBc of band.
The annexation of above-mentioned each module is following:
The output terminal of first amplifier 23 is connected to outside signal processor as the outside output of reference signal, and the output terminal of second amplifier 24 connects the FPGA 32 of control display module 3; The output terminal of the 3rd amplifier 25 connects the DDS 41 of intermediate frequency simulated target signal generator module 4;
The output terminal of the FPGA 32 of control display module 3 connects the DDS 41 of intermediate frequency simulated target signal generator module 4, the first numerical-control attenuator 52-1, the 3rd numerical-control attenuator 53-1, the second numerical-control attenuator 52-2, the 4th numerical-control attenuator 53-2, the frequency synthesizer of outside and the signal processor of outside of amplitude adjusting module respectively;
The output terminal of second power splitter 42 of intermediate frequency simulated target signal generator module 4 connects the 4th amplifier 51-1 and the 5th amplifier 51-2 in the amplitude adjusting module respectively;
The output terminal of the 3rd numerical-control attenuator 53-1 of amplitude adjusting module connects the signal input end of intermediate frequency of the first frequency mixer 61-1 among the A mixing and filtering module 6-1, and the output terminal of the 4th numerical-control attenuator 53-2 connects the signal input end of intermediate frequency of the second frequency mixer 61-2 among the B mixing and filtering module 6-2; In addition, the 3rd numerical-control attenuator 53-1, the 4th numerical-control attenuator 53-2 connect outside signal processor respectively.
The output terminal of outside frequency synthesizer is connected respectively to first frequency mixer 61-1 of mixing and filtering module and the RF signal input end of the second frequency mixer 61-2; In addition, the output terminal of the first wave filter 63-1 and the second wave filter 63-2 is connected outside radar receiver respectively.
The workflow of Pulse-compression Radar intermediate frequency radio frequency general target simulator of the present invention is following:
This Pulse-compression Radar intermediate frequency radio frequency general target simulator can switch at intermediate frequency and radio band.Under the intermediate frequency pattern, the FPGA 32 in the control display module 3 does not send any instruction to outside frequency synthesizer, frequency synthesizer local oscillator no-output, radio band no-output.Under rf-mode, the outside module of combining frequently receives 07 instruction that FPGA 32 sends in the control display module 3, the local oscillation signal F of frequency synthesizer output
L(being signal 08-1,08-2) with in A, B mixing and filtering module, realize frequency conversion respectively from A, the adjusted analog intermediate frequency signal 06-1 of B amplitude adjusting module, 06-2, analog intermediate frequency signal still can use under this pattern.
The workflow of Pulse-compression Radar intermediate frequency radio frequency general target simulator of the present invention:
Start power module 1;
The constant-temperature crystal oscillator 21 of reference source generation module 2 produces sine wave signal; First power splitter 22 is divided into 3 road 100MHz sine wave signals 01,02,03 with this sine wave signal; Sine wave signal 01 outputs to signal processor as coherent reference signal outside; Sine wave signal 02 sends to the FPGA 32 of control in the display module 3 clock as a reference, and sine wave signal 03 is given the DDS 41 in the intermediate frequency simulated target signal generator module 4 clock as a reference;
Operating personnel send signal through the 31 couples of FPGA 32 of control panel in the control display module 3, and display screen 32 shows effective instruction, the DDS 41 that FPGA 32 exports sequential control instruction 04 in the intermediate frequency simulated target signal generator module 4 to; FPGA 32 sends to the first numerical-control attenuator 52-1 and the 3rd numerical-control attenuator 53-1 among the A amplitude adjusting module 5-1 with timing control signal 05-1, and FPGA 32 sends to the second numerical-control attenuator 52-2 and the 4th numerical-control attenuator 53-2 in the B amplitude adjusting module with timing control signal 05-2; FPGA 32 exports sequential control instruction 12 to the external signal processor; If be operated under the rf-mode, FPGA 32 also needs outside frequency synthesizer is exported in sequential control instruction 07.
Under the intermediate frequency pattern; DDS 41 in the intermediate frequency simulated target signal generator module 4 receives sine wave signal 03, sequential control instruction 04; The output intermediate-freuqncy signal; This intermediate-freuqncy signal is divided into two-way medium-frequency pulse modulation signal 09-1,09-2 through second power splitter 42, and medium-frequency pulse modulation signal 09-1 is sent to the 4th amplifier 51-1 of amplitude adjusting module 5, gets into the first numerical-control attenuator 52-1, the 3rd numerical-control attenuator 53-1 then successively; Simultaneously; The first numerical-control attenuator 52-1, the 3rd numerical-control attenuator 53-1 receive sequential control instruction 05-1, and medium-frequency pulse modulation signal 09-1 obtains adjusted target analog intermediate frequency signal 11-1 and arrives the external signal processor after adjusting through distance, orientation amplitude; In like manner; Medium-frequency pulse modulation signal 09-2 is sent to the 5th amplifier 51-2; Get into second numerical-control attenuator, the 4th numerical-control attenuator 53-2 then successively, simultaneously, the second numerical-control attenuator 52-2, the 4th numerical-control attenuator 53-2 receive sequential control instruction 05-2; Medium-frequency pulse modulation signal 09-2 obtains adjusted analog intermediate frequency signal 11-2 and arrives outside signal processor after adjusting through distance, orientation amplitude.
Under the rf-mode, the 31 couples of FPGA 32 of control panel in the control display module 3 send signal, and FPGA 32 inputs to outside frequency synthesizer with sequential control instruction 07, and frequency synthesizer receives sequential control instruction 07 back output two-way local oscillation signal F
L(being signal 08-1 and 08-2); And local oscillation signal 08-1 sent to the first frequency mixer 61-1 of A mixing and filtering module 6-1; Local oscillation signal 08-2 is sent to the second frequency mixer 61-2 of B mixing and filtering module 6-2; Simultaneously, the first frequency mixer 61-1 receives the adjusted analog intermediate frequency signal f from the 3rd numerical-control attenuator 53-1 output among the A amplitude adjusting module 5-1
A(being signal 06-1), the second frequency mixer 61-2 receive the adjusted analog intermediate frequency signal f from the 4th numerical-control attenuator 53-2 output among the B amplitude adjusting module 5-2
B(being signal 06-2); First frequency mixer 61-1 output signal becomes the radiofrequency signal F of simulated target successively through the 6th amplifier 62-1 and the first wave filter 63-1
A(being signal 10-1); Second frequency mixer 61-2 output signal becomes the radiofrequency signal F of simulated target successively through the 7th amplifier 62-2 and the second wave filter 63-2
B(being signal 10-2), the radiofrequency signal 10-1 of simulated target, 10-2 are sent to outside radar receiver respectively.
Fig. 6 is the truth table graphic form made from the antenna True Data; The measurement data of real dress antenna averaged process truth table; Write the two-way numerical-control attenuator by control circuit FPGA real-time searching truth table and with instruction, the 3rd numerical-control attenuator 53-1, the 4th numerical-control attenuator 53-2 receive sequential control instruction 05-1 and the 05-2 that control display module 3 sends, to adjusting synchronously from the signal of the first numerical-control attenuator 52-1, the 4th numerical-control attenuator 52-2; This mode is utilized the principle than width of cloth angle measurement; Simulate the real-time range value of target, thereby obtain target azimuth information, among the figure at adjacent antenna A, B; A road pad value curve simulation A road antenna radiation pattern, B road pad value curve simulation B road antenna radiation pattern.
The present invention directly exports one and contains moving target Doppler frequency f through the deep development to the DDS function
dAnd apart from the time delay t that causes
rMedium-frequency pulse modulation signal f
p, utilize principle to write two-way attenuator, f then in real time simultaneously with the truth table that the antenna True Data is made than width of cloth angle measurement
pMerit divides two-way to accomplish the simulation of target azimuth information through the two-way attenuator.Therefore, method circuit of the present invention is simple, and the output signal spectrum index is good, does not have the interference of unwanted sideband information, and simulate effect is near actual user mode.
Claims (7)
1. a Pulse-compression Radar intermediate frequency radio frequency general target simulator is characterized in that, comprises power module (1), reference source generation module (2), control display module (3), analog intermediate frequency signal generation module (4), amplitude adjusting module and mixing and filtering module; Amplitude adjusting module is divided into A amplitude adjusting module (5-1) and B amplitude adjusting module (5-2) two sub-module; The mixing and filtering module is divided into A mixing and filtering module (6-1) and B mixing and filtering module (6-2) two sub-module; Wherein, Power module (1) connects all the other each modules; Reference source generation module (2) connects control display module (3), analog intermediate frequency signal generation module (4) respectively, and control display module (3) connects analog intermediate frequency signal generation module (4), A amplitude adjusting module (5-1), B amplitude adjusting module (5-2) respectively; The output terminal of analog intermediate frequency signal generation module (4) connects A amplitude adjusting module (5-1) and B amplitude adjusting module (5-2) respectively; The output terminal of A amplitude adjusting module (5-1) connects A mixing and filtering module (6-1), and the output terminal of B amplitude adjusting module (5-2) connects B mixing and filtering module (6-2).
2. Pulse-compression Radar intermediate frequency radio frequency general target simulator as claimed in claim 1; It is characterized in that; Described reference source generation module (2) comprises constant-temperature crystal oscillator (21), first power splitter (22), first amplifier (23), second amplifier (24), the 3rd amplifier (25); Wherein, the output terminal of said constant-temperature crystal oscillator connects said first power splitter (22), and three road output terminals of first power splitter (22) connect said first amplifier (23), second amplifier (24) and the 3rd amplifier (25) respectively;
Described control display module (3) comprises control panel (31), FPGA (32) and display screen (33), and said control panel (31), FPGA (32) and display screen (33) link to each other successively;
Described analog intermediate frequency signal generation module (4) comprises DDS chip (41) and second power splitter (42); The output terminal of said DDS chip connects said second power splitter (42);
Said A amplitude adjusting module (5-1) is by the 4th amplifier (51-1), first numerical-control attenuator (52-1); The 3rd numerical-control attenuator (53-1) links to each other successively and constitutes; Said B amplitude adjusting module (5-2) is by the 5th amplifier (51-2), second numerical-control attenuator (52-2), and the 4th numerical-control attenuator (53-2) links to each other successively and constitutes;
Said A mixing and filtering module (6-1) is by first frequency mixer (61-1), the 6th amplifier (62-1) and first wave filter (63-1) formation that links to each other successively; B mixing and filtering module (6-2) is by second frequency mixer (61-2), the 7th amplifier (62-2) and second wave filter (63-2) formation that links to each other successively;
Wherein, the output terminal of first amplifier (23) is connected to outside signal processor as the outside output of reference signal, and the output terminal of second amplifier (24) connects the FPGA (32) of control display module (3); The output terminal of the 3rd amplifier (25) connects the DDS (41) of intermediate frequency simulated target signal generator module (4);
The output terminal of the FPGA (32) of control display module (3) connects the DDS (41) of intermediate frequency simulated target signal generator module (4), first numerical-control attenuator (52-1) of amplitude adjusting module respectively; The 3rd numerical-control attenuator (53-1), second numerical-control attenuator (52-2), the frequency synthesizer of the 4th numerical-control attenuator (53-2), outside and outside signal processor;
The output terminal of second power splitter (42) of intermediate frequency simulated target signal generator module (4) connects the 4th amplifier (51-1) and the 5th amplifier (51-2) in the amplitude adjusting module respectively;
The output terminal of the 3rd numerical-control attenuator (53-1) of amplitude adjusting module connects the signal input end of intermediate frequency of first frequency mixer (61-1) in the A mixing and filtering module (6-1), and the output terminal of the 4th numerical-control attenuator (53-2) connects the signal input end of intermediate frequency of second frequency mixer (61-2) in the B mixing and filtering module (6-2); In addition, the 3rd numerical-control attenuator (53-1), the 4th numerical-control attenuator (53-2) connect outside signal processor respectively;
The output terminal of outside frequency synthesizer is connected respectively to first frequency mixer (61-1) of mixing and filtering module and the RF signal input end of second frequency mixer (61-2); In addition, the output terminal of first wave filter (63-1) and second wave filter (63-2) is connected outside radar receiver respectively.
3. Pulse-compression Radar intermediate frequency radio frequency general target simulator as claimed in claim 2; It is characterized in that; Described constant-temperature crystal oscillator (21) is selected SOXO18-A100M for use; First power splitter (22) is selected AD4PS-1+ for use, and first amplifier (23), second amplifier (24), the 3rd amplifier (25) are all selected HMC479MP86E for use.
4. Pulse-compression Radar intermediate frequency radio frequency general target simulator as claimed in claim 2 is characterized in that described FPGA (32) adopts EP1C6T144I7N, and display screen (33) adopts the monochromatic OLED screen of 128*64 pixel.
5. Pulse-compression Radar intermediate frequency radio frequency general target simulator as claimed in claim 2 is characterized in that described DDS chip (41) is selected AD9854ASQ for use, and second power splitter (42) is selected the power splitter of ADP-2-1W+ for use.
6. Pulse-compression Radar intermediate frequency radio frequency general target simulator as claimed in claim 2; It is characterized in that described first numerical-control attenuator (52-1), second numerical-control attenuator (52-2), the 3rd numerical-control attenuator (53-1) and the 4th numerical-control attenuator (53-2) all adopt 6 figure place controlling attenuation device HMC542LP4E.
7. Pulse-compression Radar intermediate frequency radio frequency general target simulator as claimed in claim 2 is characterized in that described frequency mixer all adopts HMC175MS8E, wave filter all adopts-and the BPF. of 1dB bandwidth 120MHz.
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| CN112230190A (en) * | 2020-09-29 | 2021-01-15 | 北京环境特性研究所 | Target RCS phase calibration method aiming at target placement position error |
| CN112230190B (en) * | 2020-09-29 | 2023-12-22 | 北京环境特性研究所 | Target RCS phase calibration method aiming at target placement position error |
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