CN102361445B - High precision protocol pulse generator based on digital frequency synthesizer - Google Patents

Abstract

The invention relates to a high-accuracy protocol pulse generator based on a digital frequency synthesizer. The high-accuracy protocol pulse generator comprises the digital frequency synthesizer, an adder and a digital signal output interface, wherein a clock frequency generated by the digital frequency synthesizer is transmitted to the digital signal output interface, and simultaneously phase information corresponding to the clock frequency generated by the digital frequency synthesizer is transmitted to the adder; the adder transmits the phase information corresponding to the clock frequency generated by the digital frequency synthesizer and phase information of an externally input signal to the digital signal output interface after performing an add operation on the phase information corresponding to the clock frequency generated by the digital frequency synthesizer and the phase information of the externally input signal; and the digital signal output interface positions a pulse according to a rising edge and a falling edge of a digital signal to update the signal output. The high-accuracy protocol pulse generator based on the digital frequency synthesizer improves the structure of a conventional digital frequency synthesizer, can singly configure the phase information according to a protocol, can accurately set a clock frequency and advance or delay information relative to a clock for each digital signal, and is less in resource consumption and simple in structure.

Description

High precision protocol pulse generator based on digital frequency synthesizer

technical field

The invention relates to a protocol pulse generator, which is suitable for generating synchronous digital signals with complex protocols requiring high precision in frequency and phase.

Background technique

With the continuous development of integrated circuit technology, the protocols between chips, boards and stand-alone devices are becoming more and more complex and faster. For protocol implementation and protocol testing, a method is needed to realize protocol pulses with high frequency accuracy and phase accuracy.

The most basic digital frequency synthesizer is an accumulator. The width and operating frequency of the accumulator determine the frequency accuracy and phase accuracy generated by the digital frequency synthesizer. As shown in Figure 1, a general digital frequency synthesizer consists of a frequency control word register, an accumulation register and an adder. The width of the accumulation register and the clock frequency determine the accuracy of the signal frequency generated by the digital frequency synthesizer. Assuming that the width of the accumulation register is N, the clock frequency of the frequency synthesizer is f, and the frequency control word is FCW, then the generated clock frequency f _clk is:

${\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; clk</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; \&CenterDot;</span>\mathrm{<span\; class="notranslate">\; FCW</span>}}{{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; N</span>}}}$

Protocol pulses generally contain multiple digital signals, and general digital frequency synthesizers can only generate one frequency signal, which cannot implement complex protocols.

Contents of the invention

The technical solution of the invention is to overcome the deficiencies of the prior art and provide a complex protocol pulse generator with high frequency and phase precision.

The technical solution of the present invention is: a high-precision protocol pulse generator based on a digital frequency synthesizer, including a digital frequency synthesizer, also including R adders and a digital signal output interface, and the clock frequency generated by the digital frequency synthesizer is sent to Digital signal output interface, and the phase information corresponding to the clock frequency generated by the digital frequency synthesizer is sent to R adders respectively; among the R adders, each adder will generate the phase information corresponding to the clock frequency generated by the digital frequency synthesizer The information is added to the phase information of an externally input signal and then sent to the digital signal output interface; the digital signal output interface samples the highest output bits of the R adders. For any one of the R signals, the digital signal output interface Use the highest bit sigN_nco of the current clock cycle and the highest bit sigN_nco_l of the previous clock cycle to generate a digital signal positioning pulse including a rising edge and a falling edge. According to the digital signal positioning pulse, the digital signal output interface is on the corresponding rising edge and falling edge Output the phase information contained in the external input signal; the method for determining the rising edge sigN_p of the digital signal is that sigN_nco is 1 and sigN_nco_l is 0, and the method for determining the falling edge sigN_n of the digital signal is that sigN_nco is 0 and sigN_nco_l is 1.

The phase information of the external input signal has one sign bit more than that of the accumulating register, which represents whether the phase of the input signal is ahead or delayed with respect to the clock frequency generated by the digital frequency synthesizer.

Compared with the prior art, the present invention has the advantages that: the present invention improves the structure of the traditional digital frequency synthesizer, adds a phase adder corresponding to each signal, and can separately configure the phase information according to the protocol. Compared with traditional digital frequency synthesizers, only adders and registers equal to the number of protocol signals are added, with less resource consumption and a simplified structure, realizing a high-precision protocol pulse generator. The invention can generate, multi-signal, and protocol pulse with complex phase information, and can accurately set the clock frequency and the advance or delay information of each digital signal relative to the clock.

Description of drawings

Fig. 1 is a structural diagram of a traditional digital frequency synthesizer;

Fig. 2 is a structural diagram of the protocol pulse generator of the present invention;

Figure 3 is a timing diagram of each signal inside the protocol pulse generator.

Detailed ways

As shown in Figure 2, the protocol pulse generator of the present invention only adds an adder on the basis of a traditional digital frequency synthesizer, can realize a synchronous digital signal protocol with any number of signals, and has high frequency accuracy and phase accuracy.

1. Use a digital frequency synthesizer to accurately phase the analog signal and generate a clock signal with an accurate frequency.

Assuming that the width of the accumulation register is N, the clock frequency of the frequency synthesizer is f, and the frequency control word is FCW, then the generated clock frequency f _clk is:

${\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; clk</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; \&CenterDot;</span>\mathrm{<span\; class="notranslate">\; FCW</span>}}{{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; N</span>}}}$

In order to improve the precision of generated signals, the width N and clock frequency f of the accumulation register should be as high as possible, but too high N and f will increase resource consumption and design difficulty. The digital frequency synthesizer has a frequency accuracy of f/2 ^N and a time resolution of 2/f. In practical applications, N and f are determined according to the frequency accuracy requirements of the protocol clock and the phase accuracy requirements of other protocol signals.

2. Use the clock phase information generated by the digital frequency synthesizer to add the phase information input of other signals in the protocol to obtain the phase information of other signals.

As shown in FIG. 2, the external input includes a clock frequency input (N bits) and a phase information (N+1 bits) input. The clock frequency input is the frequency control word of the digital frequency synthesizer, which is determined by the clock requirement of the agreement. The input of other phase information is the difference between other signals relative to the clock phase (determined according to the requirements of the generated signal), which is N+1 bits, one more sign bit than the accumulation register, representing whether the phase of the signal is advanced or delayed on the clock signal.

Use the adder to sum the output of the accumulation register and the phase information input to obtain the phase information of the signal to be generated. The adder here needs to add or subtract the phase in the accumulator according to the highest bit of the input phase information.

Multiple phase information inputs and adders for external input can generate complex phases with advanced or delayed protocol pulse signals.

3. According to the phase information and protocol of each signal, a protocol signal is generated.

Figure 3 is a timing diagram of each signal.

Use the highest bit of the accumulation register in the frequency synthesizer as the clock (nco_clk) to output to the outside. This signal is the clock. The digital signal output interface receives each signal input (signal 1 input, signal 2 input, etc., sigN_in in Figure 3) generated by an external protocol generator. These signals are synchronized with the clock of the protocol signal without phase information.

The digital signal output interface samples the highest bit of each signal phase input, and for each signal, uses the highest bit of the current clock cycle (sigN_nco) and the highest bit of the previous clock cycle (sigN_nco_l) to generate the rising edge of the digital signal (sigN_p) and falling edge (sigN_n) positioning pulse, the determination method of rising edge and falling edge is as follows:

sigN_p = sigN_nco is 1 and sigN_nco_l is 0,

sigN_n=sigN_nco is 0 and sigN_nco_l is 1;

According to the rising edge and falling edge positioning pulse of each signal, the digital signal output interface updates the input of the external protocol generator to the signal output interface (sigN) at the corresponding rising edge and falling edge.

The content that is not described in detail in the description of the present invention belongs to the well-known technology of those skilled in the art.

Claims (2)

1. A high-precision protocol pulse generator based on a digital frequency synthesizer, including a digital frequency synthesizer, is characterized in that: it also includes R adders and a digital signal output interface, and R is the output signal number of the pulse generator; The clock frequency generated by the frequency synthesizer is sent to the digital signal output interface, and the phase information corresponding to the clock frequency generated by the digital frequency synthesizer is sent to R adders respectively; among the R adders, each adder will be connected with the digital frequency The phase information corresponding to the clock frequency generated by the synthesizer is added to the phase information of an external input signal and then sent to the digital signal output interface; the digital signal output interface samples the highest output bits of the R adders. For the R signal Any one of the channels, the digital signal output interface uses the highest bit sigN_nco of the current clock cycle and the highest bit sigN_nco_l of the previous clock cycle to generate a digital signal positioning pulse including a rising edge and a falling edge, position the pulse according to the digital signal, and output the digital signal The interface outputs the phase information contained in the external input signal at the corresponding rising and falling edges; the rising edge sigN_p of the digital signal is determined as sigN_nco is 1 and sigN_nco_l is 0, and the falling edge of the digital signal sigN_n is determined as sigN_nco is 0 and sigN_nco_l is 1. 2. the high-accuracy protocol pulse generator based on digital frequency synthesizer according to claim 1, is characterized in that: the phase information of described external input signal has one sign bit more than the accumulation register in the digital frequency synthesizer, Indicates whether the phase of the input signal is leading or lagging the clock frequency generated by the digital frequency synthesizer.

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