CN102354686A

CN102354686A - 60V high-side LDNMOS (Lateral Dispersion N-channel Metal Oxide Semiconductor) structure and manufacturing method thereof

Info

Publication number: CN102354686A
Application number: CN201110366064XA
Authority: CN
Inventors: 刘建华; 吴晓丽
Original assignee: Shanghai Advanced Semiconductor Manufacturing Co Ltd
Current assignee: Shanghai Advanced Semiconductor Manufacturing Co Ltd
Priority date: 2011-11-17
Filing date: 2011-11-17
Publication date: 2012-02-15

Abstract

The invention discloses a 60V high-side LDNMOS (Lateral Dispersion N-channel Metal Oxide Semiconductor) structure and a manufacturing method thereof. The method comprises the following steps of: providing a P type silicon substrate on which an N type buried layer and a P type epitaxial layer are sequentially formed; injecting phosphor into the P type epitaxial layer, dispersing the phosphor at a high temperature to obtain a low-concentration high-voltage N trap; forming a plurality of field oxide isolations on the P type epitaxial layer; exposing a partial pattern in a source region of the LDNMOS, injecting boron and arsenic, and dispersing at the high temperature to obtain a P type body region; forming a gate oxide layer on the P type epitaxial layer between the P type body region and the field oxide isolation, wherein the gate oxide layer is connected with the gate oxide layer with the P type body region and is adjacent to the field oxide isolations; carrying out thermal growth of a polycrystalline silicon gate on the gate oxide layer and on the adjacent field oxide isolations to form a polycrystalline grid; by taking the polycrystalline grid as an aligning layer, respectively forming a source electrode, a drain electrode and a P type body region leading-out end in the source region and a drain region of the LDNMOS, wherein the source electrode and the P type body region leading-out end are arranged in the P type body region. The working voltages of both source electrode and drain electrode of the high-side LDNMOS are 60 V, and the high-side LDNMOS is compatible with the low-side LDNMOS in process.

Description

60V flash LDNMOS structure and manufacturing approach thereof

Technical field

The present invention relates to technical field of semiconductor device, specifically, the present invention relates to a kind of 0.35 μ m 60V flash LDNMOS structure and manufacturing approach thereof.

Background technology

BCD technology is a kind of advanced person's monolithic integrated technique technology, is the excellent selection of IC manufacturing process such as power management, display driver, automotive electronics, has vast market prospect.From now on, BCD technology will be popular research field in recent years towards high pressure, high power, three direction differentiation of high density development.BCD technology is produced on bipolar device and cmos device on the same chip simultaneously.It combines the advantage of bipolar device high transconductance, strong load driving ability and the high and low power consumption of cmos device integrated level, and it is made up for each other's deficiencies and learn from each other, performance advantage separately.What is more important, BCD technology is integrated DMOS power device, the DMOS device can be worked under switching mode, and power consumption is extremely low, does not need expensive encapsulation and cooling system just can pass to load with high-power.Low-power consumption is one of major advantage of BCD technology, and the BCD manufacturing process of integrating can significantly reduce power dissipation, improves systematic function, saves the encapsulation overhead of circuit, and has better reliability.

Power output stage DMOS pipe is the core of this type of circuit, often occupies 1/2～2/3 of entire chip area, and it is the key of whole integrated circuit.DMOS and cmos device similar, electrode such as also active, leakage, grid, but the drain terminal puncture voltage is high.The application requirements source termination that DMOS has has load rather than ground connection, and this application not only requires drain terminal can bear high pressure, and the source end also will bear high pressure, Here it is flash (High-side) LDNMOS device.Usually the many of usefulness is low limit (Low-side) LDNMOS device, and this technology and structure are relatively simple, and the source end is in the same place with the ground short circuit, at this moment the source termination zero potential of LDNMOS.But the source termination of flash LDNMOS device has load, and the source end is also wanted to bear high pressure, compare with low limit LDNMOS structure, and the structure of this device and technology more complicated, and good inadequately with the processing compatibility of low limit LDNMOS.

Summary of the invention

Technical problem to be solved by this invention provides a kind of 60V flash LDNMOS structure and manufacturing approach thereof, and grid voltage is 3.3V or 5V, and the operating voltage of source electrode and drain electrode all is the 60V high pressure, and the easy realization of technology, with low limit LDNMOS process compatible.

For solving the problems of the technologies described above, the present invention provides a kind of manufacturing approach of 60V flash LDNMOS structure, comprises step:

P type silicon substrate is provided, injects formation n type buried layer and hot growing P-type epitaxial loayer thereon successively;

High energy injects a N type impurity in said P type epitaxial loayer, and forms the high pressure N trap of low concentration through High temperature diffusion, as the high pressure trap of said flash LDNMOS structure and the self-isolation of high tension apparatus;

Secundum legem CMOS technology is carried out location oxidation of silicon process on said P type epitaxial loayer, make a plurality of oxidations of device/circuit part and isolate;

The part graph exposure in the source region of said flash LDNMOS structure, high energy injects p type impurity and the 2nd N type impurity, and forms P type tagma through High temperature diffusion, as the raceway groove of said flash LDNMOS structure;

On the said P type epitaxial loayer between a said P type tagma and the oxidation isolation, form gate oxide, said gate oxide is connected with said P type tagma and isolates adjacency with said oxidation;

Said gate oxide and adjacent field oxidation thereof in said flash LDNMOS structure are isolated hot growing polycrystalline silicon grid and are formed the polycrystalline grid, form the polycrystalline grid field plate in the drain region of said flash LDNMOS structure simultaneously;

Secundum legem CMOS technology; With said polycrystalline grid is alignment; In the source region of said flash LDNMOS structure and drain region graph exposure successively, form source electrode, drain electrode and P type tagma exit respectively, said source electrode and P type tagma exit are arranged in said P type tagma.

Alternatively, form said source electrode, drain electrode and P type tagma exit and also comprise step afterwards:

Said flash LDNMOS structure is carried out rapid thermal treatment process.

Alternatively, a said N type impurity is phosphorus, and said the 2nd N type impurity is arsenic.

Alternatively, said p type impurity is a boron.

Optionally, the gate oxide layer has a thickness of

For solving the problems of the technologies described above, correspondingly, the present invention also provides a kind of 60V flash LDNMOS structure, comprising:

N type buried layer is arranged in P type silicon substrate, is formed with P type epitaxial loayer on the said P type silicon substrate;

The high pressure N trap of low concentration is positioned on the said n type buried layer, among the said P type epitaxial loayer, as the high pressure trap of said flash LDNMOS structure and the self-isolation of high tension apparatus;

A plurality of oxidations are isolated, and are distributed in the surface of said P type epitaxial loayer;

P type tagma is arranged in said high pressure N trap, as the raceway groove of said flash LDNMOS structure;

Gate oxide, on the said P type epitaxial loayer between a said P type tagma and the oxidation isolation, it is connected with said P type tagma and isolates adjacency with said oxidation;

The polycrystalline grid, the said gate oxide and the adjacent field oxidation thereof that are positioned at said flash LDNMOS structure are isolated;

Source electrode, drain electrode and P type tagma exit are distributed in the surface of said P type epitaxial loayer, and said source electrode and P type tagma exit are arranged in said P type tagma.

Optionally, the gate oxide layer has a thickness of

Compared with prior art, the present invention has the following advantages:

The grid voltage of flash LDNMOS structure of the present invention is 3.3V or 5V, and the operating voltage of source electrode and drain electrode all is the 60V high pressure, with low limit LDNMOS process compatible.Only need to increase technology level of n type buried layer, and optimize the thickness of P type epitaxial loayer and the structure of source end, reach the safety operation area high pressure that the source end also can bear 60V, puncture voltage is greater than 80V, and conducting resistance is less than 60mohm.mm ²The present invention also adopts P type epitaxial loayer and high pressure N trap to realize self-isolation, and technology realizes that easily the polycrystalline grid forms field plate structure near the field oxidation isolation the drain electrode simultaneously.The present invention has great role to the development and the extensive use of high voltage power device.

Description of drawings

The above and other features of the present invention, character and advantage will become more obvious through the description below in conjunction with accompanying drawing and embodiment, wherein:

Fig. 1 is the flow chart of manufacturing approach of the 60V flash LDNMOS structure of one embodiment of the invention;

Fig. 2 to Fig. 8 is the cross-sectional view of manufacture process of the 60V flash LDNMOS structure of one embodiment of the invention.

Embodiment

Below in conjunction with specific embodiment and accompanying drawing the present invention is described further; Set forth more details in the following description so that make much of the present invention; But the present invention obviously can implement with multiple this description ground alternate manner that is different from; Those skilled in the art can do similar popularization, deduction according to practical situations under the situation of intension of the present invention, therefore should be with content constraints protection scope of the present invention of this specific embodiment.

Fig. 1 is the flow chart of manufacturing approach of the 60V flash LDNMOS structure of one embodiment of the invention.As shown in Figure 1, this manufacturing approach can comprise:

Execution in step S101 provides P type silicon substrate, injects successively thereon to form n type buried layer and hot growing P-type epitaxial loayer;

Execution in step S102, high energy injects a N type impurity in P type epitaxial loayer, and forms the high pressure N trap of low concentration through High temperature diffusion, as the high pressure trap of flash LDNMOS structure and the self-isolation of high tension apparatus;

Execution in step S103, secundum legem CMOS technology is carried out location oxidation of silicon process on P type epitaxial loayer, make a plurality of oxidations of device/circuit part and isolate;

Execution in step S104, the part graph exposure in the source region of flash LDNMOS structure, high energy injects p type impurity and the 2nd N type impurity, and forms P type tagma through High temperature diffusion, as the raceway groove of flash LDNMOS structure;

Execution in step S105 forms gate oxide on the P type epitaxial loayer between a P type tagma and the oxidation isolation, gate oxide is connected with P type tagma and isolates adjacency with the field oxidation;

Execution in step S106 isolates hot growing polycrystalline silicon grid and forms the polycrystalline grid in the gate oxide and the adjacent field oxidation thereof of flash LDNMOS structure, forms the polycrystalline grid field plate in the drain region of flash LDNMOS structure simultaneously;

Execution in step S107; Secundum legem CMOS technology is alignment with the polycrystalline grid, in the source region of flash LDNMOS structure and drain region graph exposure successively; Form source electrode, drain electrode and P type tagma exit respectively, source electrode and P type tagma exit are arranged in P type tagma.

The embodiment of the manufacturing approach of 60V flash LDNMOS structure

Fig. 2 to Fig. 8 is the cross-sectional view of manufacture process of the 60V flash LDNMOS structure of one embodiment of the invention.Wherein, the 60V flash LDNMOS structure 200 and the adjacent CMOS transistor 300 of present embodiment generally can form in 0.35 μ m BCD technology synchronously, and be compatible mutually with 60V high pressure BCD technology, so do to describe in the lump at this.In addition, these accompanying drawings all only as an example, it is not to be to draw according to the condition of equal proportion, and should not limit as the protection range formation to the actual requirement of the present invention with this.

As shown in Figure 2, P type silicon substrate 201 is provided, this P type silicon substrate 201 can be divided into left and right sides two parts, and left part is the zone of CMOS transistor 300, and right portions is the zone of 60V flash LDNMOS structure 200.On this P type silicon substrate 201, inject successively and form n type buried layer 202 and hot growing P-type epitaxial loayer 203.

As shown in Figure 3, high energy injects a N type impurity in P type epitaxial loayer 203, phosphorus for example, and form the high pressure N trap 204 of low concentration through High temperature diffusion, as the high pressure trap of flash LDNMOS structure 200 and the self-isolation of high tension apparatus.The follow-up twin well process that can carry out CMOS transistor 300 promptly forms N trap 301 and P trap 302 (twin well process of CMOS transistor 300 also can form) before forming high pressure N trap 204.

As shown in Figure 4, secundum legem CMOS technology is carried out location oxidation of silicon process on P type epitaxial loayer 203, makes a plurality of oxidations of device/circuit part and isolates (LOCOS) 205.Simultaneously, go out the position of the N trap and the P trap of CMOS transistor 300 in the zone isolation of CMOS transistor 300.

As shown in Figure 5, the part graph exposure in the source region of flash LDNMOS structure 200, high energy injects p type impurity (for example boron) and the 2nd N type impurity (for example arsenic), and forms P type tagma 206 through High temperature diffusion, as the raceway groove of flash LDNMOS structure 200.

Shown in Figure 6, the P-type body region 206 and the field oxide 205 isolation between the P-type epitaxial layer 203 is formed on the gate oxide layer 207, a gate oxide layer 207 may have a thickness of

or so, and the P-type body region 206 is connected and with the adjacent field oxide isolation 205.Simultaneously, form the gate oxide of CMOS transistor 300 in the zone of CMOS transistor 300.

As shown in Figure 7, isolate on 205 hot growing polycrystalline silicon grid and form polycrystalline grid 208, form the polycrystalline grid field plate in the drain region of flash LDNMOS structure 200 simultaneously in the gate oxide 207 of flash LDNMOS structure 200 and adjacent field oxidation thereof.Simultaneously, form the grid of CMOS transistor 300 in the zone of CMOS transistor 300.

As shown in Figure 8, secundum legem CMOS technology is alignment with polycrystalline grid 208, in the source region of flash LDNMOS structure 200 and drain region graph exposure successively, forms source electrode 211, drain electrode 212 and P type tagma exit 213 respectively.Wherein, source electrode 211 is arranged in P type tagma 206 with P type tagma exit 213,212 is arranged in high pressure N trap 204 and drain.Simultaneously, form the source electrode and the drain electrode of CMOS transistor 300 in the zone of CMOS transistor 300.

In the present embodiment, also comprise after formation source electrode 211, drain electrode 212 and the P type tagma exit 213 flash LDNMOS structure 200 is carried out rapid thermal treatment process (RTA), to reduce contact resistance.

The embodiment of 60V flash LDNMOS structure

The 0.35 μ m 60V flash LDNMOS structure that the present invention proposes is the overlay region and the P type epitaxy layer thickness in high pressure N trap and P type tagma through the source configuration of improving LDNMOS; Increase n type buried layer structure forms flash LDNMOS below the LDNMOS structure, and the source electrode of this flash LDNMOS can connect load and bear high pressure.

Be illustrated in figure 8 as the cross-sectional view of the 60V flash LDNMOS structure of one embodiment of the invention.As shown in Figure 8, the 60V flash LDNMOS structure 200 of present embodiment can be formed together with adjacent CMOS transistor 300.

This 60V flash LDNMOS structure 200 can comprise: the high pressure N trap 204 of P type silicon substrate 201, n type buried layer 202, P type epitaxial loayer 203, low concentration, a plurality of oxidation isolation 205, P type tagma 206, gate oxide 207, polycrystalline grid 208, source electrode 211, drain electrode 212 and P type tagma exits 213.Wherein, n type buried layer 202 is arranged in P type silicon substrate 201, is formed with P type epitaxial loayer 203 on the P type silicon substrate 201.The high pressure N trap 204 of low concentration is positioned on the n type buried layer 202, among the P type epitaxial loayer 203, as the high pressure trap of flash LDNMOS structure 200 and the self-isolation of high tension apparatus.205 surfaces that are distributed in P type epitaxial loayer 203 are isolated in a plurality of oxidations.P type tagma 206 is arranged in high pressure N trap 204, as the raceway groove of flash LDNMOS structure 200.Gate oxide layer 207 has a thickness of

206 of the P-type body region 205 and the field oxide isolation between the P-type epitaxial layer 203, the P-type body region which is connected to 206 and 205 adjacent to the field oxide isolation.Polycrystalline grid 208 is positioned at the gate oxide 207 of flash LDNMOS structure 200 and adjacent field oxidation is isolated on 205.The surface that source electrode 211, drain electrode 212 and P type tagma exit 213 are distributed in P type epitaxial loayer 203, source electrode 211 is arranged in P type tagma 206 with P type tagma exit 213.

Though the present invention with preferred embodiment openly as above, it is not to be used for limiting the present invention, and any those skilled in the art are not breaking away from the spirit and scope of the present invention, can make possible change and modification.Therefore, every content that does not break away from technical scheme of the present invention, according to technical spirit of the present invention to any modification, equivalent variations and modification that above embodiment did, within the protection range that all falls into claim of the present invention and defined.

Claims

1. the manufacturing approach of a 60V flash LDNMOS structure (200) comprises step:

P type silicon substrate (201) is provided, injects formation n type buried layer (202) and hot growing P-type epitaxial loayer (203) thereon successively;

High energy injects a N type impurity in said P type epitaxial loayer (203), and forms the high pressure N trap (204) of low concentration through High temperature diffusion, as the high pressure trap of said flash LDNMOS structure (200) and the self-isolation of high tension apparatus;

Secundum legem CMOS technology is carried out location oxidation of silicon process on said P type epitaxial loayer (203), make a plurality of oxidations of device/circuit part and isolate (205);

The part graph exposure in the source region of said flash LDNMOS structure (200), high energy injects p type impurity and the 2nd N type impurity, and forms P type tagma (206) through High temperature diffusion, as the raceway groove of said flash LDNMOS structure (200);

Said P type epitaxial loayer (203) between a said P type tagma (206) and an oxidation isolation (205) is gone up and is formed gate oxide (207), and said gate oxide (207) is connected with said P type tagma (206) and isolates (205) adjacency with said oxidation;

Said gate oxide (207) and adjacent field oxidation isolation (205) thereof in said flash LDNMOS structure (200) are gone up hot growing polycrystalline silicon grid and are formed polycrystalline grid (208), form the polycrystalline grid field plate in the drain region of said flash LDNMOS structure (200) simultaneously;

Secundum legem CMOS technology; With said polycrystalline grid (208) is alignment; In the source region of said flash LDNMOS structure (200) and drain region graph exposure successively; Form source electrode (211), drain electrode (212) and P type tagma exit (213) respectively, said source electrode (211) and P type tagma exit (213) are arranged in said P type tagma (206).

2. manufacturing approach according to claim 1 is characterized in that, forms said source electrode (211), drain electrode (212) and P type tagma exit (213) and also comprises step afterwards:

Said flash LDNMOS structure (200) is carried out rapid thermal treatment process.

3. manufacturing approach according to claim 2 is characterized in that, a said N type impurity is phosphorus, and said the 2nd N type impurity is arsenic.

4. manufacturing approach according to claim 3 is characterized in that, said p type impurity is a boron.

5 as claimed in any of claims 1 to 4 for producing one of claims, characterized in that said gate oxide layer (207) has a thickness of

6. a 60V flash LDNMOS structure (200) comprising:

N type buried layer (202) is arranged in P type silicon substrate (201), is formed with P type epitaxial loayer (203) on the said P type silicon substrate (201);

The high pressure N trap (204) of low concentration is positioned on the said n type buried layer (202), among the said P type epitaxial loayer (203), as the high pressure trap of said flash LDNMOS structure (200) and the self-isolation of high tension apparatus;

(205) are isolated in a plurality of oxidations, are distributed in the surface of said P type epitaxial loayer (203);

P type tagma (206) is arranged in said high pressure N trap (204), as the raceway groove of said flash LDNMOS structure (200);

Gate oxide (207) is positioned at a said P type tagma (206) and an oxidation and isolates on the said P type epitaxial loayer (203) between (205), and it is connected with said P type tagma (206) and isolates (205) adjacency with said oxidation;

Polycrystalline grid (208), the said gate oxide (207) and the adjacent field oxidation thereof that are positioned at said flash LDNMOS structure (200) are isolated on (205);

Source electrode (211), drain electrode (212) and P type tagma exit (213) are distributed in the surface of said P type epitaxial loayer (203), and said source electrode (211) and P type tagma exit (213) are arranged in said P type tagma (206).

As claimed in claim 6, wherein the high-side LDNMOS 60V structure (200), characterized in that said gate oxide layer (207) has a thickness of