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CN102347219A - Method for forming composite functional material structure - Google Patents

Method for forming composite functional material structure Download PDF

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Publication number
CN102347219A
CN102347219A CN2011102856484A CN201110285648A CN102347219A CN 102347219 A CN102347219 A CN 102347219A CN 2011102856484 A CN2011102856484 A CN 2011102856484A CN 201110285648 A CN201110285648 A CN 201110285648A CN 102347219 A CN102347219 A CN 102347219A
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wafer
ion
donor wafer
annealing
functional material
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张轩雄
杨帆
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Abstract

The invention discloses a method for forming a composite functional material structure. The method comprises the following steps: step A, high-energy ions are implanted into the surface layer of a donor wafer, and a fragile area is formed at the position of the ion implantation projection range, wherein the energy of the ion implantation is between 60KeV and 500 KeV; step B, bonding the donor wafer and the substrate wafer to form a composite structure comprising the donor wafer and the substrate wafer; and step C, annealing the bonded composite structure to enable the donor wafer to be peeled off in the fragile area, so that a donor wafer thin layer structure is attached to the surface of the substrate wafer to form a composite functional material structure. The invention adopts high-energy ion implantation, controls the projection range to be at a position farther away from the surface, and can obtain a better transfer thin layer by utilizing the peeling of the surface layer of the wafer even under the condition of few bonding defects, thereby improving the peeling efficiency and the quality and the performance of the transfer layer.

Description

Form the method for composite functional material structure
Technical field
The present invention relates to microelectronic industry components and parts preparing technical field, relate in particular to a kind of method that forms the composite functional material structure.
Background technology
Current semiconductor technology fast development; Device size is more and more littler; Circuit integrated more and more higher; The MOS device of silicon (Si) is owing to receive the constraint of self material property; In microelectric technique development instantly, shown significant limitation; Along with the integrated circuit characteristic size progressively is contracted to 45nm; Even 22nm; Body silicon MOS device a series of new problem occurred in various aspects such as device theory, device architecture and manufacture crafts, makes its power consumption, reliability and cost performance etc. receive very big influence.And other is like germanium (Ge), and graphite is rare, gallium nitride (GaN), and materials such as III-V compound have higher carrier mobility and better frequency power characteristic with respect to Si, are fit to be applied to microelectronic component and circuit more.While new structure such as SOI (Silicon On Insulator); GeOI (Germanium On Insulator); SSOI (strain-Silicon On Insulator); The appearance of SGeOI semiconductor-on-insulator structures such as (Silicon-Germanium On Insulator) can continue to continue the validity of Moore's Law.With respect to common aspect silicon, the novel semi-conductor structure has multiple advantage.Therefore, it is to have good prospect that this type of novel semiconductor material structure is construed to, and is counted as the excellent material structure of preparation integrated circuit of future generation.
In order to improve the charge stripping efficiency that injects ion and the quality of transfer layer, a kind of smart peeling technology (Smart-Cut) appearred in the nineties in last century.This technology is at first to be proposed and apply for a patent in 1991 by M.Bruel, and delivers academic article in nineteen ninety-five, is used to prepare soi structure at first.Up to the present captured nearly 80% the market share based on the SOI product of Smart-Cut technology.The Smart-Cut technology is mainly concerned with following consecutive steps: (a) the H ion is injected into the SiO that is coated with thermal oxide growth 2The wafer A of dielectric layer; (b) wafer A and wafer B are carried out bonding, process standard cleaning PROCESS FOR TREATMENT before the two wafer bondings; (c) handle through two Buwen's degree, the first step makes wafer A peel off, and second step is for strengthening the bond strength of A, B wafer; (d) polishing is carried out on the surface after separating, to reach the surface that conformance with standard requires.Smart-Cut makes the technical method of SOI with respect to other: the Si film thickness homogeneity that covers on the insulator is good, and crystal mass is good, and interface quality is good between layer and the layer, and the material structure performance is good.
The Smart-Cut technical development till now; Not only be confined to the Si sheet; Having become a kind of thin layer shifts; The current techique of structure preparation is particularly for not causing the complex function wafer material of high density of defects (because lattice constant does not match) to have very large advantage through epitaxy technology (like soi structure) or extension.At present,, expanded to Ge from the scope of research material, GaN and III-V compound etc., technological means has also had continuous change and progressive such as the ionic species that injects, and annealing in process process or the like has also had some variations.
Such as doping, unite injection for all improvement means, divide step annealing or the like, one of them most important reason is that Smart-Cut has strict thermal budget limitations for the annealing heat treatment of peeling off when taking place.Especially for GeOI, during the isostructural formation of SGeOI, (thermal coefficient of expansion is respectively Ge=5.8 * 10 because thermal expansion coefficient difference is big -6-1, Si=2.8 * 10 -6-1), when annealing temperature is too high for like Ge-Si bonding, Ge-SiO 2Strain even fracture will take place in bonding because degrees of expansion is different, make that the interface between bonding quality, crystal mass, layer and the layer becomes very poor, thereby influence architecture quality and performance.
Summary of the invention
(1) technical problem that will solve
For solving above-mentioned one or more problems, the invention provides a kind of method that forms the composite functional material structure, to form the composite functional material structure of high-quality.
(2) technical scheme
According to an aspect of the present invention, a kind of method that forms the composite functional material structure is provided.This method comprises: steps A, ion flow into the donor wafer top layer, inject the projected range position at ion and form vulnerable areas, and wherein, the energy that ion injects is between between the 60KeV to 500KeV; Step B carries out bonding with donor wafer and substrate wafer, forms the composite construction that comprises donor wafer and substrate wafer; Step C, the composite construction that forms behind the para-linkage carries out annealing in process, makes donor wafer peel off in vulnerable areas, thereby at substrate wafer surface attachment donor wafer laminate structure, forms the composite functional material structure.
Preferably, the present invention forms in the composite functional material structural approach, and in the steps A, ion injects projected range between between the 500nm to 5000nm.
Preferably, the present invention forms in the composite functional material structural approach, and in the steps A, the type of injecting ion is a kind of of following type: hydrogen ion injects separately, the helium ion injects separately, hydrogen-helium ion is united injection or boron-hydrogen ion is united injection.
Preferably, the present invention forms in the composite functional material structural approach, and in the steps A, the dosage that injects ion is between 1 * 10 16To 3 * 10 17Cm -2Between.
Preferably, the present invention forms in the composite functional material structural approach, and the substrate wafer material is a kind of in the following material: Si, glass, SiC, Ge or III-V compounds of group; The donor wafer material is a kind of in the following material: Ge, III-V compounds of group, GaN, AlN, Al 2O 3, ZnO, SiC, BaTiO 3, LaAlO 3Or diamond;
Preferably, the present invention forms in the composite functional material structural approach, before step B, also comprises: step B ', in one or more layers intermediate layer of substrate surface growth, this intermediate layer is as insulating barrier or bonding resilient coating.
Preferably, the present invention forms in the composite functional material structural approach, and the thickness in intermediate layer is between between the 80nm to 2000nm; The preparation method in intermediate layer is thermal oxidation or chemical vapor deposition and epitaxial method.
Preferably, the present invention forms in the composite functional material structural approach, also comprises before the step C: step C ', the composite construction that forms behind the para-linkage carry out preannealing to be handled, to strengthen the intensity of donor wafer and substrate wafer bonding.
Preferably, the present invention forms in the composite functional material structural approach, and among the step C ', the temperature of preannealing is between 150 ℃ to 250 ℃; Among the step C, the temperature of annealing in process is between 200 ℃ to 400 ℃; Preannealing is handled and annealing in process is carried out in same annealing furnace, and the vacuum ranges that annealing in process and preannealing are handled is between 10 -5Pa to 10 5Between the Pa.
Preferably, the present invention forms in the composite functional material structural approach, also comprises before the B: step B ", donor wafer and substrate wafer are cleaned and surface ion activation processing.
Preferably, the present invention forms in the composite functional material structural approach, also comprises after the C: step D, carry out polishing to the substrate wafer that contains the donor wafer laminate structure.
(3) beneficial effect
Within the specific limits; Ion implantation energy is high more; It is dark more to inject the degree of depth; Vulnerable areas is far away more apart from wafer surface; Then by ion inject the inner formed micro-crack of wafer can be when the annealing cross growth big more, help peeling off of corresponding wafer top layer more greatly according to fracture mechanics principle micro-crack, even under the situation that has minority bonding defective; Also can access better transfer thin layer, thus the efficient that raising is peeled off and the quality of transfer layer.And for the technology of material transfer, the material that needs to shift can not be too thick, otherwise the effect that just can not obtain shifting, the substrate wafer performance can reduce on the contrary, thereby has lost the meaning of transfer.Therefore; The present invention adopts within the specific limits, and high energy ion injects deeply; Preferably the energy of ion injection is between between the 60KeV to 500KeV; Thereby neither can or not cause the substrate wafer performance to reduce again owing to energy is too high owing to energy is crossed low efficient and the quality that has influenced stripping process.In addition, inject the energy height and also can cause cost to improve, keeping ions with proper to inject energy can also control cost.
Description of drawings
Fig. 1 carries the flow chart that embodiment forms the composite functional material structural approach for the present invention;
Fig. 2 a-Fig. 2 d is that the embodiment of the invention forms the chip architecture sketch map after each step of execution in the composite functional material structural approach;
Fig. 3 a-Fig. 3 d is that another embodiment of the present invention forms the chip architecture sketch map after each step of execution in the composite functional material structural approach;
Fig. 4 a-Fig. 4 d is that another embodiment of the present invention forms the chip architecture sketch map after each step of execution in the composite functional material structural approach.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, to further explain of the present invention.Though this paper can provide the demonstration of the parameter that comprises particular value, should be appreciated that parameter need not definitely to equal corresponding value, but can in acceptable error margin or design constraint, be similar to said value.
In an exemplary embodiment of the present invention, a kind of method that forms the composite functional material structure is disclosed.Fig. 1 forms the flow chart of composite functional material structural approach for the embodiment of the invention.As shown in Figure 1, present embodiment comprises the steps:
Step S102, ion flows into donor wafer, is specially:
The high energy ion kind is injected donor wafer, injects projected range through injecting energy control ion, near ion injects projected range, forms vulnerable areas; When ion injected, the source was various gaseous states or solid source, afterwards by ionization, quickened the back and injected wafer with ionic forms; The different types of ion of " ionic species " fingering row injects.
Wherein, the donor wafer material is Ge, III-V compounds of group, GaN, AlN, Al 2O 3, ZnO, SiC, BaTiO 3, LaAlO 3Or diamond.The injection atomic species is that H (hydrogen) ion injects separately, He (helium) ion injects separately, H (hydrogen)-He (helium) ion is united injection or B (boron)-H (hydrogen) ion is united injection.
Among the present invention, ion implantation energy is 60KeV-500KeV, and control is injected the degree of depth at 500nm-5000nm.The energy of ions that key of the present invention is to inject is than higher, and preferably the energy that injects of ion is between between the 60KeV to 500KeV, thereby both can under the prerequisite that guarantees transfer effect, improve and peel off quality, can also control cost.
For the implantation dosage of ion, if too low then more can not peel off, too high then big to material damage; Therefore to select low and suitable as far as possible; The scope of dosage is because the pairing optimal dosage of material different is also different, and preferably, the dosage that injects ion is between 1 * 10 16To 3 * 10 17Cm -2Between.
Step S104 carries out bonding with donor wafer and substrate wafer, is specially:
Donor wafer and substrate wafer are handled, and cleaning and removing is carried out bonding with donor wafer and substrate wafer then except that surface contaminant; Substrate wafer can be insulation wafers such as Si or glass.
The substrate wafer material is a kind of in the following material: Si, glass, SiC, Ge or III-V compounds of group; Can also be provided with the intermediate layer between substrate wafer and the donor wafer.Preferably, intermediate layer thickness is 80-2000nm, adopts method growths such as thermal oxidation or chemical vapor deposition and epitaxial; Concrete type of interlayer will describe in three follow-up embodiment.
Step S106, the structure behind the para-linkage is carried out double annealing heat treatment, is specially:
First step annealing in process is in order to strengthen bond strength; Second step made donor wafer peel off in vulnerable areas, thereby on substrate wafer, formed laminate structure; Double annealing is being carried out in same body of heater, and wherein, first step annealing temperature is 150-250 ℃, and the second step annealing temperature is 200-400 ℃.The vacuum ranges that the first step annealing in process and second step annealing are handled is between 10 -5Pa to 10 5Between the Pa.
Step S108 carries out surface treatment to the material after peeling off, and is specially:
For donor wafer after peeling off and the substrate wafer that contains laminate structure, the surface obtains remaining donor material and desired composite functional material structure through chemical mechanical polish process and Temperature Treatment.
Below will on the basis of the foregoing description, provide the embodiment under several concrete scene of the present invention.Need illustrate that those embodiment only are used to understand the present invention, are not limited to protection scope of the present invention.And the technical characterictic that in identical or different embodiment, occurs can make up use under not conflicting situation.
Embodiment 1:
Present embodiment discloses a kind of high-energy and has injected the method that forms the germanium on insulator structure deeply.Fig. 2 a-Fig. 2 d is that present embodiment forms the chip architecture sketch map after each step of execution in the composite functional material structural approach.As shown in the figure, present embodiment comprises the steps:
Step S202:He ion injects and acts on donor wafer Ge sheet 102, and dosage is 1 * 10 16, energy is 500KeV, and the H ion injects and acts on the Ge wafer, and dosage is 3 * 10 16Cm -2, the injection energy is 300KeV, control H ion and He ion inject projected range at 2100nm, and around this projected range, form vulnerable areas 20, shown in Fig. 2 a;
Step S204: on substrate wafer Si sheet 202 surfaces with thermal oxidation process growth one deck SiO 2Film 302, thickness is about 80nm, with Si sheet and Ge sheet through standard cleaning technology and ion surface activation, with two wafers Ge-SiO at normal temperatures 2Bonding, shown in Fig. 2 b, this SiO 2Film is as insulating barrier or bonding resilient coating;
Step S206: the structure heat treatment of annealing behind the para-linkage; First step annealing temperature is 150 ℃; Annealing time is 60 hours; In order to strengthen bond strength; The second step annealing temperature is 300 ℃, and the time is 40 hours, makes Ge sheet 102 peel off in vulnerable areas 20; Thickness is that the Ge thin layer 102 of 2100nm is transferred on the Si sheet 202, shown in Fig. 2 c;
Step S208:, obtain desired germanium on insulator structure and remaining Ge sheet through subsequent treatment, shown in Fig. 2 d for Ge after peeling off and the substrate Si wafer that contains the Ge laminate structure.
Embodiment 2:
Present embodiment discloses LaAlO on a kind of formation insulator 3The method of laminate structure.Fig. 3 a-Fig. 3 d is that present embodiment forms the chip architecture sketch map after each step of execution in the composite functional material structural approach.As shown in the figure, present embodiment comprises the steps:
Step S302:H ion injects and acts on LaAlO 3Wafer 103, dosage are 2 * 10 17Cm -2, the injection energy is 60KeV, the control ion injects projected range at 500nm, and around this projected range, forms vulnerable areas 30, shown in Fig. 3 a;
Step S304: with LaAlO 3Wafer 103 and glass (glass) 203 is through cleaning and the ion surface activation, with two wafer bondings, shown in Fig. 3 b;
Step S306: the structure heat treatment of annealing behind the para-linkage, first step annealing temperature is 250 ℃, and annealing time is 40 hours, and in order to strengthen bond strength, the second step annealing temperature is 400 ℃, and the time is 60 hours, makes LaAlO 3Sheet is peeled off, and thickness is the LaAlO of 500nm 3Thin layer is transferred on glass 203 (glass) sheet, shown in Fig. 3 c;
Step S308: for the LaAlO after peeling off 3With contain LaAlO 3The substrate sheet glass of laminate structure through subsequent treatment, obtains desired structure and residue LaAlO 3Wafer is shown in Fig. 3 d.
Embodiment 3:
Present embodiment discloses a kind of method of the GaN of formation laminate structure.Fig. 4 a-Fig. 4 d is that present embodiment forms the chip architecture sketch map after each step of execution in the composite functional material structural approach.As shown in the figure, present embodiment comprises the steps:
Step S402:H ion injects and acts on donor wafer GaN wafer 104, and dosage is 3 * 10 17Cm -2, energy is 200KeV, the control ion injects projected range at 500nm, and around this projected range, forms vulnerable areas 40, like Fig. 4 a;
Step S404: surperficial with epitaxial growth one deck Al at donor wafer GaN wafer 104 2O 3Film 404, thickness is about 150nm, on substrate wafer Si sheet 204 surface with the grow SiO of a layer thickness 200nm of CVD (chemical vapor deposition) method 2Layer 304 activates through standard cleaning technology and ion surface, will carry out Al with donor wafer 2O 3-SiO 2Bonding, shown in Fig. 4 b, this SiO 2Layer is as insulating barrier or bonding resilient coating;
Step S406: the structure heat treatment of annealing behind the para-linkage, first step annealing temperature is 200 ℃, annealing time is 60 hours, in order to strengthening bond strength, the second step annealing temperature be 250 ℃ 10 -5Carry out under the low vacuum of Pa, the time is 60 hours, makes GaN wafer 104 peel off, and thickness is that the GaN thin layer of 100nm is transferred on the Si sheet 204, shown in Fig. 4 c;
Step S408: for GaN after peeling off and the substrate Si wafer that contains the GaN laminate structure, remove because ion injects formed surface damage through chemical mechanical polish process on the surface, obtains the structure of GaN on the desired insulator, shown in Fig. 4 d.
In sum; The present invention adopts high-octane ion to inject; Control projected range is in farther position, distance surface; Utilize peeling off of wafer top layer; Even under the situation that has minority bonding defective; Also can access better transfer thin layer, thus the efficient that raising is peeled off and the quality and the performance of transfer layer.
Above-described specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain; Institute is understood that; The above only is a specific embodiment of the present invention; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (11)

1. a method that forms the composite functional material structure is characterized in that, comprising:
Steps A, ion flow into the donor wafer top layer, inject the projected range position at ion and form vulnerable areas, and wherein, the energy that said ion injects is between between the 60KeV to 500KeV;
Step B carries out bonding with said donor wafer and substrate wafer, forms the composite construction that comprises donor wafer and substrate wafer;
Step C, the composite construction that forms behind the para-linkage carries out annealing in process, makes donor wafer peel off in vulnerable areas, thereby at substrate wafer surface attachment donor wafer laminate structure, forms the composite functional material structure.
2. method according to claim 1 is characterized in that, in the said steps A, said ion injects projected range between between the 500nm to 5000nm.
3. method according to claim 1 is characterized in that, in the said steps A, the type of said injection ion is a kind of of following type: hydrogen ion injects separately, the helium ion injects separately, hydrogen-helium ion is united injection or boron-hydrogen ion is united injection.
4. method according to claim 3 is characterized in that, in the said steps A, the dosage of said injection ion is between 1 * 10 16To 3 * 10 17Cm -2Between.
5. according to each described method in the claim 1 to 4, it is characterized in that,
Said substrate wafer material is a kind of in the following material: Si, glass, SiC, Ge or III-V compounds of group;
Said donor wafer material is a kind of in the following material: Ge, III-V compounds of group, GaN, AlN, Al 2O 3, ZnO, SiC, BaTiO 3, LaAlO 3Or diamond;
6. method according to claim 5 is characterized in that, saidly also comprises before the step B:
Step B ', in one or more layers intermediate layer of said substrate surface growth, this intermediate layer is as insulating barrier or bonding resilient coating.
7. method according to claim 6 is characterized in that,
The thickness in said intermediate layer is between between the 80nm to 2000nm;
The preparation method in said intermediate layer is thermal oxidation or chemical vapor deposition and epitaxial method.
8. according to each described method in the claim 1 to 4, it is characterized in that, also comprise before the said step C:
Step C ', the composite construction that forms behind the para-linkage carry out preannealing to be handled, to strengthen the intensity of said donor wafer and said substrate wafer bonding.
9. method according to claim 8 is characterized in that,
Among the said step C ', the temperature of said preannealing is between 150 ℃ to 250 ℃; Among the said step C, the temperature of said annealing in process is between 200 ℃ to 400 ℃;
Said preannealing is handled and said annealing in process is carried out in same annealing furnace, and the vacuum ranges that said annealing in process and preannealing are handled is between 10 -5Pa to 10 5Between the Pa.
10. according to each described method in the claim 1 to 4, it is characterized in that, also comprise before the said B:
Step B ", said donor wafer and said substrate wafer are cleaned and surface ion activation processing.
11. according to each described method in the claim 1 to 4, it is characterized in that, also comprise after the said C:
Step D carries out polishing to the substrate wafer that contains the donor wafer laminate structure.
CN2011102856484A 2011-09-23 2011-09-23 Method for forming composite functional material structure Pending CN102347219A (en)

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CN102779902A (en) * 2012-08-08 2012-11-14 天津蓝天太阳科技有限公司 Preparation method of Ge/Si substrate slice for GaAs solar cell
CN105358474A (en) * 2013-06-28 2016-02-24 Soitec公司 Method for producing a composite structure
CN105374664A (en) * 2015-10-23 2016-03-02 中国科学院上海微系统与信息技术研究所 Preparation method of InP film composite substrate
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6833195B1 (en) * 2003-08-13 2004-12-21 Intel Corporation Low temperature germanium transfer
CN102184882A (en) * 2011-04-07 2011-09-14 中国科学院微电子研究所 Method for forming composite functional material structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6833195B1 (en) * 2003-08-13 2004-12-21 Intel Corporation Low temperature germanium transfer
CN102184882A (en) * 2011-04-07 2011-09-14 中国科学院微电子研究所 Method for forming composite functional material structure

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CN105358474A (en) * 2013-06-28 2016-02-24 Soitec公司 Method for producing a composite structure
US9887124B2 (en) 2013-06-28 2018-02-06 Soitec Method for producing a composite structure
CN105358474B (en) * 2013-06-28 2018-02-13 Soitec公司 The manufacturing process of composite construction
CN105374664A (en) * 2015-10-23 2016-03-02 中国科学院上海微系统与信息技术研究所 Preparation method of InP film composite substrate
CN105632894A (en) * 2015-12-30 2016-06-01 东莞市青麦田数码科技有限公司 Method for bonding compound semiconductor and silicon-based semiconductor
CN106711027B (en) * 2017-02-13 2021-01-05 中国科学院上海微系统与信息技术研究所 Wafer bonding method and heterogeneous substrate preparation method
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CN107680899A (en) * 2017-09-14 2018-02-09 西安电子科技大学 Heterogeneous (Ga is prepared based on smart cut technique1‑xAlx)2O3Method
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CN111540684A (en) * 2020-05-11 2020-08-14 中国科学院上海微系统与信息技术研究所 Microelectronic device of diamond-based heterogeneous integrated gallium nitride thin film and transistor and preparation method thereof
CN111900200A (en) * 2020-06-24 2020-11-06 西安交通大学 Diamond-based gallium nitride composite wafer and bonding preparation method thereof
CN116529851A (en) * 2020-12-11 2023-08-01 华为技术有限公司 Epitaxial substrate, preparation method thereof and semiconductor wafer
CN113013033A (en) * 2020-12-21 2021-06-22 上海大学 Ion beam etching method of metal thick film and application thereof
CN113078047A (en) * 2021-03-30 2021-07-06 芜湖启迪半导体有限公司 Bonded Si substrate, preparation method thereof, and method for preparing Si/3C-SiC heterostructure and 3C-SiC film
CN115863149A (en) * 2022-12-12 2023-03-28 中国科学院上海微系统与信息技术研究所 Preparation method of gallium oxide structure
CN115863149B (en) * 2022-12-12 2023-07-21 中国科学院上海微系统与信息技术研究所 Preparation method of gallium oxide structure

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