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CN102270588B - 在半导体管芯周围形成emi屏蔽层的半导体器件和方法 - Google Patents

在半导体管芯周围形成emi屏蔽层的半导体器件和方法 Download PDF

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Publication number
CN102270588B
CN102270588B CN201110147365.3A CN201110147365A CN102270588B CN 102270588 B CN102270588 B CN 102270588B CN 201110147365 A CN201110147365 A CN 201110147365A CN 102270588 B CN102270588 B CN 102270588B
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China
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sealant
semiconductor element
layer
conductive material
interconnection structure
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CN102270588A (zh
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R.A.帕盖拉
F.卡森
尹胜煜
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及在半导体管芯周围形成EMI屏蔽层的半导体器件和方法。半导体器件具有安装在临时载体上形成的界面层上的多个第一半导体管芯。密封剂沉积在第一管芯和载体上。平坦的屏蔽层在密封剂上形成。穿过屏蔽层和密封剂下至界面层而形成沟道。导电层沉积在沟道中且电连接到屏蔽层。界面层和载体被去除。互连结构在导电材料、密封剂和第一管芯上形成。导电材料通过互连结构而电连接到接地点。导电材料被分割以分离第一管芯。第二半导体管芯可以安装在第一管芯上，使得屏蔽层覆盖第二管芯且导电材料环绕第二管芯或第一和第二管芯。

Description

在半导体管芯周围形成EMI屏蔽层的半导体器件和方法
技术领域
本发明一般涉及半导体器件，且更具体而言，涉及在半导体管芯周围使用导电材料形成EMI和RFI屏蔽层的半导体器件和方法。
背景技术
常常在现代电子产品中存在半导体器件。半导体器件在电组件的数目和密度方面有变化。分立的半导体器件一般包含一种类型的电组件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件典型地包含几百到几百万的电组件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池以及数字微镜器件（DMD）。
半导体器件执行各种的功能，诸如高速计算、发射和接收电磁信号、控制电子器件、将太阳光变换为电力以及产生用于电视显示的视觉投影。在娱乐、通信、功率转换、网络、计算机以及消费产品的领域中存在半导体器件。还在军事应用、航空、汽车、工业控制和办公设备中存在半导体器件。
半导体器件利用半导体材料的电属性。半导体材料的原子结构允许通过施加电场或基电流（basecurrent）或通过掺杂工艺而操纵其导电性。掺杂向半导体材料引入杂质以操纵和控制半导体器件的导电性。
半导体器件包含有源和无源电结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂水平和施加电场或基电流，晶体管要么促进要么限制电流的流动。包括电阻器、电容器和电感器的无源结构创建为执行各种电功能所必须的电压和电流之间的关系。无源和有源结构被电连接以形成电路，这使得半导体器件能够执行高速计算和其他有用功能。
半导体器件一般使用两个复杂的制造工艺来制造，即，前端制造和后端制造，每一个可能涉及成百个步骤。前端制造涉及在半导体晶片的表面上形成多个管芯。每个管芯典型地相同且包含通过电连接有源和无源组件而形成的电路。后端制造涉及从完成的晶片分割（singulate）各个管芯且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目的是生产较小的半导体器件。较小的器件典型地消耗较少的功率、具有较高的性能且可以更高效地生产。另外，较小的半导体器件具有较小的占位面积，这对于较小的终端产品而言是希望的。较小的管芯尺寸可以通过前端工艺中的改进来获得，该前端工艺中的改进导致管芯具有较小、较高密度的有源和无源组件。后端工艺可以通过电互连和封装材料中的改进而导致具有较小占位面积的半导体器件封装。
半导体制造的另一目的是生产较高性能的半导体器件。器件性能的增加可以通过形成能够以较高速度操作的有源组件来实现。在诸如射频（RF）无线通信的高频应用中，集成无源器件（IPD）通常被包含在半导体器件中。IPD的示例包括电阻器、电容器和电感器。典型的RF系统要求在一个或更多半导体封装中的多个IPD以执行必要的电功能。然而，高频电器件产生或者经历不希望的电场干扰（EMI）和射频干扰（RFI）或者其他诸如电容性、电感性或导电耦合的器件间干扰（也称为串扰），这可能干扰器件的操作。
发明内容
存在对使半导体管芯与EMI、RFI和其他器件间干扰隔离的需求。因此，在一个实施例中，本发明是一种制作半导体器件的方法，其包含以下步骤：提供被界面层覆盖的临时载体，在界面层上安装多个第一半导体管芯，在第一半导体管芯和临时载体上沉积密封剂，在密封剂上形成平坦的屏蔽层，形成穿过平坦的屏蔽层和密封剂下至界面层的沟道，在沟道中沉积电连接到平坦的屏蔽层的导电材料，去除界面层和临时载体，在导电材料、密封剂和第一半导体管芯上形成互连结构，以及分割导电材料以分离第一半导体管芯。导电材料电连接到互连结构。
在另一实施例中，本发明是一种制作半导体器件的方法，其包含以下步骤：提供载体，在载体上安装第一半导体管芯，在第一半导体管芯和载体上沉积第一密封剂，在第一密封剂上形成屏蔽层，形成穿过屏蔽层和第一密封剂下至载体的沟道，在沟道中沉积电连接到屏蔽层的导电材料，去除载体，以及在导电材料、第一密封剂和第一半导体管芯上形成第一互连结构。导电材料电连接到第一互连结构。
在另一实施例中，本发明是一种制作半导体器件的方法，其包含以下步骤：提供第一半导体管芯，在第一半导体管芯上沉积第一密封剂，在第一密封剂上形成屏蔽层，形成穿过屏蔽层和第一密封剂的沟道，在沟道中沉积电连接到屏蔽层的导电材料，以及在导电材料、第一密封剂和第一半导体管芯上形成第一互连结构。
在另一实施例中，本发明是一种半导体器件，其包含：第一半导体管芯和沉积在第一半导体管芯上的第一密封剂。屏蔽层在第一密封剂上形成。沟道穿过屏蔽层和第一密封剂形成。导电材料沉积在沟道中，电连接到屏蔽层。第一互连结构在导电材料、第一密封剂和第一半导体管芯上形成。
附图说明
图1说明具有安装到其表面的不同类型封装的PCB；
图2a-2c说明安装到PCB的代表性半导体封装的进一步细节；
图3a-3k说明在半导体管芯周围使用导电材料形成EMI和RFI屏蔽层的工艺；
图4说明具有在半导体管芯周围形成的屏蔽层和导电材料的FO-WLCSP；
图5说明在互连结构中向下延伸至水平导电层的导电材料；
图6说明在密封剂终止且从密封剂露出的导电材料；
图7说明并排的半导体管芯，每个管芯被屏蔽层覆盖且被导电材料环绕；
图8说明具有在层叠的半导体管芯周围形成的屏蔽层和导电材料的另一实施例；以及
图9说明在上半导体管芯周围终止的导电材料。
具体实施方式
在下面的描述中，参考附图以一个或更多实施例描述本发明，在所述附图中相似的标号代表相同或类似的元件。尽管在用于实现本发明目的的最佳模式方面描述本发明，但是本领域技术人员将理解，其旨在覆盖可以包括在如下面的公开和附图所支持的所附权利要求及其等价物的本发明的精神和范围内的备选、修改和等价物。
半导体器件一般使用两个复杂的制造工艺来制造：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含有源和无源电组件，它们电相连以形成功能电路。诸如晶体管和二极管的有源电组件具有控制电流流动的能力。诸如电容器、电感器、电阻器和变压器的无源电组件创建为执行电路功能所必须的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、蚀刻和平整化的一系列工艺步骤在半导体晶片的表面上形成无源和有源组件。掺杂通过诸如离子注入或热扩散的技术将杂质引入到半导体材料中。掺杂工艺修改了有源器件中半导体材料的导电性，将半导体材料转变为绝缘体、导体，或者响应于电场或基电流而动态地改变半导体材料导电性。晶体管包含不同掺杂类型和程度的区域，其被布置为在必要时使得晶体管能够在施加电场或基电流时促进或限制电流流动。
通过具有不同电属性的材料层形成有源和无源组件。这些层可以通过由被沉积的材料类型部分地确定的各种沉积技术来形成。例如，薄膜沉积可能涉及化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀和化学镀工艺。每一层一般被图案化以形成有源组件、无源组件、或组件之间的电连接的部分。
可以使用光刻对层进行图案化，该光刻涉及例如光刻胶的光敏材料在待被图案化的层上的沉积。使用光，图案从光掩模转印到光刻胶。受光影响的光刻胶图案的部分使用溶剂去除，露出待被图案化的底层的部分。光刻胶的剩余部分被去除，留下图案化层。备选地，使用诸如化学镀和电解电镀这样的技术，一些类型的材料通过直接向由原先沉积/蚀刻工艺形成的区域或通孔沉积材料而被图案化。
在现有图案上沉积材料的薄膜可以放大底层图案且形成不均匀的平坦表面。需要均匀的平坦表面来生产更小且更致密堆叠的有源和无源组件。平整化可以用于从晶片的表面去除材料且产生均匀的平坦表面。平整化涉及使用抛光垫对晶片的表面进行抛光。研磨材料和腐蚀化学物在抛光期间被添加到晶片的表面。化学物的研磨和腐蚀动作的组合机械动作去除任意不规则拓扑，导致均匀的平坦表面。
后端制造指将完成的晶片切割或分割为各个管芯且然后封装管芯以用于结构支撑和环境隔离。为了分割管芯，晶片沿着称为切割线或划线的晶片的非功能区域被划片且折断。使用激光切割工具或锯条来分割晶片。在分割之后，各个管芯被安装到封装基板，该封装基板包括引脚或接触焊盘以用于与其他系统组件互连。在半导体管芯上形成的接触焊盘然后连接到封装内的接触焊盘。电连接可以使用焊料凸点、柱形凸点、导电胶或引线接合来制成。密封剂或其他成型材料沉积在封装上以提供物理支撑和电隔离。然后把完成的封装插入到电系统中且使半导体器件的功能性对于其他系统组件可用。
图1说明具有芯片载体基板或印刷电路板（PCB）52的电子器件50，该芯片载体基板或印刷电路板（PCB）52具有安装在其表面上的多个半导体封装。取决于应用，电子器件50可以具有一种类型的半导体封装或多种类型的半导体封装。用于说明性目的，在图1中示出了不同类型的半导体封装。
电子器件50可以是使用半导体封装以执行一个或更多电功能的独立系统。备选地，电子器件50可以是较大系统的子组件。例如，电子器件50可以是蜂窝电话、个人数字助理（PDA）、数码摄像机（DVC）或其他电子通信器件的一部分。备选地，电子器件50可以是图形卡、网络接口卡或可以被插入到计算机中的其他信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件或其他半导体管芯或电组件。微型化和重量减小对于这些产品被市场接受而言是必须的。半导体器件之间的距离必须减小以实现更高的密度。
在图1中，PCB52提供用于安装到PCB上的半导体封装的结构支撑和电互连的一般基板。使用蒸发、电解电镀、化学镀、丝网印刷或者其他合适的金属沉积工艺，导电信号迹线54在PCB的表面上或在PCB的层内形成。信号迹线54提供每一个半导体封装、安装的组件以及其他外部系统组件之间的电通信。迹线54还向半导体封装中的每一个提供功率和接地连接。
在一些实施例中，半导体器件具有两个封装级别。第一级封装是用于机械和电附接半导体管芯到中间载体的技术。第二级封装涉及机械和电附接中间载体到PCB。在其他实施例中，半导体器件可以仅具有第一级封装，其中管芯被直接机械和电地安装到PCB。
用于说明目的，在PCB52上示出包括引线接合封装56和倒装芯片58的若干类型的第一级封装。另外，示出在PCB52上安装的若干类型的第二级封装，包括球栅阵列（BGA）60、凸点芯片载体（BCC）62、双列直插式封装（DIP）64、栅格阵列封装（LGA）66、多芯片模块（MCM）68、四方扁平无引脚封装（QFN）72以及四方扁平封装72。取决于系统需求，使用第一和第二级封装型式的任意组合配置的半导体封装以及其他电子组件的任意组合可以连接到PCB52。在一些实施例中，电子器件50包括单一附接的半导体封装，而其他实施例需要多个互连封装。通过在单个基板上组合一个或更多半导体封装，制造商可以将预制组件结合到电子器件和系统中。因为半导体封装包括复杂的功能性，可以使用较廉价的组件和流水线制造工艺来制造电子器件。所得到的器件较不可能发生故障且对于制造而言较不昂贵，导致针对消费者的较低成本。
图2a-2c示出示例性半导体封装。图2a示出安装在PCB52上的DIP64的进一步细节。半导体管芯74包括有源区域，该有源区域包含实现为根据管芯的电设计在管芯内形成且电互连的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及在半导体管芯74的有源区域内形成的其他电路元件。接触焊盘76是诸如铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）或银（Ag）的一层或多层导电材料，且电连接到半导体管芯74内形成的电路元件。在DIP64的组装期间，半导体管芯74使用金-硅共熔层或者诸如热树脂或环氧树脂的粘合剂材料而安装到中间载体78。封装体包括诸如聚合物或陶瓷的绝缘封装材料。导线80和引线接合82提供半导体管芯74和PCB52之间的电互连。密封剂84沉积在封装上以通过防止湿气和颗粒进入封装和污染管芯74或引线接合82而进行环境保护。
图2b说明安装在PCB52上的BCC62的进一步细节。半导体管芯88使用底层填料或者环氧树脂粘合剂材料92安装在载体90上。引线接合94提供接触焊盘96和98之间的第一级封装互连。成型化合物或密封剂100沉积在半导体管芯88和引线接合94上，从而为器件提供物理支撑和电隔离。接触焊盘102使用诸如电解电镀或化学镀之类的合适的金属沉积工艺而在PCB52的表面上形成以防止氧化。接触焊盘102电连接到PCB52中的一个或更多导电信号迹线54。凸点104在BCC62的接触焊盘98和PCB52的接触焊盘102之间形成。
在图2c中，使用倒装芯片型式第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区域108包含实现为根据管芯的电设计而形成的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及有源区域108内的其他电路元件。半导体管芯58通过凸点110电和机械连接到载体106。
使用利用凸点112的BGA型式第二级封装，BGA60电且机械连接到PCB52。半导体管芯58通过凸点110、信号线114和凸点112而电连接到PCB52中的导电信号迹线54。成型化合物或密封剂116被沉积在半导体管芯58和载体106上以提供用于器件的物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB52上的导电迹线的短导电路径以便减小信号传播距离、降低电容且改善整体电路性能。在另一个实施例中，半导体管芯58可以使用倒装芯片型式第一级封装机械和电地直接连接到PCB52而不使用中间载体106。
与图1和2a-2c相关，图3a-3k说明在半导体管芯周围使用导电材料形成EMI和RFI屏蔽层的工艺。在图3a中，临时载体或基板120包含牺牲基底材料，诸如硅、聚合物、聚合物复合物、金属、陶瓷、玻璃、玻璃环氧物、氧化铍或其他合适的用于结构支撑的低成本、刚性材料或体半导体材料。可选的界面层122可以在载体120上形成作为临时粘合剂接合膜或蚀刻停止层。
图3b示出具有使用拾放操作而安装到界面层122的多个半导体管芯或组件124的载体120的一部分。在半导体管芯124的有源表面128上形成的接触焊盘126朝向载体120定向。有源表面128包含实现为根据管芯的电设计和功能在管芯内形成且电互连的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多个晶体管、二极管、以及在有源表面128内形成的其他电路元件以实施诸如数字信号处理（DSP）、ASIC、存储器或其他信号处理电路之类的模拟电路或数字电路。半导体管芯124还可以包含诸如电感器、电容器和电阻器的IPD以用于RF信号处理。在一个实施例中，半导体管芯124是倒装芯片类型半导体管芯。图3c示出具有安装到载体120上的界面层122的有源表面128的所有半导体管芯124。
在图3d中，使用膏印、压塑成型、转印成型、液封成型、真空压合、旋涂或其他合适的涂敷器，密封剂或成型化合物130沉积到半导体管芯124和载体120上。密封剂130可以是聚合物复合材料，诸如具有填充剂的环氧树脂、具有填充剂的环氧丙烯酸脂或具有适当填充剂的聚合物。密封剂130是不导电的且环境地保护半导体器件以免受外部元件和污染物的影响。
半导体管芯124可以包含产生EMI、RIF或诸如电容性、电感性或导电耦合的其他器件间干扰的基带电路。在其他实施例中，半导体管芯124包含易受EMI、RIF和器件间干扰的IPD。例如，包含在半导体管芯124内的IPD提供高频应用所需的电特性，诸如谐振器、高通滤波器、低通滤波器、带通滤波器、对称高Q谐振变压器以及调谐电容器。IPD可以用作可以布置在天线和收发器之间的前端无线RF组件。IPD电感器可以是高达100GHz操作的高Q平衡-不平衡变换器、变压器或线圈。在一些应用中，多个平衡-不平衡变换器在相同的基板上形成，允许多频带操作。例如，两个或更多平衡-不平衡变换器用在用于移动电话或其他全球移动系统（GSM）通信的4频中，每个平衡-不平衡变换器专用于4频器件的一个操作频带。典型的RF系统要求在一个或更多半导体封装中的多个IPD和其他高频电路执行必要的电功能。
为了减小EMI和RFI的影响，屏蔽层132共型地沉积在密封剂130与载体120相对的顶表面131上，如图3e所示。屏蔽层132在密封剂130的顶表面131上基本平坦。在形成屏蔽层132之前，可选的种子层133共型地沉积在密封剂130的顶表面131上。屏蔽层132可以是Al、铁素体或羰基铁、不锈钢、镍银、低碳钢、硅铁钢、箔、导电树脂以及能够阻隔或吸收EMI、RFI和其他器件间干扰的其他金属和复合物。屏蔽层132还可以是诸如碳黑或铝片的非金属材料以减小EMI和RFI的影响。种子层133可以使用Cu、Ni、镍钒（NiV）、Au或Al来制成。屏蔽层132和种子层133被图案化且使用电解电镀、化学镀、溅射、PVD、CVD或其他合适的金属沉积工艺来共型地沉积。对于非金属材料，可以通过层压、喷涂或喷漆来施加屏蔽层132。
在图3f中，使用锯条或激光切割工具136，穿过半导体管芯124之间的屏蔽层132和密封剂130切割沟道134。沟道134仅向下延伸至界面层122的顶表面（密封剂130和界面结构150之间的边界）或者部分地延伸到界面层122中。沟道134完全环绕半导体管芯124形成，如图3g所示。
在图3h中，导电材料138沉积到沟道134中上至屏蔽层132的水平。导电材料138可以是软焊料、铜、或者导电聚合物。导电材料138构成完全环绕半导体管芯124延伸的EMI屏蔽的侧面部分。导电材料138电连接到屏蔽层132。
在图3i中，临时载体120和界面层122通过化学蚀刻、机械剥离、CMP、机械研磨、热烘烤、激光扫描或湿法脱模（strip）而去除。导电材料138的一部分从密封剂130露出或延伸超出密封剂130。
在图3j中，积层互连结构150在密封剂130和半导体管芯124的有源表面128上形成。积层互连结构150包括使用图案化和诸如溅射、电解电镀以及化学镀之类的金属沉积工艺而形成的导电层或再分配层（RDL）152。导电层152可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一层或更多层。导电层152a电连接到接触焊盘126以用于路由信号。导电层152b电连接到作为低阻抗接地点的导电材料138。导电层152的其他部分根据半导体管芯124的设计和功能而可以是电公用或电隔离的。
积层互连结构150还包括在导电层152之间形成的绝缘或钝化层154以用于电隔离。绝缘层154包含二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）或具有类似绝缘和结构属性的其他材料中的一层或更多层。绝缘层154使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化来形成。绝缘层154的一部分通过蚀刻工艺而去除以露出导电层152，以用于凸点形成或附加封装互连。
在图3k中，使用蒸发、电解电镀、化学镀、球滴或丝网印刷工艺，导电凸点材料沉积在积层互连结构150上且电连接到导电层152。凸点材料可以是具有可选助焊剂溶液（fluxsolution）的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸点材料可以是共熔Sn/Pb、高铅焊料或无铅焊料。凸点材料使用合适的附接或接合工艺而接合到导电层152。在一个实施例中，凸点材料通过加热材料到其熔点之上进行回流以形成圆形球或凸点156。在一些应用中，凸点156第二次回流以改善与导电层152的电接触。凸点下金属化（UBM）可以在凸点156下形成。凸点还可以被压缩接合到导电层152。凸点156代表可以在导电层152上形成的一种类型的互连结构。互连结构也可以使用接合引线、柱形凸点、微凸点或其他电互连。
图3k中示出的半导体器件使用锯条或激光切割工具158穿过导电材料138进行分割以分离各个半导体管芯124。
图4示出分割之后的FO-WLCSP160。半导体管芯124电连接到互连结构150的导电层152a和凸点156。平坦的屏蔽层132准备在密封剂130上形成以阻隔或吸收EMI、RFI和其他器件间干扰。导电材料138提供半导体管芯124侧面周围的EMI覆盖且将EMI、RFI和其他干扰信号路由通过导电层152b和凸点156到外部低阻抗接地点。因此，平坦屏蔽层132和导电材料138提供用于半导体管芯124的顶面和侧面的有效EMI和RFI屏蔽。
图5示出类似于图4的FO-WLCSP162的实施例，其中导电材料138突出或延伸到互连结构150的绝缘层154中以接触基本水平的导电层152b。导电材料138、导电层152b和凸点156将EMI、RFI和其他干扰信号从屏蔽层132路由到外部低阻抗接地点。
图6示出类似于图4的FO-WLCSP164的实施例，其中导电材料138在密封剂130和互连结构150的边界终止但是从其露出，即，没有进入互连结构150的导电材料138的突起或延伸。导电层152b的垂直部分延伸到互连结构150的顶表面以接触导电材料138。导电材料138、导电层152b和凸点156将EMI、RFI和其他干扰信号从屏蔽层132路由到外部低阻抗接地点。
图7示出类似于图4的FO-WLCSP166的实施例，其中并排的半导体管芯124均被屏蔽层132覆盖且被导电材料138环绕。
图8示出具有在有源表面174上形成接触焊盘172的半导体管芯170的另一实施例，该有源表面174包含实现为根据管芯的电设计和功能在管芯内形成且电互连的有源器件、无源器件、导电层和电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管和在有源表面174内形成的其他电路元件以实现诸如DSP、ASIC、存储器或其他信号处理电路的模拟电路或数字电路。半导体管芯170还可以包含诸如电感器、电容器和电阻器的IPD以用于RF信号处理。在一个实施例中，半导体管芯170是倒装类型半导体管芯。半导体管芯170安装到在临时载体上形成的界面层。
使用膏印、压塑成型、转印成型、液封成型、真空压合、旋涂或其他合适的涂敷器，密封剂或成型化合物176沉积在半导体管芯170上。密封剂176可以是聚合物复合材料，诸如具有填充剂的环氧树脂、具有填充剂的环氧丙烯酸脂或具有适当填充剂的聚合物。密封剂176是不导电的且环境地保护半导体器件以免受外部元件和污染物的影响。
使用机械钻孔、激光钻孔或深反应离子蚀刻（DRIE）在半导体管芯170的外围周围形成穿过密封剂176的多个通孔。使用电解电镀、化学镀或其他合适的金属沉积工艺，通孔被填充以Al、Cu、Sn、Ni、Au、Ag、Ti、钨（W）、多晶硅或其他合适的导电材料以形成导电柱或通孔178。备选地，多个柱形凸点或者焊球可以在通孔内形成。
在密封剂176上形成积层互连结构。积层互连结构180包括使用图案化和诸如溅射、电解电镀和化学镀的金属沉积工艺而形成的导电层或RDL182。导电层182可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料中的一层或更多层。导电层182的一部分电连接到导电柱或通孔178以用于路由信号。取决于半导体管芯124的设计和功能，导电层182的其他部分可以是电公用或者电隔离的。
积层互连结构180还包括在导电层182之间形成的绝缘或钝化层184以用于隔离。绝缘层184包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构属性的其它材料中的一层或更多层。绝缘层184使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化来形成。绝缘层184的一部分通过蚀刻工艺而去除以露出导电层182。
半导体管芯190具有在有源表面194上形成的接触焊盘192，该有源表面194包含实现为根据管芯的电设计和功能在管芯内形成且电互连的有源器件、无源器件、导电层和电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管以及在有源表面194内形成的其他电路元件以实现诸如DSP、ASIC、存储器或其他信号处理电路的模拟电路或数字电路。半导体管芯190还包含诸如电感器、电容器和电阻器的IPD以用于RF信号处理。在一个实施例中，半导体管芯190是倒装芯片类型半导体管芯。多个凸点196在接触焊盘192上形成。半导体管芯190安装到互连结构180且使用凸点196而电连接到导电层182。
使用膏印、压塑成型、转印成型、液封成型、真空压合、旋涂或其他合适的涂敷器，密封剂或成型化合物198沉积在半导体管芯190上。密封剂198可以是聚合物复合材料，诸如是具有填充剂的环氧树脂、具有填充剂的环氧丙烯酸脂或具有适当填充剂的聚合物。密封剂198是不导电的且环境地保护半导体器件以免受外部元件和污染物的影响。
半导体管芯170和/或半导体管芯190可以包含产生EMI、RFI或诸如电容性、电感性或导电耦合的其他器件间干扰的基带电路。在其他实施例中，半导体管芯170和/或190包含易于受到EMI、RFI和器件间干扰影响的IPD。例如，包含在半导体管芯170和/或190内的IPD提供高频应用所需的电特性，诸如谐振器、高通滤波器、低通滤波器、带通滤波器、对称高Q谐振变压器以及调谐电容器。IPD可以用作可以布置在天线和收发器之间的前端无线RF组件。IPD电感器可以是高达100GHz操作的高Q平衡-不平衡变换器、变压器或线圈。在一些应用中，在相同的基板上形成多个平衡-不平衡变换器，允许多频带操作。例如，在用于移动电话或其他GSM通信的4频中使用两个或更多平衡-不平衡变换器，每个平衡-不平衡变换器专用于4频器件的一个操作频带。典型的RF系统要求一个或更多半导体封装中的多个IPD和其他高频电路执行必要的电功能。
为了减小EMI和RFI的影响，屏蔽层200共型地沉积在密封剂198和半导体管芯190的顶表面202上。屏蔽层200在密封剂198和半导体管芯的顶表面202上基本是平坦的。在形成屏蔽层200之前，可选的种子层204共型地沉积在密封剂198和半导体管芯190的顶表面202上。屏蔽层200可以是Al、铁素体或羰基铁、不锈钢、镍银、低碳钢、硅铁钢、箔、导电树脂以及能够阻隔或吸收EMI、RFI和其他器件间干扰的其他金属和复合物。屏蔽层200还可以是诸如碳黑或铝片的非金属材料以减小EMI和RFI的影响。种子层204可以使用Cu、Ni、NiV、Au或Al制成。使用电解电镀、化学镀、溅射、PVD、CVD或其他合适的金属沉积工艺，屏蔽层200和种子层204被图案化且共型地沉积。对于非金属材料，可以通过层压、喷涂或喷漆来施加屏蔽层200。
使用锯条或激光切割工具，穿过屏蔽层200、密封剂198、互连结构180以及密封剂176来切割沟道。沟道仅向下延伸至界面层的顶表面（密封剂176和界面结构210之间的边界）或者部分地延伸到界面层中。沟道完全环绕半导体管芯170和190形成。
导电材料208沉积到沟道中上至屏蔽层200的水平。导电材料208可以是软焊料、铜、或者导电聚合物。导电材料208构成完全环绕半导体管芯170和190延伸的EMI屏蔽的侧面部分。导电材料208电连接到屏蔽层200。
临时载体和界面层通过化学蚀刻、机械剥离、CMP、机械研磨、热烘烤、激光扫描或湿法脱模来去除。导电材料208的一部分从密封剂176露出或延伸超出密封剂176。
积层互连结构210在密封剂176和半导体管芯170的有源表面174上形成。积层互连结构210包括使用图案化和诸如溅射、电解电镀以及化学镀之类的金属沉积工艺而形成的导电层或RDL212。导电层212可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一层或更多层。导电层212a电连接到接触焊盘172以用于路由信号。导电层212b电连接到作为低阻抗接地点的导电材料208。导电层212的其他部分根据半导体管芯170和190的设计和功能可以是电公用或电隔离的。
积层互连结构210还包括在导电层212之间形成的绝缘或钝化层214以用于电隔离。绝缘层214包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构属性的其他材料中的一层或更多层。绝缘层214使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化来形成。绝缘层214的一部分通过蚀刻工艺而去除以露出导电层212，以用于凸点形成或附加封装互连。
使用蒸发、电解电镀、化学镀、球滴或丝网印刷工艺，导电凸点材料沉积在积层互连结构210上且电连接到导电层212。凸点材料可以是具有可选助焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸点材料可以是共熔Sn/Pb、高铅焊料或无铅焊料。凸点材料使用合适的附接或接合工艺而接合到导电层212。在一个实施例中，凸点材料通过加热材料到其熔点之上进行回流以形成球形球或凸点216。在一些应用中，凸点216第二次回流以改善与导电层212的电接触。UBM可以在凸点216下形成。凸点还可以被压缩接合到导电层212。凸点216代表可以在导电层212上形成的一种类型的互连结构。互连结构也可以使用接合引线、柱形凸点、微凸点或其他电互连。
在FO-WLCSP220中，半导体管芯170电连接到互连结构210的导电层212a和凸点216。半导体管芯190通过凸点196、导电层182、导电柱或通孔178以及导电层212而电连接到半导体管芯170和凸点216。平坦的屏蔽层200准备在半导体管芯170和190上形成以阻隔或吸收EMI、RFI和其他器件间干扰。导电材料208提供半导体管芯170和190的侧面周围的EMI和RFI屏蔽且路由EMI、RFI和其他干扰信号通过导电层212b和凸点216到外部低阻抗接地点。因此，平坦的屏蔽层200和导电材料208提供用于半导体管芯170和190的顶面和侧面的有效EMI和RFI屏蔽。
图9示出类似于图7的实施例，其中导电材料208仅在密封剂198和半导体管芯190周围形成。导电材料208终止在互连结构180。屏蔽层200和导电材料208通过导电层182b、导电柱或通孔178、导电层212以及凸点216接地。
尽管已经详细描述了本发明的一个或更多实施例，本领域技术人员将意识到，可以在不偏离所附权利要求阐述的本发明的范围的情况下对那些实施例做出修改和改写。

Claims (16)

1.一种制作半导体器件的方法，包含：
提供界面层；
在所述界面层上设置第一半导体管芯；
在该第一半导体管芯上沉积第一密封剂；
在该第一密封剂上形成屏蔽层；
形成穿过该屏蔽层和第一密封剂以及部分穿过所述界面层的沟道，所述沟道穿透所述界面层的第一表面，同时让所述界面层的第二表面与未受影响的所述第一表面相对；
在沟道中沉积从该屏蔽层延伸越过所述第一密封剂的表面且部分地通过所述界面层的导电材料；
去除所述界面层以暴露所述第一密封剂的表面以及所述导电材料延伸越过所述第一密封剂的表面；以及
在去除所述界面层之后，在该导电材料、第一密封剂和第一半导体管芯上通过（a）形成与延伸越过所述第一密封剂的表面的所暴露的导电材料、第一密封剂的所述表面、以及第一半导体管芯接触的再分配层，以及（b）在所述再分配层上形成绝缘层来形成第一互连结构。
2.根据权利要求1所述的方法，其中该导电材料延伸到该第一互连结构中。
3.根据权利要求1所述的方法，还包括通过该第一互连结构电连接该导电材料到接地点。
4.根据权利要求1所述的方法，还包括：
形成穿过该第一密封剂的导电通孔；
在该第一密封剂上形成与第一互连结构相对的第二互连结构；以及
在该第二互连结构上设置第二半导体管芯。
5.根据权利要求4所述的方法，还包括：
在该第二半导体管芯上沉积第二密封剂；以及
在该第二密封剂上形成该屏蔽层，其中该导电材料环绕该第一和第二半导体管芯。
6.一种制作半导体器件的方法，包含：
提供临时界面层；
在所述临时界面层上设置第一半导体管芯；
在该第一半导体管芯上沉积第一密封剂；
在该第一密封剂上形成屏蔽层；
形成穿过该屏蔽层和第一密封剂的沟道；
在沟道中沉积电连接到该屏蔽层的导电材料，包括形成终止在临时界面层处的所述导电材料的端部；
去除所述临时界面层以露出所述第一密封剂以及所述导电材料的端部；
以及
在去除所述临时界面层之后，通过如下步骤形成第一互连结构：
a）形成包括与所述半导体管芯的接触焊盘接触的第一部分及与所述导电材料所露出的端部接触的第二部分的导电层，所述导电层的所述第二部分用作接地点；以及
b）在所述第一半导体管芯与所述导电层上形成绝缘层。
7.根据权利要求6所述的方法，其中该导电材料电连接到该第一互连结构。
8.根据权利要求6所述的方法，其中该导电材料延伸到该第一互连结构中。
9.根据权利要求6所述的方法，其中该导电材料终止在该第一密封剂和第一互连结构之间的边界处。
10.根据权利要求6所述的方法，还包括：
形成穿过该第一密封剂的导电通孔；
在该第一密封剂上形成与所述第一互连结构相对的第二互连结构；以及
在该第二互连结构上设置第二半导体管芯。
11.根据权利要求10所述的方法，还包括：
在该第二半导体管芯上沉积第二密封剂；以及
在该第二密封剂上形成该屏蔽层，其中该导电材料环绕该第一半导体管芯该以及第二半导体管芯。
12.一种半导体器件，包含：
第一半导体管芯；
第一密封剂，其沉积在该第一半导体管芯上；
导电通孔，其穿过所述第一密封剂形成；
第一互连结构，其包括在所述第一密封剂与导电通孔上形成的第一再分配层；
第二半导体管芯，其设置在所述第一互连结构上并与所述第一半导体管芯相对；
沉积在所述第二半导体管芯上的第二密封剂；
屏蔽层，其在该第二密封剂上形成；
沟道，其穿过该屏蔽层和第二密封剂而形成；
导电材料，其沉积在沟道中，电连接到该屏蔽层；以及
形成在所述第一半导体管芯上的第二互连结构，其包括（a）形成在所述导电通孔、第一密封剂与第一半导体管芯上的第二再分配层，（b）形成在所述第二再分配层上的绝缘层，以及（c）形成在所述第二再分配层上的绝缘层中的开口。
13.权利要求12所述的半导体器件，其中该导电材料电连接到该第二互连结构。
14.根据权利要求12所述的半导体器件，其中该导电材料通过该第二互连结构电连接到接地点。
15.根据权利要求12所述的半导体器件，还包括：
导电通孔，其穿过该第一密封剂而形成；
第二互连结构，其在该第一密封剂上形成；以及
第二半导体管芯，其设置在该第二互连结构上。
16.根据权利要求15所述的半导体器件，还包括：
第二密封剂，其沉积在该第二半导体管芯上，其中该屏蔽层在该第二密封剂上形成且该导电材料环绕该第二半导体管芯。
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